drm-uapi: Update drm_fourcc.h for new TGL modifier
Pull in the header from drm-next commit 32c3d9b0f51ee1e6bb0160496b97e50b5caca4d0. Among other things, this brings in the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
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Nanley Chery
Marge Bot
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7a69942d29
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@ -58,6 +58,30 @@ extern "C" {
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* may preserve meaning - such as number of planes - from the fourcc code,
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* whereas others may not.
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*
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* Modifiers must uniquely encode buffer layout. In other words, a buffer must
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* match only a single modifier. A modifier must not be a subset of layouts of
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* another modifier. For instance, it's incorrect to encode pitch alignment in
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* a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
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* aligned modifier. That said, modifiers can have implicit minimal
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* requirements.
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*
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* For modifiers where the combination of fourcc code and modifier can alias,
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* a canonical pair needs to be defined and used by all drivers. Preferred
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* combinations are also encouraged where all combinations might lead to
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* confusion and unnecessarily reduced interoperability. An example for the
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* latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
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*
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* There are two kinds of modifier users:
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*
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* - Kernel and user-space drivers: for drivers it's important that modifiers
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* don't alias, otherwise two drivers might support the same format but use
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* different aliases, preventing them from sharing buffers in an efficient
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* format.
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* - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
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* see modifiers as opaque tokens they can check for equality and intersect.
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* These users musn't need to know to reason about the modifier value
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* (i.e. they are not expected to extract information out of the modifier).
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*
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* Vendors should document their modifier usage in as much detail as
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* possible, to ensure maximum compatibility across devices, drivers and
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* applications.
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@ -155,6 +179,12 @@ extern "C" {
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#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
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#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
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/*
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* RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
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* of unused padding per component:
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*/
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#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
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/* packed YCbCr */
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#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
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#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
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@ -320,7 +350,6 @@ extern "C" {
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*/
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/* Vendor Ids: */
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#define DRM_FORMAT_MOD_NONE 0
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#define DRM_FORMAT_MOD_VENDOR_NONE 0
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#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
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#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
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@ -392,6 +421,16 @@ extern "C" {
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*/
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#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
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/*
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* Deprecated: use DRM_FORMAT_MOD_LINEAR instead
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*
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* The "none" format modifier doesn't actually mean that the modifier is
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* implicit, instead it means that the layout is linear. Whether modifiers are
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* used is out-of-band information carried in an API-specific way (e.g. in a
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* flag for drm_mode_fb_cmd2).
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*/
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#define DRM_FORMAT_MOD_NONE 0
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/* Intel framebuffer modifiers */
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/*
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@ -488,6 +527,25 @@ extern "C" {
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*/
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#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
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/*
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* Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
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* compression.
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*
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* The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
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* and at index 1. The clear color is stored at index 2, and the pitch should
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* be ignored. The clear color structure is 256 bits. The first 128 bits
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* represents Raw Clear Color Red, Green, Blue and Alpha color each represented
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* by 32 bits. The raw clear color is consumed by the 3d engine and generates
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* the converted clear color of size 64 bits. The first 32 bits store the Lower
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* Converted Clear Color value and the next 32 bits store the Higher Converted
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* Clear Color value when applicable. The Converted Clear Color values are
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* consumed by the DE. The last 64 bits are used to store Color Discard Enable
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* and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
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* corresponds to an area of 4x1 tiles in the main surface. The main surface
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* pitch is required to be a multiple of 4 tile widths.
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*/
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#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
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/*
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* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
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*
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@ -671,7 +729,7 @@ extern "C" {
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* which corresponds to the "generic" kind used for simple single-sample
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* uncompressed color formats on Fermi - Volta GPUs.
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*/
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static __inline__ __u64
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static inline __u64
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drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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{
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if (!(modifier & 0x10) || (modifier & (0xff << 12)))
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@ -997,9 +1055,9 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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* Not all combinations are valid, and different SoCs may support different
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* combinations of layout and options.
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*/
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#define __fourcc_mod_amlogic_layout_mask 0xf
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#define __fourcc_mod_amlogic_layout_mask 0xff
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#define __fourcc_mod_amlogic_options_shift 8
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#define __fourcc_mod_amlogic_options_mask 0xf
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#define __fourcc_mod_amlogic_options_mask 0xff
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#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
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fourcc_mod_code(AMLOGIC, \
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@ -1073,9 +1131,27 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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* - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
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* - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
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*
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* For formats with multiple format planes (e.g. NV12) all planes for a given
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* format plane are packed together in a single memory plane based on the
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* required alignments.
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* For multi-plane formats the above surfaces get merged into one plane for
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* each format plane, based on the required alignment only.
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*
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* Bits Parameter Notes
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* ----- ------------------------ ---------------------------------------------
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*
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* 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_*
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* 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
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* 13 DCC
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* 14 DCC_RETILE
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* 15 DCC_PIPE_ALIGN
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* 16 DCC_INDEPENDENT_64B
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* 17 DCC_INDEPENDENT_128B
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* 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
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* 20 DCC_CONSTANT_ENCODE
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* 23:21 PIPE_XOR_BITS Only for some chips
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* 26:24 BANK_XOR_BITS Only for some chips
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* 29:27 PACKERS Only for some chips
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* 32:30 RB Only for some chips
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* 35:33 PIPE Only for some chips
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* 55:36 - Reserved for future use, must be zero
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*/
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#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
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@ -1158,7 +1234,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
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#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
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#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
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#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */
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#define AMD_FMT_MOD_PACKERS_SHIFT 27
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#define AMD_FMT_MOD_PACKERS_MASK 0x7
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#define AMD_FMT_MOD_RB_SHIFT 30
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#define AMD_FMT_MOD_RB_MASK 0x7
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