KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

genxml: Add L3 Cache Control register definitions 

Based on intel_reg.h (5912da45a6)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Jordan Justen 2016-03-24 00:29:50 -07:00
parent d353ba8f5f
commit 7a03fb9ccb
4 changed files with 69 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
src/intel/genxml/gen7.xml
View File

@ -2508,4 +2508,31 @@
<field name="SW Tessellation Memory Object Control State" start="40" end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
</instruction>
<register name="L3SQCREG1" length="1" num="0xb010">
<field name="Convert DC_UC" start="24" end="24" type="uint"/>
<field name="Convert IS_UC" start="25" end="25" type="uint"/>
<field name="Convert C_UC" start="26" end="26" type="uint"/>
<field name="Convert T_UC" start="27" end="27" type="uint"/>
</register>
<register name="L3CNTLREG2" length="1" num="0xb020">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="6" type="uint"/>
<field name="URB Low Bandwidth" start="7" end="7" type="uint"/>
<field name="ALL Allocation" start="8" end="13" type="uint"/>
<field name="RO Allocation" start="14" end="19" type="uint"/>
<field name="RO Low Bandwidth" start="20" end="20" type="uint"/>
<field name="DC Allocation" start="21" end="26" type="uint"/>
<field name="DC Low Bandwidth" start="27" end="27" type="uint"/>
</register>
<register name="L3CNTLREG3" length="1" num="0xb024">
<field name="IS Allocation" start="1" end="6" type="uint"/>
<field name="IS Low Bandwidth" start="7" end="7" type="uint"/>
<field name="C Allocation" start="8" end="13" type="uint"/>
<field name="C Low Bandwidth" start="14" end="14" type="uint"/>
<field name="T Allocation" start="15" end="20" type="uint"/>
<field name="T Low Bandwidth" start="21" end="21" type="uint"/>
</register>
</genxml>

26
src/intel/genxml/gen75.xml
View File

@ -2906,4 +2906,30 @@
<field name="SW Tessellation Memory Object Control State" start="40" end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
</instruction>
<register name="L3SQCREG1" length="1" num="0xb010">
<field name="Convert DC_UC" start="24" end="24" type="uint"/>
<field name="Convert IS_UC" start="25" end="25" type="uint"/>
<field name="Convert C_UC" start="26" end="26" type="uint"/>
<field name="Convert T_UC" start="27" end="27" type="uint"/>
</register>
<register name="L3CNTLREG2" length="1" num="0xb020">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="6" type="uint"/>
<field name="URB Low Bandwidth" start="7" end="7" type="uint"/>
<field name="RO Allocation" start="14" end="19" type="uint"/>
<field name="RO Low Bandwidth" start="20" end="20" type="uint"/>
<field name="DC Allocation" start="21" end="26" type="uint"/>
<field name="DC Low Bandwidth" start="27" end="27" type="uint"/>
</register>
<register name="L3CNTLREG3" length="1" num="0xb024">
<field name="IS Allocation" start="1" end="6" type="uint"/>
<field name="IS Low Bandwidth" start="7" end="7" type="uint"/>
<field name="C Allocation" start="8" end="13" type="uint"/>
<field name="C Low Bandwidth" start="14" end="14" type="uint"/>
<field name="T Allocation" start="15" end="20" type="uint"/>
<field name="T Low Bandwidth" start="21" end="21" type="uint"/>
</register>
</genxml>

8
src/intel/genxml/gen8.xml
View File

@ -3163,4 +3163,12 @@
<field name="SW Tessellation Memory Object Control State" start="40" end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
</instruction>
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
<field name="RO Allocation" start="11" end="17" type="uint"/>
<field name="DC Allocation" start="18" end="24" type="uint"/>
<field name="All Allocation" start="25" end="31" type="uint"/>
</register>
</genxml>

8
src/intel/genxml/gen9.xml
View File

@ -3467,4 +3467,12 @@
<field name="System Instruction Pointer" start="36" end="95" type="offset"/>
</instruction>
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
<field name="RO Allocation" start="11" end="17" type="uint"/>
<field name="DC Allocation" start="18" end="24" type="uint"/>
<field name="All Allocation" start="25" end="31" type="uint"/>
</register>
</genxml>