i965/miptree: Use cpu tiling/detiling when mapping
Rename the (un)map_gtt functions to (un)map_map (map by
returning a map) and add new functions (un)map_tiled_memcpy that
return a shadow buffer populated with the intel_tiled_memcpy
functions.
Tiling/detiling with the cpu will be the only way to handle Yf/Ys
tiling, when support is added for those formats.
v2: Compute extents properly in the x|y-rounded-down case (Chris Wilson)
v3: Add units to parameter names of tile_extents (Nanley Chery)
Use _mesa_align_malloc for the shadow copy (Nanley)
Continue using gtt maps on gen4 (Nanley)
v4: Use streaming_load_memcpy when detiling
v5: (edited by Ken) Move map_tiled_memcpy above map_movntdqa, so it
takes precedence. Add intel_miptree_access_raw, needed after
rebasing on commit b499b85b0f
.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
parent
f5e8b13f78
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@ -31,6 +31,7 @@
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#include "intel_image.h"
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#include "intel_mipmap_tree.h"
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#include "intel_tex.h"
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#include "intel_tiled_memcpy.h"
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#include "intel_blit.h"
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#include "intel_fbo.h"
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@ -3023,7 +3024,7 @@ intel_miptree_unmap_raw(struct intel_mipmap_tree *mt)
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}
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static void
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intel_miptree_unmap_gtt(struct brw_context *brw,
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intel_miptree_unmap_map(struct brw_context *brw,
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struct intel_mipmap_tree *mt,
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struct intel_miptree_map *map,
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unsigned int level, unsigned int slice)
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@ -3032,7 +3033,7 @@ intel_miptree_unmap_gtt(struct brw_context *brw,
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}
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static void
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intel_miptree_map_gtt(struct brw_context *brw,
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intel_miptree_map_map(struct brw_context *brw,
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struct intel_mipmap_tree *mt,
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struct intel_miptree_map *map,
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unsigned int level, unsigned int slice)
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@ -3080,7 +3081,7 @@ intel_miptree_map_gtt(struct brw_context *brw,
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mt, _mesa_get_format_name(mt->format),
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x, y, map->ptr, map->stride);
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map->unmap = intel_miptree_unmap_gtt;
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map->unmap = intel_miptree_unmap_map;
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}
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static void
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@ -3112,6 +3113,94 @@ intel_miptree_unmap_blit(struct brw_context *brw,
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intel_miptree_release(&map->linear_mt);
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}
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/* Compute extent parameters for use with tiled_memcpy functions.
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* xs are in units of bytes and ys are in units of strides.
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*/
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static inline void
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tile_extents(struct intel_mipmap_tree *mt, struct intel_miptree_map *map,
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unsigned int level, unsigned int slice, unsigned int *x1_B,
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unsigned int *x2_B, unsigned int *y1_el, unsigned int *y2_el)
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{
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unsigned int block_width, block_height;
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unsigned int x0_el, y0_el;
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_mesa_get_format_block_size(mt->format, &block_width, &block_height);
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assert(map->x % block_width == 0);
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assert(map->y % block_height == 0);
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intel_miptree_get_image_offset(mt, level, slice, &x0_el, &y0_el);
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*x1_B = (map->x / block_width + x0_el) * mt->cpp;
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*y1_el = map->y / block_height + y0_el;
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*x2_B = (DIV_ROUND_UP(map->x + map->w, block_width) + x0_el) * mt->cpp;
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*y2_el = DIV_ROUND_UP(map->y + map->h, block_height) + y0_el;
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}
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static void
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intel_miptree_unmap_tiled_memcpy(struct brw_context *brw,
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struct intel_mipmap_tree *mt,
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struct intel_miptree_map *map,
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unsigned int level,
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unsigned int slice)
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{
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if (map->mode & GL_MAP_WRITE_BIT) {
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unsigned int x1, x2, y1, y2;
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tile_extents(mt, map, level, slice, &x1, &x2, &y1, &y2);
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char *dst = intel_miptree_map_raw(brw, mt, map->mode | MAP_RAW);
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dst += mt->offset;
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linear_to_tiled(x1, x2, y1, y2, dst, map->ptr, mt->surf.row_pitch,
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map->stride, brw->has_swizzling, mt->surf.tiling, memcpy);
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intel_miptree_unmap_raw(mt);
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}
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_mesa_align_free(map->buffer);
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map->buffer = map->ptr = NULL;
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}
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static void
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intel_miptree_map_tiled_memcpy(struct brw_context *brw,
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struct intel_mipmap_tree *mt,
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struct intel_miptree_map *map,
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unsigned int level, unsigned int slice)
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{
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intel_miptree_access_raw(brw, mt, level, slice,
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map->mode & GL_MAP_WRITE_BIT);
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unsigned int x1, x2, y1, y2;
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tile_extents(mt, map, level, slice, &x1, &x2, &y1, &y2);
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map->stride = ALIGN(_mesa_format_row_stride(mt->format, map->w), 16);
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/* The tiling and detiling functions require that the linear buffer
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* has proper 16-byte alignment (that is, its `x0` is 16-byte
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* aligned). Here we over-allocate the linear buffer by enough
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* bytes to get the proper alignment.
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*/
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map->buffer = _mesa_align_malloc(map->stride * (y2 - y1) + (x1 & 0xf), 16);
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map->ptr = (char *)map->buffer + (x1 & 0xf);
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assert(map->buffer);
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if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
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char *src = intel_miptree_map_raw(brw, mt, map->mode | MAP_RAW);
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src += mt->offset;
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const mem_copy_fn fn =
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#if defined(USE_SSE41)
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cpu_has_sse4_1 ? (mem_copy_fn)_mesa_streaming_load_memcpy :
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#endif
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memcpy;
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tiled_to_linear(x1, x2, y1, y2, map->ptr, src, map->stride,
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mt->surf.row_pitch, brw->has_swizzling, mt->surf.tiling,
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fn);
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intel_miptree_unmap_raw(mt);
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}
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map->unmap = intel_miptree_unmap_tiled_memcpy;
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}
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static void
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intel_miptree_map_blit(struct brw_context *brw,
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struct intel_mipmap_tree *mt,
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@ -3643,6 +3732,7 @@ intel_miptree_map(struct brw_context *brw,
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void **out_ptr,
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ptrdiff_t *out_stride)
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{
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const struct gen_device_info *devinfo = &brw->screen->devinfo;
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struct intel_miptree_map *map;
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assert(mt->surf.samples == 1);
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@ -3663,6 +3753,8 @@ intel_miptree_map(struct brw_context *brw,
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intel_miptree_map_depthstencil(brw, mt, map, level, slice);
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} else if (use_intel_mipree_map_blit(brw, mt, mode, level, slice)) {
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intel_miptree_map_blit(brw, mt, map, level, slice);
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} else if (mt->surf.tiling != ISL_TILING_LINEAR && devinfo->gen > 4) {
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intel_miptree_map_tiled_memcpy(brw, mt, map, level, slice);
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#if defined(USE_SSE41)
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} else if (!(mode & GL_MAP_WRITE_BIT) &&
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!mt->compressed && cpu_has_sse4_1 &&
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@ -3670,7 +3762,9 @@ intel_miptree_map(struct brw_context *brw,
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intel_miptree_map_movntdqa(brw, mt, map, level, slice);
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#endif
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} else {
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intel_miptree_map_gtt(brw, mt, map, level, slice);
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if (mt->surf.tiling != ISL_TILING_LINEAR)
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perf_debug("intel_miptree_map: mapping via gtt");
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intel_miptree_map_map(brw, mt, map, level, slice);
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}
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*out_ptr = map->ptr;
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