radeonsi/gfx9: keep reusing the same buffer/address for the gfx9 flush fence
instead of using a monotonic suballocator v2: initialize the memory at context creation Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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c66fc618cc
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@ -64,6 +64,7 @@ static void si_destroy_context(struct pipe_context *context)
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free(sctx->border_color_table);
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free(sctx->border_color_table);
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r600_resource_reference(&sctx->scratch_buffer, NULL);
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r600_resource_reference(&sctx->scratch_buffer, NULL);
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r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
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r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
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r600_resource_reference(&sctx->wait_mem_scratch, NULL);
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si_pm4_free_state(sctx, sctx->init_config, ~0);
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si_pm4_free_state(sctx, sctx->init_config, ~0);
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if (sctx->init_config_gs_rings)
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if (sctx->init_config_gs_rings)
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@ -269,6 +270,23 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
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/* these must be last */
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/* these must be last */
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si_begin_new_cs(sctx);
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si_begin_new_cs(sctx);
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if (sctx->b.chip_class >= GFX9) {
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sctx->wait_mem_scratch = (struct r600_resource*)
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pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4);
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if (!sctx->wait_mem_scratch)
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goto fail;
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/* Initialize the memory. */
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struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
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radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
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radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
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S_370_WR_CONFIRM(1) |
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S_370_ENGINE_SEL(V_370_ME));
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radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
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radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
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radeon_emit(cs, sctx->wait_mem_number);
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}
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/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
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/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
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* if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
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* if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
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if (sctx->b.chip_class == CIK) {
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if (sctx->b.chip_class == CIK) {
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@ -263,6 +263,8 @@ struct si_context {
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struct si_screen *screen;
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struct si_screen *screen;
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LLVMTargetMachineRef tm; /* only non-threaded compilation */
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LLVMTargetMachineRef tm; /* only non-threaded compilation */
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struct si_shader_ctx_state fixed_func_tcs_shader;
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struct si_shader_ctx_state fixed_func_tcs_shader;
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struct r600_resource *wait_mem_scratch;
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unsigned wait_mem_number;
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struct radeon_winsys_cs *ce_ib;
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struct radeon_winsys_cs *ce_ib;
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struct radeon_winsys_cs *ce_preamble_ib;
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struct radeon_winsys_cs *ce_preamble_ib;
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@ -954,9 +954,8 @@ void si_emit_cache_flush(struct si_context *sctx)
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* wait for idle on GFX9. We have to use a TS event.
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* wait for idle on GFX9. We have to use a TS event.
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*/
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*/
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if (sctx->b.chip_class >= GFX9 && flush_cb_db) {
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if (sctx->b.chip_class >= GFX9 && flush_cb_db) {
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struct r600_resource *rbuf = NULL;
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uint64_t va;
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uint64_t va;
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unsigned offset = 0, tc_flags, cb_db_event;
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unsigned tc_flags, cb_db_event;
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/* Set the CB/DB flush event. */
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/* Set the CB/DB flush event. */
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switch (flush_cb_db) {
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switch (flush_cb_db) {
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@ -997,14 +996,15 @@ void si_emit_cache_flush(struct si_context *sctx)
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sctx->b.num_L2_invalidates++;
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sctx->b.num_L2_invalidates++;
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}
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}
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/* Allocate memory for the fence. */
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/* Do the flush (enqueue the event and wait for it). */
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u_suballocator_alloc(rctx->allocator_zeroed_memory, 4, 4,
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va = sctx->wait_mem_scratch->gpu_address;
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&offset, (struct pipe_resource**)&rbuf);
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sctx->wait_mem_number++;
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va = rbuf->gpu_address + offset;
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r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
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r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
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rbuf, va, 0, 1);
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sctx->wait_mem_scratch, va,
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r600_gfx_wait_fence(rctx, va, 1, 0xffffffff);
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sctx->wait_mem_number - 1,
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sctx->wait_mem_number);
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r600_gfx_wait_fence(rctx, va, sctx->wait_mem_number, 0xffffffff);
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}
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}
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/* Make sure ME is idle (it executes most packets) before continuing.
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/* Make sure ME is idle (it executes most packets) before continuing.
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