amd/addrlib: add gfx10 support
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
parent
112bf7f900
commit
78cdf9a99f
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@ -23,6 +23,10 @@ ADDRLIB_FILES = \
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addrlib/src/core/coord.h \
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addrlib/src/gfx9/gfx9addrlib.cpp \
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addrlib/src/gfx9/gfx9addrlib.h \
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addrlib/src/gfx10/gfx10addrlib.cpp \
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addrlib/src/gfx10/gfx10addrlib.h \
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addrlib/src/gfx10/gfx10SwizzlePattern.h \
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addrlib/src/chip/gfx10/gfx10_gb_reg.h \
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addrlib/src/chip/gfx9/gfx9_gb_reg.h \
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addrlib/src/chip/r800/si_gb_reg.h \
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addrlib/src/r800/ciaddrlib.cpp \
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@ -2266,17 +2266,17 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
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/**
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****************************************************************************************************
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* ADDR_GET_MAX_ALINGMENTS_OUTPUT
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* ADDR_GET_MAX_ALIGNMENTS_OUTPUT
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*
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* @brief
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* Output structure of AddrGetMaxAlignments
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****************************************************************************************************
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*/
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typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
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typedef struct _ADDR_GET_MAX_ALIGNMENTS_OUTPUT
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{
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UINT_32 size; ///< Size of this structure in bytes
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UINT_32 baseAlign; ///< Maximum base alignment in bytes
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} ADDR_GET_MAX_ALINGMENTS_OUTPUT;
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} ADDR_GET_MAX_ALIGNMENTS_OUTPUT;
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/**
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****************************************************************************************************
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@ -2288,7 +2288,7 @@ typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
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*/
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ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
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ADDR_HANDLE hLib,
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ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
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ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut);
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/**
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****************************************************************************************************
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@ -2300,7 +2300,7 @@ ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
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*/
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ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
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ADDR_HANDLE hLib,
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ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
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ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut);
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/**
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****************************************************************************************************
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@ -37,7 +37,11 @@ files_addrlib = files(
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'src/core/coord.h',
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'src/gfx9/gfx9addrlib.cpp',
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'src/gfx9/gfx9addrlib.h',
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'src/gfx10/gfx10addrlib.cpp',
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'src/gfx10/gfx10addrlib.h',
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'src/gfx10/gfx10SwizzlePattern.h',
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'src/amdgpu_asic_addr.h',
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'src/chip/gfx10/gfx10_gb_reg.h',
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'src/chip/gfx9/gfx9_gb_reg.h',
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'src/chip/r800/si_gb_reg.h',
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'src/r800/ciaddrlib.cpp',
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@ -54,8 +58,9 @@ libamdgpu_addrlib = static_library(
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include_directories : [
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include_directories(
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'inc', 'src', 'src/core', 'src/chip/gfx9', 'src/chip/r800',
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'src/chip/gfx10',
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),
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inc_amd_common, inc_common, inc_src,
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],
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cpp_args : cpp_vis_args,
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cpp_args : [cpp_vis_args, '-Wno-unused-variable'],
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)
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@ -1070,7 +1070,7 @@ ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
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*/
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ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
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ADDR_HANDLE hLib, ///< address lib handle
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ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) ///< [out] output structure
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ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) ///< [out] output structure
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{
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Addr::Lib* pLib = Lib::GetLib(hLib);
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@ -1101,7 +1101,7 @@ ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
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*/
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ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
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ADDR_HANDLE hLib, ///< address lib handle
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ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) ///< [out] output structure
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ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) ///< [out] output structure
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{
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Addr::Lib* pLib = Lib::GetLib(hLib);
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@ -43,6 +43,7 @@
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#define FAMILY_CZ 0x87
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#define FAMILY_AI 0x8D
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#define FAMILY_RV 0x8E
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#define FAMILY_NV 0x8F
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// AMDGPU_FAMILY_IS(familyId, familyName)
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#define FAMILY_IS(f, fn) (f == FAMILY_##fn)
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@ -55,6 +56,7 @@
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#define FAMILY_IS_CZ(f) FAMILY_IS(f, CZ)
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#define FAMILY_IS_AI(f) FAMILY_IS(f, AI)
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#define FAMILY_IS_RV(f) FAMILY_IS(f, RV)
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#define FAMILY_IS_NV(f) FAMILY_IS(f, NV)
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#define AMDGPU_UNKNOWN 0xFF
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@ -92,6 +94,8 @@
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#define AMDGPU_RAVEN_RANGE 0x01, 0x81
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#define AMDGPU_RAVEN2_RANGE 0x81, 0xFF
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#define AMDGPU_NAVI10_RANGE 0x01, 0xFF
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#define AMDGPU_EXPAND_FIX(x) x
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#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
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#define AMDGPU_IN_RANGE(val, ...) AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
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@ -134,4 +138,6 @@
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#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
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#define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2)
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#define ASICREV_IS_NAVI10_P(r) ASICREV_IS(r, NAVI10)
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#endif // _AMDGPU_ASIC_ADDR_H
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@ -0,0 +1,72 @@
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/*
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* Copyright © 2007-2019 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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#if !defined (__GFX10_GB_REG_H__)
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#define __GFX10_GB_REG_H__
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/*
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* gfx10_gb_reg.h
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*
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* Register Spec Release: 1.0
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*
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*/
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//
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// Make sure the necessary endian defines are there.
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//
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#include "util/u_endian.h"
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#if defined(PIPE_ARCH_LITTLE_ENDIAN)
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#define LITTLEENDIAN_CPU
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#elif defined(PIPE_ARCH_BIG_ENDIAN)
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#define BIGENDIAN_CPU
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#endif
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union GB_ADDR_CONFIG
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{
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struct
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{
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#if defined(LITTLEENDIAN_CPU)
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unsigned int NUM_PIPES : 3;
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unsigned int PIPE_INTERLEAVE_SIZE : 3;
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unsigned int MAX_COMPRESSED_FRAGS : 2;
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unsigned int NUM_PKRS : 3;
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unsigned int : 21;
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#elif defined(BIGENDIAN_CPU)
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unsigned int : 21;
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unsigned int NUM_PKRS : 3;
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unsigned int MAX_COMPRESSED_FRAGS : 2;
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unsigned int PIPE_INTERLEAVE_SIZE : 3;
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unsigned int NUM_PIPES : 3;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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int i32All;
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float f32All;
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};
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#endif
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@ -1,6 +1,3 @@
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#if !defined (__GFX9_GB_REG_H__)
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#define __GFX9_GB_REG_H__
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/*
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* Copyright © 2007-2019 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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@ -27,6 +24,19 @@
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* of the Software.
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*/
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#if !defined (__GFX9_GB_REG_H__)
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#define __GFX9_GB_REG_H__
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/*
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* gfx9_gb_reg.h
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*
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* Register Spec Release: 1.0
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*
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*/
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//
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// Make sure the necessary endian defines are there.
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//
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#include "util/u_endian.h"
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#if defined(PIPE_ARCH_LITTLE_ENDIAN)
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#define BIGENDIAN_CPU
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#endif
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//
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// Make sure the necessary endian defines are there.
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//
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#if defined(LITTLEENDIAN_CPU)
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#elif defined(BIGENDIAN_CPU)
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#else
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#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
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#endif
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union GB_ADDR_CONFIG {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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@ -1,6 +1,3 @@
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#if !defined (__SI_GB_REG_H__)
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#define __SI_GB_REG_H__
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/*
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* Copyright © 2007-2019 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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@ -27,6 +24,20 @@
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* of the Software.
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*/
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#if !defined (__SI_GB_REG_H__)
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#define __SI_GB_REG_H__
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/*****************************************************************************************************************
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*
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* si_gb_reg.h
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*
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* Register Spec Release: Chip Spec 0.28
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*
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*****************************************************************************************************************/
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//
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// Make sure the necessary endian defines are there.
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//
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#include "util/u_endian.h"
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#if defined(PIPE_ARCH_LITTLE_ENDIAN)
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#define BIGENDIAN_CPU
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#endif
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//
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// Make sure the necessary endian defines are there.
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//
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#if defined(LITTLEENDIAN_CPU)
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#elif defined(BIGENDIAN_CPU)
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#else
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#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
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#endif
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/*
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* GB_ADDR_CONFIG struct
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*/
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@ -241,6 +241,7 @@ enum ChipFamily
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ADDR_CHIP_FAMILY_CI,
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ADDR_CHIP_FAMILY_VI,
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ADDR_CHIP_FAMILY_AI,
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ADDR_CHIP_FAMILY_NAVI,
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};
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/**
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@ -223,6 +223,9 @@ ADDR_E_RETURNCODE Lib::Create(
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case FAMILY_RV:
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pLib = Gfx9HwlInit(&client);
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break;
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case FAMILY_NV:
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pLib = Gfx10HwlInit(&client);
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break;
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default:
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ADDR_ASSERT_ALWAYS();
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break;
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@ -384,14 +387,14 @@ Lib* Lib::GetLib(
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****************************************************************************************************
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*/
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ADDR_E_RETURNCODE Lib::GetMaxAlignments(
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ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut ///< [out] output structure
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ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut ///< [out] output structure
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) const
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{
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ADDR_E_RETURNCODE returnCode = ADDR_OK;
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if (GetFillSizeFieldsFlags() == TRUE)
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{
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if (pOut->size != sizeof(ADDR_GET_MAX_ALINGMENTS_OUTPUT))
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if (pOut->size != sizeof(ADDR_GET_MAX_ALIGNMENTS_OUTPUT))
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{
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returnCode = ADDR_PARAMSIZEMISMATCH;
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}
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@ -424,14 +427,14 @@ ADDR_E_RETURNCODE Lib::GetMaxAlignments(
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****************************************************************************************************
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*/
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ADDR_E_RETURNCODE Lib::GetMaxMetaAlignments(
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ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut ///< [out] output structure
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ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut ///< [out] output structure
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) const
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{
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ADDR_E_RETURNCODE returnCode = ADDR_OK;
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if (GetFillSizeFieldsFlags() == TRUE)
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{
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if (pOut->size != sizeof(ADDR_GET_MAX_ALINGMENTS_OUTPUT))
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if (pOut->size != sizeof(ADDR_GET_MAX_ALIGNMENTS_OUTPUT))
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{
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returnCode = ADDR_PARAMSIZEMISMATCH;
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}
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@ -282,9 +282,9 @@ public:
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BOOL_32 GetExportNorm(const ELEM_GETEXPORTNORM_INPUT* pIn) const;
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ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
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ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
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ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
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ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
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UINT_32 GetBpe(AddrFormat format) const;
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@ -409,6 +409,7 @@ private:
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Lib* SiHwlInit (const Client* pClient);
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Lib* CiHwlInit (const Client* pClient);
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Lib* Gfx9HwlInit (const Client* pClient);
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Lib* Gfx10HwlInit(const Client* pClient);
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} // Addr
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#endif
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@ -104,6 +104,8 @@ enum AddrBlockSet
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AddrBlockSetLinear = 1 << AddrBlockLinear,
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AddrBlockSetMacro = AddrBlockSetMacro4KB | AddrBlockSetMacro64KB,
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AddrBlockSet2dGfx10 = AddrBlockSetMicro | AddrBlockSetMacro,
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AddrBlockSet3dGfx10 = AddrBlockSetMacro,
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};
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enum AddrSwSet
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@ -114,6 +116,8 @@ enum AddrSwSet
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AddrSwSetR = 1 << ADDR_SW_R,
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AddrSwSetAll = AddrSwSetZ | AddrSwSetS | AddrSwSetD | AddrSwSetR,
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AddrSwSet3dThinGfx10 = AddrSwSetZ | AddrSwSetR,
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AddrSwSetColorGfx10 = AddrSwSetS | AddrSwSetD | AddrSwSetR,
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};
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/**
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@ -1,3 +1,4 @@
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/*
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* Copyright © 2007-2019 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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|
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,569 @@
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/*
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* Copyright © 2007-2019 Advanced Micro Devices, Inc.
|
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* All Rights Reserved.
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||||
*
|
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* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sub license, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
|
||||
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||||
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial portions
|
||||
* of the Software.
|
||||
*/
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/**
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************************************************************************************************************************
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* @file gfx10addrlib.h
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* @brief Contains the Gfx10Lib class definition.
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************************************************************************************************************************
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*/
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#ifndef __GFX10_ADDR_LIB_H__
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#define __GFX10_ADDR_LIB_H__
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#include "addrlib2.h"
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#include "coord.h"
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namespace Addr
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{
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namespace V2
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{
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/**
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************************************************************************************************************************
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* @brief GFX10 specific settings structure.
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************************************************************************************************************************
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*/
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struct Gfx10ChipSettings
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{
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struct
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{
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UINT_32 reserved1 : 32;
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// Misc configuration bits
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UINT_32 isDcn2 : 1;
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UINT_32 supportRbPlus : 1;
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UINT_32 dsMipmapHtileFix : 1;
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UINT_32 dccUnsup3DSwDis : 1;
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UINT_32 reserved2 : 28;
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};
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};
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/**
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************************************************************************************************************************
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* @brief GFX10 data surface type.
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************************************************************************************************************************
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*/
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enum Gfx10DataType
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{
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Gfx10DataColor,
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Gfx10DataDepthStencil,
|
||||
Gfx10DataFmask
|
||||
};
|
||||
|
||||
const UINT_32 Gfx10LinearSwModeMask = (1u << ADDR_SW_LINEAR);
|
||||
|
||||
const UINT_32 Gfx10Blk256BSwModeMask = (1u << ADDR_SW_256B_S) |
|
||||
(1u << ADDR_SW_256B_D);
|
||||
|
||||
const UINT_32 Gfx10Blk4KBSwModeMask = (1u << ADDR_SW_4KB_S) |
|
||||
(1u << ADDR_SW_4KB_D) |
|
||||
(1u << ADDR_SW_4KB_S_X) |
|
||||
(1u << ADDR_SW_4KB_D_X);
|
||||
|
||||
const UINT_32 Gfx10Blk64KBSwModeMask = (1u << ADDR_SW_64KB_S) |
|
||||
(1u << ADDR_SW_64KB_D) |
|
||||
(1u << ADDR_SW_64KB_S_T) |
|
||||
(1u << ADDR_SW_64KB_D_T) |
|
||||
(1u << ADDR_SW_64KB_Z_X) |
|
||||
(1u << ADDR_SW_64KB_S_X) |
|
||||
(1u << ADDR_SW_64KB_D_X) |
|
||||
(1u << ADDR_SW_64KB_R_X);
|
||||
|
||||
const UINT_32 Gfx10ZSwModeMask = (1u << ADDR_SW_64KB_Z_X);
|
||||
|
||||
const UINT_32 Gfx10StandardSwModeMask = (1u << ADDR_SW_256B_S) |
|
||||
(1u << ADDR_SW_4KB_S) |
|
||||
(1u << ADDR_SW_64KB_S) |
|
||||
(1u << ADDR_SW_64KB_S_T) |
|
||||
(1u << ADDR_SW_4KB_S_X) |
|
||||
(1u << ADDR_SW_64KB_S_X);
|
||||
|
||||
const UINT_32 Gfx10DisplaySwModeMask = (1u << ADDR_SW_256B_D) |
|
||||
(1u << ADDR_SW_4KB_D) |
|
||||
(1u << ADDR_SW_64KB_D) |
|
||||
(1u << ADDR_SW_64KB_D_T) |
|
||||
(1u << ADDR_SW_4KB_D_X) |
|
||||
(1u << ADDR_SW_64KB_D_X);
|
||||
|
||||
const UINT_32 Gfx10RenderSwModeMask = (1u << ADDR_SW_64KB_R_X);
|
||||
|
||||
const UINT_32 Gfx10XSwModeMask = (1u << ADDR_SW_4KB_S_X) |
|
||||
(1u << ADDR_SW_4KB_D_X) |
|
||||
(1u << ADDR_SW_64KB_Z_X) |
|
||||
(1u << ADDR_SW_64KB_S_X) |
|
||||
(1u << ADDR_SW_64KB_D_X) |
|
||||
(1u << ADDR_SW_64KB_R_X);
|
||||
|
||||
const UINT_32 Gfx10TSwModeMask = (1u << ADDR_SW_64KB_S_T) |
|
||||
(1u << ADDR_SW_64KB_D_T);
|
||||
|
||||
const UINT_32 Gfx10XorSwModeMask = Gfx10XSwModeMask |
|
||||
Gfx10TSwModeMask;
|
||||
|
||||
const UINT_32 Gfx10Rsrc1dSwModeMask = Gfx10LinearSwModeMask |
|
||||
Gfx10RenderSwModeMask |
|
||||
Gfx10ZSwModeMask;
|
||||
|
||||
const UINT_32 Gfx10Rsrc2dSwModeMask = Gfx10LinearSwModeMask |
|
||||
Gfx10Blk256BSwModeMask |
|
||||
Gfx10Blk4KBSwModeMask |
|
||||
Gfx10Blk64KBSwModeMask;
|
||||
|
||||
const UINT_32 Gfx10Rsrc3dSwModeMask = (1u << ADDR_SW_LINEAR) |
|
||||
(1u << ADDR_SW_4KB_S) |
|
||||
(1u << ADDR_SW_64KB_S) |
|
||||
(1u << ADDR_SW_64KB_S_T) |
|
||||
(1u << ADDR_SW_4KB_S_X) |
|
||||
(1u << ADDR_SW_64KB_Z_X) |
|
||||
(1u << ADDR_SW_64KB_S_X) |
|
||||
(1u << ADDR_SW_64KB_D_X) |
|
||||
(1u << ADDR_SW_64KB_R_X);
|
||||
|
||||
const UINT_32 Gfx10Rsrc2dPrtSwModeMask = (Gfx10Blk4KBSwModeMask | Gfx10Blk64KBSwModeMask) & ~Gfx10XSwModeMask;
|
||||
|
||||
const UINT_32 Gfx10Rsrc3dPrtSwModeMask = Gfx10Rsrc2dPrtSwModeMask & ~Gfx10DisplaySwModeMask;
|
||||
|
||||
const UINT_32 Gfx10Rsrc3dThinSwModeMask = (1u << ADDR_SW_64KB_Z_X) |
|
||||
(1u << ADDR_SW_64KB_R_X);
|
||||
|
||||
const UINT_32 Gfx10MsaaSwModeMask = Gfx10ZSwModeMask |
|
||||
Gfx10RenderSwModeMask;
|
||||
|
||||
const UINT_32 Dcn2NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) |
|
||||
(1u << ADDR_SW_4KB_S) |
|
||||
(1u << ADDR_SW_64KB_S) |
|
||||
(1u << ADDR_SW_64KB_S_T) |
|
||||
(1u << ADDR_SW_4KB_S_X) |
|
||||
(1u << ADDR_SW_64KB_S_X) |
|
||||
(1u << ADDR_SW_64KB_R_X);
|
||||
|
||||
const UINT_32 Dcn2Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) |
|
||||
(1u << ADDR_SW_64KB_D) |
|
||||
(1u << ADDR_SW_64KB_D_T) |
|
||||
(1u << ADDR_SW_4KB_D_X) |
|
||||
(1u << ADDR_SW_64KB_D_X) |
|
||||
Dcn2NonBpp64SwModeMask;
|
||||
/**
|
||||
************************************************************************************************************************
|
||||
* @brief This class is the GFX10 specific address library
|
||||
* function set.
|
||||
************************************************************************************************************************
|
||||
*/
|
||||
class Gfx10Lib : public Lib
|
||||
{
|
||||
public:
|
||||
/// Creates Gfx10Lib object
|
||||
static Addr::Lib* CreateObj(const Client* pClient)
|
||||
{
|
||||
VOID* pMem = Object::ClientAlloc(sizeof(Gfx10Lib), pClient);
|
||||
return (pMem != NULL) ? new (pMem) Gfx10Lib(pClient) : NULL;
|
||||
}
|
||||
|
||||
protected:
|
||||
Gfx10Lib(const Client* pClient);
|
||||
virtual ~Gfx10Lib();
|
||||
|
||||
virtual BOOL_32 HwlIsStandardSwizzle(
|
||||
AddrResourceType resourceType,
|
||||
AddrSwizzleMode swizzleMode) const
|
||||
{
|
||||
return m_swizzleModeTable[swizzleMode].isStd;
|
||||
}
|
||||
|
||||
virtual BOOL_32 HwlIsDisplaySwizzle(
|
||||
AddrResourceType resourceType,
|
||||
AddrSwizzleMode swizzleMode) const
|
||||
{
|
||||
return m_swizzleModeTable[swizzleMode].isDisp;
|
||||
}
|
||||
|
||||
virtual BOOL_32 HwlIsThin(
|
||||
AddrResourceType resourceType,
|
||||
AddrSwizzleMode swizzleMode) const
|
||||
{
|
||||
return ((IsTex1d(resourceType) == TRUE) ||
|
||||
(IsTex2d(resourceType) == TRUE) ||
|
||||
((IsTex3d(resourceType) == TRUE) &&
|
||||
(m_swizzleModeTable[swizzleMode].isStd == FALSE) &&
|
||||
(m_swizzleModeTable[swizzleMode].isDisp == FALSE)));
|
||||
}
|
||||
|
||||
virtual BOOL_32 HwlIsThick(
|
||||
AddrResourceType resourceType,
|
||||
AddrSwizzleMode swizzleMode) const
|
||||
{
|
||||
return ((IsTex3d(resourceType) == TRUE) &&
|
||||
(m_swizzleModeTable[swizzleMode].isStd || m_swizzleModeTable[swizzleMode].isDisp));
|
||||
}
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeHtileInfo(
|
||||
const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo(
|
||||
const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
|
||||
const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
|
||||
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
|
||||
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
|
||||
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord(
|
||||
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
|
||||
|
||||
virtual UINT_32 HwlGetEquationIndex(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
|
||||
{
|
||||
*ppEquationTable = m_equationTable;
|
||||
|
||||
return m_numEquations;
|
||||
}
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputePipeBankXor(
|
||||
const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
|
||||
const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
|
||||
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting(
|
||||
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
|
||||
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
|
||||
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
|
||||
// Initialize equation table
|
||||
VOID InitEquationTable();
|
||||
|
||||
ADDR_E_RETURNCODE ComputeSurfaceInfoMacroTiled(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
ADDR_E_RETURNCODE ComputeSurfaceInfoMicroTiled(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
|
||||
|
||||
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMacroTiled(
|
||||
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
|
||||
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMicroTiled(
|
||||
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
|
||||
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
|
||||
|
||||
UINT_32 ComputeOffsetFromSwizzlePattern(
|
||||
const UINT_64* pPattern,
|
||||
UINT_32 numBits,
|
||||
UINT_32 x,
|
||||
UINT_32 y,
|
||||
UINT_32 z,
|
||||
UINT_32 s) const;
|
||||
|
||||
UINT_32 ComputeOffsetFromEquation(
|
||||
const ADDR_EQUATION* pEq,
|
||||
UINT_32 x,
|
||||
UINT_32 y,
|
||||
UINT_32 z) const;
|
||||
|
||||
ADDR_E_RETURNCODE ComputeStereoInfo(
|
||||
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
|
||||
UINT_32 blkHeight,
|
||||
UINT_32* pAlignY,
|
||||
UINT_32* pRightXor) const;
|
||||
|
||||
Dim3d GetDccCompressBlk(
|
||||
AddrResourceType resourceType,
|
||||
AddrSwizzleMode swizzleMode,
|
||||
UINT_32 bpp) const
|
||||
{
|
||||
UINT_32 index = Log2(bpp >> 3);
|
||||
Dim3d compressBlkDim;
|
||||
|
||||
if (IsThin(resourceType, swizzleMode))
|
||||
{
|
||||
compressBlkDim.w = Block256_2d[index].w;
|
||||
compressBlkDim.h = Block256_2d[index].h;
|
||||
compressBlkDim.d = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
compressBlkDim = Block256_3d[index];
|
||||
}
|
||||
|
||||
return compressBlkDim;
|
||||
}
|
||||
|
||||
static UINT_32 ShiftCeil(
|
||||
UINT_32 a,
|
||||
UINT_32 b)
|
||||
{
|
||||
return (a >> b) + (((a & ((1 << b) - 1)) != 0) ? 1 : 0);
|
||||
}
|
||||
|
||||
static void GetMipSize(
|
||||
UINT_32 mip0Width,
|
||||
UINT_32 mip0Height,
|
||||
UINT_32 mip0Depth,
|
||||
UINT_32 mipId,
|
||||
UINT_32* pMipWidth,
|
||||
UINT_32* pMipHeight,
|
||||
UINT_32* pMipDepth = NULL)
|
||||
{
|
||||
*pMipWidth = ShiftCeil(Max(mip0Width, 1u), mipId);
|
||||
*pMipHeight = ShiftCeil(Max(mip0Height, 1u), mipId);
|
||||
|
||||
if (pMipDepth != NULL)
|
||||
{
|
||||
*pMipDepth = ShiftCeil(Max(mip0Depth, 1u), mipId);
|
||||
}
|
||||
}
|
||||
|
||||
const UINT_64* GetSwizzlePattern(
|
||||
AddrSwizzleMode swizzleMode,
|
||||
AddrResourceType resourceType,
|
||||
UINT_32 log2Elem,
|
||||
UINT_32 numFrag) const;
|
||||
|
||||
VOID ConvertSwizzlePatternToEquation(
|
||||
UINT_32 elemLog2,
|
||||
AddrResourceType rsrcType,
|
||||
AddrSwizzleMode swMode,
|
||||
const UINT_64* pPattern,
|
||||
ADDR_EQUATION* pEquation) const;
|
||||
|
||||
static INT_32 GetMetaElementSizeLog2(Gfx10DataType dataType);
|
||||
|
||||
static INT_32 GetMetaCacheSizeLog2(Gfx10DataType dataType);
|
||||
|
||||
void GetBlk256SizeLog2(
|
||||
AddrResourceType resourceType,
|
||||
AddrSwizzleMode swizzleMode,
|
||||
UINT_32 elemLog2,
|
||||
UINT_32 numSamplesLog2,
|
||||
Dim3d* pBlock) const;
|
||||
|
||||
void GetCompressedBlockSizeLog2(
|
||||
Gfx10DataType dataType,
|
||||
AddrResourceType resourceType,
|
||||
AddrSwizzleMode swizzleMode,
|
||||
UINT_32 elemLog2,
|
||||
UINT_32 numSamplesLog2,
|
||||
Dim3d* pBlock) const;
|
||||
|
||||
INT_32 GetMetaOverlapLog2(
|
||||
Gfx10DataType dataType,
|
||||
AddrResourceType resourceType,
|
||||
AddrSwizzleMode swizzleMode,
|
||||
UINT_32 elemLog2,
|
||||
UINT_32 numSamplesLog2) const;
|
||||
|
||||
INT_32 Get3DMetaOverlapLog2(
|
||||
AddrResourceType resourceType,
|
||||
AddrSwizzleMode swizzleMode,
|
||||
UINT_32 elemLog2) const;
|
||||
|
||||
UINT_32 GetMetaBlkSize(
|
||||
Gfx10DataType dataType,
|
||||
AddrResourceType resourceType,
|
||||
AddrSwizzleMode swizzleMode,
|
||||
UINT_32 elemLog2,
|
||||
UINT_32 numSamplesLog2,
|
||||
BOOL_32 pipeAlign,
|
||||
Dim3d* pBlock) const;
|
||||
|
||||
BOOL_32 IsEquationCompatibleThick(
|
||||
AddrResourceType resourceType,
|
||||
AddrSwizzleMode swizzleMode) const
|
||||
{
|
||||
return IsThick(resourceType, swizzleMode) &&
|
||||
((m_settings.supportRbPlus == 0) || (swizzleMode != ADDR_SW_64KB_D_X));
|
||||
}
|
||||
|
||||
INT_32 GetPipeRotateAmount(
|
||||
AddrResourceType resourceType,
|
||||
AddrSwizzleMode swizzleMode) const;
|
||||
|
||||
INT_32 GetEffectiveNumPipes() const
|
||||
{
|
||||
return ((m_settings.supportRbPlus == FALSE) ||
|
||||
((m_numSaLog2 + 1) >= m_pipesLog2)) ? m_pipesLog2 : m_numSaLog2 + 1;
|
||||
}
|
||||
|
||||
BOOL_32 IsRbAligned(
|
||||
AddrResourceType resourceType,
|
||||
AddrSwizzleMode swizzleMode) const
|
||||
{
|
||||
const BOOL_32 isRtopt = IsRtOptSwizzle(swizzleMode);
|
||||
const BOOL_32 isZ = IsZOrderSwizzle(swizzleMode);
|
||||
const BOOL_32 isDisplay = IsDisplaySwizzle(swizzleMode);
|
||||
|
||||
return (IsTex2d(resourceType) && (isRtopt || isZ)) ||
|
||||
(IsTex3d(resourceType) && isDisplay);
|
||||
|
||||
}
|
||||
|
||||
static const Dim3d Block256_3d[MaxNumOfBpp];
|
||||
static const Dim3d Block64K_3d[MaxNumOfBpp];
|
||||
static const Dim3d Block4K_3d[MaxNumOfBpp];
|
||||
static const Dim3d Block64K_Log2_3d[MaxNumOfBpp];
|
||||
static const Dim3d Block4K_Log2_3d[MaxNumOfBpp];
|
||||
|
||||
static const Dim2d Block64K_2d[MaxNumOfBpp];
|
||||
static const Dim2d Block4K_2d[MaxNumOfBpp];
|
||||
|
||||
static const Dim2d Block64K_Log2_2d[MaxNumOfBpp];
|
||||
static const Dim2d Block4K_Log2_2d[MaxNumOfBpp];
|
||||
|
||||
static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE];
|
||||
|
||||
// Max number of swizzle mode supported for equation
|
||||
static const UINT_32 MaxSwMode = 32;
|
||||
// Max number of resource type (2D/3D) supported for equation
|
||||
static const UINT_32 MaxRsrcType = 2;
|
||||
// Max number of bpp (8bpp/16bpp/32bpp/64bpp/128bpp)
|
||||
static const UINT_32 MaxElementBytesLog2 = 5;
|
||||
// Almost all swizzle mode + resource type support equation
|
||||
static const UINT_32 EquationTableSize = MaxElementBytesLog2 * MaxSwMode * MaxRsrcType;
|
||||
// Equation table
|
||||
ADDR_EQUATION m_equationTable[EquationTableSize];
|
||||
|
||||
// Number of equation entries in the table
|
||||
UINT_32 m_numEquations;
|
||||
// Equation lookup table according to bpp and tile index
|
||||
UINT_32 m_equationLookupTable[MaxRsrcType][MaxSwMode][MaxElementBytesLog2];
|
||||
// Number of packers log2
|
||||
UINT_32 m_numPkrLog2;
|
||||
// Number of shader array log2
|
||||
UINT_32 m_numSaLog2;
|
||||
|
||||
private:
|
||||
virtual UINT_32 HwlComputeMaxBaseAlignments() const;
|
||||
|
||||
virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const;
|
||||
|
||||
virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn);
|
||||
|
||||
virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
|
||||
|
||||
BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
|
||||
|
||||
UINT_32 GetMaxNumMipsInTail(UINT_32 blockSizeLog2, BOOL_32 isThin) const;
|
||||
|
||||
static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet)
|
||||
{
|
||||
ADDR2_BLOCK_SET allowedBlockSet = {};
|
||||
|
||||
allowedBlockSet.micro = (allowedSwModeSet.value & Gfx10Blk256BSwModeMask) ? TRUE : FALSE;
|
||||
allowedBlockSet.macro4KB = (allowedSwModeSet.value & Gfx10Blk4KBSwModeMask) ? TRUE : FALSE;
|
||||
allowedBlockSet.macro64KB = (allowedSwModeSet.value & Gfx10Blk64KBSwModeMask) ? TRUE : FALSE;
|
||||
allowedBlockSet.linear = (allowedSwModeSet.value & Gfx10LinearSwModeMask) ? TRUE : FALSE;
|
||||
|
||||
return allowedBlockSet;
|
||||
}
|
||||
|
||||
static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)
|
||||
{
|
||||
ADDR2_SWTYPE_SET allowedSwSet = {};
|
||||
|
||||
allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx10ZSwModeMask) ? TRUE : FALSE;
|
||||
allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx10StandardSwModeMask) ? TRUE : FALSE;
|
||||
allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx10DisplaySwModeMask) ? TRUE : FALSE;
|
||||
allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx10RenderSwModeMask) ? TRUE : FALSE;
|
||||
|
||||
return allowedSwSet;
|
||||
}
|
||||
|
||||
BOOL_32 IsInMipTail(
|
||||
Dim3d mipTailDim,
|
||||
UINT_32 maxNumMipsInTail,
|
||||
UINT_32 mipWidth,
|
||||
UINT_32 mipHeight,
|
||||
UINT_32 numMipsToTheEnd) const
|
||||
{
|
||||
BOOL_32 inTail = ((mipWidth <= mipTailDim.w) &&
|
||||
(mipHeight <= mipTailDim.h) &&
|
||||
(numMipsToTheEnd <= maxNumMipsInTail));
|
||||
|
||||
return inTail;
|
||||
}
|
||||
|
||||
UINT_32 GetBankXorBits(UINT_32 blockBits) const
|
||||
{
|
||||
return (blockBits > m_pipeInterleaveLog2 + m_pipesLog2 + ColumnBits) ?
|
||||
Min(blockBits - m_pipeInterleaveLog2 - m_pipesLog2 - ColumnBits, BankBits) : 0;
|
||||
}
|
||||
|
||||
BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
|
||||
BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
|
||||
|
||||
static const UINT_32 ColumnBits = 2;
|
||||
static const UINT_32 BankBits = 4;
|
||||
|
||||
Gfx10ChipSettings m_settings;
|
||||
UINT_32 m_colorBaseIndex;
|
||||
UINT_32 m_htileBaseIndex;
|
||||
};
|
||||
|
||||
} // V2
|
||||
} // Addr
|
||||
|
||||
#endif
|
||||
|
|
@ -62,6 +62,7 @@ struct Gfx9ChipSettings
|
|||
// Display engine IP version name
|
||||
UINT_32 isDce12 : 1;
|
||||
UINT_32 isDcn1 : 1;
|
||||
UINT_32 reserved1 : 30;
|
||||
|
||||
// Misc configuration bits
|
||||
UINT_32 metaBaseAlignFix : 1;
|
||||
|
|
|
@ -23,7 +23,6 @@
|
|||
* next paragraph) shall be included in all copies or substantial portions
|
||||
* of the Software.
|
||||
*/
|
||||
|
||||
/**
|
||||
****************************************************************************************************
|
||||
* @file egbaddrlib.cpp
|
||||
|
|
|
@ -68,7 +68,7 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
|
|||
ADDR_CREATE_OUTPUT addrCreateOutput = {0};
|
||||
ADDR_REGISTER_VALUE regValue = {0};
|
||||
ADDR_CREATE_FLAGS createFlags = {{0}};
|
||||
ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
|
||||
ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
|
||||
ADDR_E_RETURNCODE addrRet;
|
||||
|
||||
addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
|
||||
|
|
Loading…
Reference in New Issue