radv: use nir_fold_16bit_sampler_conversions()
for now only for texture dest and if there is no rounding mode required. Totals from 2 (0.00% of 150170) affected shaders: (GFX10.3) CodeSize: 7980 -> 7948 (-0.40%) Instrs: 1441 -> 1422 (-1.32%) Latency: 7703 -> 7626 (-1.00%) InvThroughput: 2336 -> 2302 (-1.46%) VClause: 34 -> 36 (+5.88%) Copies: 57 -> 58 (+1.75%) Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13592>
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@ -3589,8 +3589,14 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
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nir_opt_remove_phis(nir[i]); /* cleanup LCSSA phis */
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nir_opt_remove_phis(nir[i]); /* cleanup LCSSA phis */
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}
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}
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if (((nir[i]->info.bit_sizes_int | nir[i]->info.bit_sizes_float) & 16) &&
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if (((nir[i]->info.bit_sizes_int | nir[i]->info.bit_sizes_float) & 16) &&
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device->physical_device->rad_info.chip_class >= GFX9)
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device->physical_device->rad_info.chip_class >= GFX9) {
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// TODO: also optimize the tex srcs. see radeonSI for reference */
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/* Skip if there are potentially conflicting rounding modes */
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if (!nir_has_any_rounding_mode_enabled(nir[i]->info.float_controls_execution_mode))
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NIR_PASS_V(nir[i], nir_fold_16bit_sampler_conversions, 0);
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NIR_PASS_V(nir[i], nir_opt_vectorize, opt_vectorize_callback, NULL);
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NIR_PASS_V(nir[i], nir_opt_vectorize, opt_vectorize_callback, NULL);
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}
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/* cleanup passes */
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/* cleanup passes */
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nir_lower_load_const_to_scalar(nir[i]);
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nir_lower_load_const_to_scalar(nir[i]);
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