aco: implement 8/16-bit instructions which can be trivially widened
When nir_lower_bit_size becomes more capable, we might want to revert some of this. fossil-db (parallel-rdp, Navi): Totals from 217 (31.77% of 683) affected shaders: SGPRs: 11320 -> 10200 (-9.89%) VGPRs: 7156 -> 7364 (+2.91%) CodeSize: 1453948 -> 1430136 (-1.64%); split: -1.66%, +0.02% Instrs: 258530 -> 254840 (-1.43%); split: -1.44%, +0.01% Cycles: 37334360 -> 37247936 (-0.23%); split: -0.26%, +0.03% Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4791>
This commit is contained in:
Rhys Perry
Marge Bot
parent
ef95ba8cdd
commit
786828131a
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@ -1224,7 +1224,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
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/* Don't use s_andn2 here, this allows the optimizer to make a better decision */
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Temp tmp = bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), src);
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bld.sop2(Builder::s_and, Definition(dst), bld.def(s1, scc), tmp, Operand(exec, bld.lm));
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} else if (dst.regClass() == v1) {
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} else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
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emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
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} else if (dst.regClass() == v2) {
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Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
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@ -1365,7 +1365,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
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case nir_op_ior: {
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if (instr->dest.dest.ssa.bit_size == 1) {
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emit_boolean_logic(ctx, instr, Builder::s_or, dst);
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} else if (dst.regClass() == v1) {
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} else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
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emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
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} else if (dst.regClass() == v2) {
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emit_vop2_instruction_logic64(ctx, instr, aco_opcode::v_or_b32, dst);
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@ -1381,7 +1381,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
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case nir_op_iand: {
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if (instr->dest.dest.ssa.bit_size == 1) {
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emit_boolean_logic(ctx, instr, Builder::s_and, dst);
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} else if (dst.regClass() == v1) {
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} else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
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emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
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} else if (dst.regClass() == v2) {
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emit_vop2_instruction_logic64(ctx, instr, aco_opcode::v_and_b32, dst);
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@ -1397,7 +1397,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
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case nir_op_ixor: {
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if (instr->dest.dest.ssa.bit_size == 1) {
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emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
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} else if (dst.regClass() == v1) {
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} else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
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emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
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} else if (dst.regClass() == v2) {
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emit_vop2_instruction_logic64(ctx, instr, aco_opcode::v_xor_b32, dst);
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@ -1527,17 +1527,17 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
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if (dst.regClass() == s1) {
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emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
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break;
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} else if (dst.regClass() == v2b && ctx->program->chip_class < GFX10) {
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emit_vop2_instruction(ctx, instr, aco_opcode::v_add_u16, dst, true);
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break;
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} else if (dst.regClass() == v2b) {
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} else if (dst.bytes() <= 2 && ctx->program->chip_class >= GFX10) {
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emit_vop3a_instruction(ctx, instr, aco_opcode::v_add_u16_e64, dst);
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break;
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} else if (dst.bytes() <= 2 && ctx->program->chip_class >= GFX8) {
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emit_vop2_instruction(ctx, instr, aco_opcode::v_add_u16, dst, true);
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break;
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}
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Temp src0 = get_alu_src(ctx, instr->src[0]);
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Temp src1 = get_alu_src(ctx, instr->src[1]);
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if (dst.regClass() == v1) {
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if (dst.type() == RegType::vgpr && dst.bytes() <= 4) {
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bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
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break;
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}
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@ -1649,13 +1649,15 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
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if (dst.regClass() == v1) {
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bld.vsub32(Definition(dst), src0, src1);
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break;
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} else if (dst.regClass() == v2b) {
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} else if (dst.bytes() <= 2) {
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if (ctx->program->chip_class >= GFX10)
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bld.vop3(aco_opcode::v_sub_u16_e64, Definition(dst), src0, src1);
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else if (src1.type() == RegType::sgpr)
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bld.vop2(aco_opcode::v_subrev_u16, Definition(dst), src1, as_vgpr(ctx, src0));
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else
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else if (ctx->program->chip_class >= GFX8)
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bld.vop2(aco_opcode::v_sub_u16, Definition(dst), src0, as_vgpr(ctx, src1));
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else
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bld.vsub32(Definition(dst), src0, src1);
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break;
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}
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@ -1714,7 +1716,11 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
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break;
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}
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case nir_op_imul: {
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if (dst.regClass() == v1) {
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if (dst.bytes() <= 2 && ctx->program->chip_class >= GFX10) {
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emit_vop3a_instruction(ctx, instr, aco_opcode::v_mul_lo_u16_e64, dst);
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} else if (dst.bytes() <= 2 && ctx->program->chip_class >= GFX8) {
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emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_lo_u16, dst, true);
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} else if (dst.type() == RegType::vgpr) {
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uint32_t src0_ub = get_alu_src_ub(ctx, instr, 0);
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uint32_t src1_ub = get_alu_src_ub(ctx, instr, 1);
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@ -1723,10 +1729,6 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
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} else {
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emit_vop3a_instruction(ctx, instr, aco_opcode::v_mul_lo_u32, dst);
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}
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} else if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) {
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emit_vop3a_instruction(ctx, instr, aco_opcode::v_mul_lo_u16_e64, dst);
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} else if (dst.regClass() == v2b) {
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emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_lo_u16, dst, true);
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} else if (dst.regClass() == s1) {
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emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
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} else {
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@ -2957,7 +2957,6 @@ lower_bit_size_callback(const nir_alu_instr *alu, void *_)
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unsigned bit_size = alu->dest.dest.ssa.bit_size;
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switch (alu->op) {
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case nir_op_iabs:
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case nir_op_iand:
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case nir_op_bitfield_select:
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case nir_op_udiv:
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case nir_op_idiv:
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@ -2966,11 +2965,8 @@ lower_bit_size_callback(const nir_alu_instr *alu, void *_)
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case nir_op_imul_high:
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case nir_op_umul_high:
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case nir_op_ineg:
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case nir_op_inot:
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case nir_op_ior:
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case nir_op_irem:
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case nir_op_isign:
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case nir_op_ixor:
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return 32;
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case nir_op_imax:
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case nir_op_umax:
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@ -2979,10 +2975,7 @@ lower_bit_size_callback(const nir_alu_instr *alu, void *_)
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case nir_op_ishr:
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case nir_op_ushr:
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case nir_op_ishl:
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case nir_op_iadd:
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case nir_op_uadd_sat:
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case nir_op_isub:
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case nir_op_imul:
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return (bit_size == 8 ||
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!(chip >= GFX8 && nir_dest_is_divergent(alu->dest.dest))) ? 32 : 0;
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default:
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