freedreno/all: Introduce fd_dev_id
Move away from using gpu_id as the primary means to identify which adreno we are running on, as future GPUs (starting with 7c3) stop providing a gpu_id as a new naming scheme is introduced. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12159>
This commit is contained in:
parent
7ba6100c2a
commit
7806843866
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@ -29,18 +29,24 @@
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* Table entry for a single GPU version
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*/
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struct fd_dev_rec {
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uint32_t gpu_id;
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struct fd_dev_id id;
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const char *name;
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const struct fd_dev_info *info;
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};
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#include "freedreno_devices.h"
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static bool
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dev_id_compare(const struct fd_dev_id *a, const struct fd_dev_id *b)
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{
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return a->gpu_id == b->gpu_id;
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}
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const struct fd_dev_info *
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fd_dev_info(uint32_t gpu_id)
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fd_dev_info(const struct fd_dev_id *id)
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{
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for (int i = 0; i < ARRAY_SIZE(fd_dev_recs); i++) {
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if (gpu_id == fd_dev_recs[i].gpu_id) {
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if (dev_id_compare(&fd_dev_recs[i].id, id)) {
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return fd_dev_recs[i].info;
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}
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}
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@ -48,10 +54,10 @@ fd_dev_info(uint32_t gpu_id)
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}
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const char *
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fd_dev_name(uint32_t gpu_id)
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fd_dev_name(const struct fd_dev_id *id)
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{
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for (int i = 0; i < ARRAY_SIZE(fd_dev_recs); i++) {
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if (gpu_id == fd_dev_recs[i].gpu_id) {
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if (dev_id_compare(&fd_dev_recs[i].id, id)) {
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return fd_dev_recs[i].name;
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}
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}
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@ -105,6 +105,28 @@ struct fd_dev_info {
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};
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};
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struct fd_dev_id {
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uint32_t gpu_id;
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};
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static inline uint32_t
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fd_dev_gpu_id(const struct fd_dev_id *id)
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{
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return id->gpu_id;
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}
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static uint8_t
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fd_dev_gen(const struct fd_dev_id *id)
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{
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return fd_dev_gpu_id(id) / 100;
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}
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static inline bool
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fd_dev_64b(const struct fd_dev_id *id)
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{
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return fd_dev_gen(id) >= 5;
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}
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/* per CCU GMEM amount reserved for depth cache for direct rendering */
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#define A6XX_CCU_DEPTH_SIZE (64 * 1024)
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/* per CCU GMEM amount reserved for color cache used by GMEM resolves
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@ -116,8 +138,8 @@ struct fd_dev_info {
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*/
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#define A6XX_CCU_GMEM_COLOR_SIZE (16 * 1024)
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const struct fd_dev_info * fd_dev_info(uint32_t gpu_id);
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const char * fd_dev_name(uint32_t gpu_id);
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const struct fd_dev_info * fd_dev_info(const struct fd_dev_id *id);
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const char * fd_dev_name(const struct fd_dev_id *id);
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#ifdef __cplusplus
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} /* end of extern "C" */
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@ -328,7 +328,7 @@ static const struct fd_dev_info __info${s.info_index(info)} = ${str(info)};
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static const struct fd_dev_rec fd_dev_recs[] = {
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%for id, info in s.gpus.items():
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{ ${id.gpu_id}, "${id.name}", &__info${s.info_index(info)} },
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{ {${id.gpu_id}}, "${id.name}", &__info${s.info_index(info)} },
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%endfor
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};
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"""
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@ -21,6 +21,7 @@
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* SOFTWARE.
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*/
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#include "freedreno_dev_info.h"
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#include "freedreno_uuid.h"
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#include <assert.h>
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@ -57,7 +58,7 @@ fd_get_driver_uuid(void *uuid)
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}
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void
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fd_get_device_uuid(void *uuid, unsigned gpu_id)
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fd_get_device_uuid(void *uuid, const struct fd_dev_id *id)
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{
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struct mesa_sha1 sha1_ctx;
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_mesa_sha1_init(&sha1_ctx);
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@ -83,7 +84,7 @@ fd_get_device_uuid(void *uuid, unsigned gpu_id)
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static const char *device_name = "freedreno";
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_mesa_sha1_update(&sha1_ctx, device_name, strlen(device_name));
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_mesa_sha1_update(&sha1_ctx, &gpu_id, sizeof(gpu_id));
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_mesa_sha1_update(&sha1_ctx, id, sizeof(*id));
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uint8_t sha1[SHA1_DIGEST_LENGTH];
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_mesa_sha1_final(&sha1_ctx, sha1);
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@ -24,7 +24,9 @@
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#ifndef __FREEDRENO_UUID_H__
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#define __FREEDRENO_UUID_H__
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struct fd_dev_id;
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void fd_get_driver_uuid(void *uuid);
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void fd_get_device_uuid(void *uuid, unsigned gpu_id);
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void fd_get_device_uuid(void *uuid, const struct fd_dev_id *id);
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#endif /* __FREEDRENO_UUID_H__ */
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@ -484,7 +484,7 @@ a6xx_read_perfcntrs(struct backend *b, uint64_t *results)
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}
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struct backend *
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a6xx_init(struct fd_device *dev, uint32_t gpu_id)
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a6xx_init(struct fd_device *dev, const struct fd_dev_id *dev_id)
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{
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struct a6xx_backend *a6xx_backend = calloc(1, sizeof(*a6xx_backend));
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@ -496,7 +496,7 @@ a6xx_init(struct fd_device *dev, uint32_t gpu_id)
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.read_perfcntrs = a6xx_read_perfcntrs,
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};
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a6xx_backend->compiler = ir3_compiler_create(dev, gpu_id, false);
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a6xx_backend->compiler = ir3_compiler_create(dev, dev_id, false);
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a6xx_backend->dev = dev;
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a6xx_backend->control_mem =
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@ -167,14 +167,14 @@ setup_counter(const char *name, struct perfcntr *c)
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}
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static struct perfcntr *
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parse_perfcntrs(uint32_t gpu_id, const char *perfcntrstr,
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parse_perfcntrs(const struct fd_dev_id *dev_id, const char *perfcntrstr,
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unsigned *num_perfcntrs)
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{
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struct perfcntr *counters = NULL;
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char *cnames, *s;
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unsigned cnt = 0;
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groups = fd_perfcntrs(gpu_id, &num_groups);
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groups = fd_perfcntrs(dev_id, &num_groups);
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enabled_counters = calloc(num_groups, sizeof(enabled_counters[0]));
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cnames = strdup(perfcntrstr);
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@ -243,19 +243,17 @@ main(int argc, char **argv)
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struct fd_device *dev = fd_device_new(fd);
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struct fd_pipe *pipe = fd_pipe_new(dev, FD_PIPE_3D);
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uint64_t val;
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fd_pipe_get_param(pipe, FD_GPU_ID, &val);
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uint32_t gpu_id = val;
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const struct fd_dev_id *dev_id = fd_pipe_dev_id(pipe);
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printf("got gpu_id: %u\n", gpu_id);
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printf("got gpu: %s\n", fd_dev_name(dev_id));
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struct backend *backend;
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switch (gpu_id) {
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case 600 ... 699:
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backend = a6xx_init(dev, gpu_id);
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switch (fd_dev_gen(dev_id)) {
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case 6:
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backend = a6xx_init(dev, dev_id);
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break;
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default:
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err(1, "unsupported gpu: a%u", gpu_id);
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err(1, "unsupported gpu generation: a%uxx", fd_dev_gen(dev_id));
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}
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struct kernel *kernel = backend->assemble(backend, in);
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@ -278,7 +276,7 @@ main(int argc, char **argv)
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if (!backend->set_perfcntrs) {
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err(1, "performance counters not supported");
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}
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perfcntrs = parse_perfcntrs(gpu_id, perfcntrstr, &num_perfcntrs);
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perfcntrs = parse_perfcntrs(dev_id, perfcntrstr, &num_perfcntrs);
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backend->set_perfcntrs(backend, perfcntrs, num_perfcntrs);
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}
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return (struct _to *)f; \
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}
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struct backend *a6xx_init(struct fd_device *dev, uint32_t gpu_id);
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struct backend *a6xx_init(struct fd_device *dev, const struct fd_dev_id *dev_id);
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/* for conditionally setting boolean flag(s): */
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#define COND(bool, val) ((bool) ? (val) : 0)
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@ -143,6 +143,7 @@ struct fd_pipe *fd_pipe_ref(struct fd_pipe *pipe);
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struct fd_pipe *fd_pipe_ref_locked(struct fd_pipe *pipe);
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void fd_pipe_del(struct fd_pipe *pipe);
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void fd_pipe_purge(struct fd_pipe *pipe);
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const struct fd_dev_id * fd_pipe_dev_id(struct fd_pipe *pipe);
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int fd_pipe_get_param(struct fd_pipe *pipe, enum fd_param_id param,
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uint64_t *value);
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int fd_pipe_wait(struct fd_pipe *pipe, const struct fd_fence *fence);
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p_atomic_set(&pipe->refcnt, 1);
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fd_pipe_get_param(pipe, FD_GPU_ID, &val);
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pipe->gpu_id = val;
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pipe->dev_id.gpu_id = val;
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pipe->control_mem = fd_bo_new(dev, sizeof(*pipe->control),
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0, "pipe-control");
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return pipe->funcs->get_param(pipe, param, value);
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}
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const struct fd_dev_id *
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fd_pipe_dev_id(struct fd_pipe *pipe)
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{
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return &pipe->dev_id;
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}
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int
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fd_pipe_wait(struct fd_pipe *pipe, const struct fd_fence *fence)
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{
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{
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uint32_t fence = ++pipe->last_fence;
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if (pipe->gpu_id >= 500) {
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if (fd_dev_64b(&pipe->dev_id)) {
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OUT_PKT7(ring, CP_EVENT_WRITE, 4);
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OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS));
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OUT_RELOC(ring, control_ptr(pipe, fence)); /* ADDR_LO/HI */
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#include "util/u_debug.h"
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#include "util/u_math.h"
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#include "freedreno_dev_info.h"
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#include "freedreno_drmif.h"
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#include "freedreno_ringbuffer.h"
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struct fd_pipe {
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struct fd_device *dev;
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enum fd_pipe_id id;
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uint32_t gpu_id;
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struct fd_dev_id dev_id;
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/**
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* Note refcnt is *not* atomic, but protected by table_lock, since the
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@ -512,7 +512,7 @@ msm_ringbuffer_emit_reloc(struct fd_ringbuffer *ring,
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ring->cur++;
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if (pipe->gpu_id >= 500) {
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if (fd_dev_64b(&pipe->dev_id)) {
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APPEND(msm_ring->cmd, relocs,
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(struct drm_msm_gem_submit_reloc){
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.reloc_idx = reloc_idx,
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@ -798,13 +798,13 @@ msm_ringbuffer_sp_init(struct msm_ringbuffer_sp *msm_ring, uint32_t size,
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ring->flags = flags;
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if (flags & _FD_RINGBUFFER_OBJECT) {
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if (msm_ring->u.pipe->gpu_id >= 500) {
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if (fd_dev_64b(&msm_ring->u.pipe->dev_id)) {
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ring->funcs = &ring_funcs_obj_64;
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} else {
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ring->funcs = &ring_funcs_obj_32;
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}
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} else {
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if (msm_ring->u.submit->pipe->gpu_id >= 500) {
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if (fd_dev_64b(&msm_ring->u.submit->pipe->dev_id)) {
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ring->funcs = &ring_funcs_nonobj_64;
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} else {
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ring->funcs = &ring_funcs_nonobj_32;
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@ -134,12 +134,7 @@ FreedrenoDriver::init_perfcnt()
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dev = fd_device_new(drm_device.fd);
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pipe = fd_pipe_new(dev, FD_PIPE_3D);
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if (fd_pipe_get_param(pipe, FD_GPU_ID, &val)) {
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PERFETTO_FATAL("Could not get GPU_ID");
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return false;
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}
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gpu_id = val;
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dev_id = fd_pipe_dev_id(pipe);
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if (fd_pipe_get_param(pipe, FD_MAX_FREQ, &val)) {
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PERFETTO_FATAL("Could not get MAX_FREQ");
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has_suspend_count = true;
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}
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perfcntrs = fd_perfcntrs(gpu_id, &num_perfcntrs);
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perfcntrs = fd_perfcntrs(fd_pipe_dev_id(pipe), &num_perfcntrs);
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if (num_perfcntrs == 0) {
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PERFETTO_FATAL("No hw counters available");
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return false;
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@ -163,12 +158,12 @@ FreedrenoDriver::init_perfcnt()
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assigned_counters.resize(num_perfcntrs);
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assigned_counters.assign(assigned_counters.size(), 0);
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switch (gpu_id) {
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case 600 ... 699:
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switch (fd_dev_gen(dev_id)) {
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case 6:
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setup_a6xx_counters();
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break;
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default:
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PERFETTO_FATAL("Unsupported GPU: a%03u", gpu_id);
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PERFETTO_FATAL("Unsupported GPU: a%03u", fd_dev_gpu_id(dev_id));
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return false;
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}
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for (auto countable : countables)
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countable.resolve();
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info = fd_dev_info(gpu_id);
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info = fd_dev_info(dev_id);
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io = fd_dt_find_io();
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if (!io) {
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@ -32,7 +32,7 @@ public:
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private:
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struct fd_device *dev;
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struct fd_pipe *pipe;
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uint32_t gpu_id;
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const struct fd_dev_id *dev_id;
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uint32_t max_freq;
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uint32_t next_counter_id;
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uint32_t next_countable_id;
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@ -69,7 +69,7 @@ ir3_compiler_destroy(struct ir3_compiler *compiler)
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}
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struct ir3_compiler *
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ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id,
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ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
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bool robust_ubo_access)
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{
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struct ir3_compiler *compiler = rzalloc(NULL, struct ir3_compiler);
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}
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compiler->dev = dev;
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compiler->gpu_id = gpu_id;
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compiler->gen = gpu_id / 100;
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compiler->dev_id = dev_id;
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compiler->gen = fd_dev_gen(dev_id);
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compiler->robust_ubo_access = robust_ubo_access;
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/* All known GPU's have 32k local memory (aka shared) */
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compiler->has_pvtmem = true;
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compiler->tess_use_shared =
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fd_dev_info(compiler->gpu_id)->a6xx.tess_use_shared;
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fd_dev_info(compiler->dev_id)->a6xx.tess_use_shared;
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} else {
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compiler->max_const_pipeline = 512;
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compiler->max_const_geom = 512;
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@ -139,7 +139,7 @@ ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id,
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if (compiler->gen >= 6) {
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compiler->reg_size_vec4 =
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fd_dev_info(compiler->gpu_id)->a6xx.reg_size_vec4;
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fd_dev_info(compiler->dev_id)->a6xx.reg_size_vec4;
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} else if (compiler->gen >= 4) {
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/* On a4xx-a5xx, using r24.x and above requires using the smallest
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* threadsize.
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@ -30,6 +30,8 @@
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#include "util/disk_cache.h"
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#include "util/log.h"
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#include "freedreno_dev_info.h"
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#include "ir3.h"
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struct ir3_ra_reg_set;
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@ -37,7 +39,7 @@ struct ir3_shader;
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struct ir3_compiler {
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struct fd_device *dev;
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uint32_t gpu_id;
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const struct fd_dev_id *dev_id;
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uint8_t gen;
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uint32_t shader_count;
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||||
|
@ -157,7 +159,8 @@ struct ir3_compiler {
|
|||
};
|
||||
|
||||
void ir3_compiler_destroy(struct ir3_compiler *compiler);
|
||||
struct ir3_compiler *ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id,
|
||||
struct ir3_compiler *ir3_compiler_create(struct fd_device *dev,
|
||||
const struct fd_dev_id *dev_id,
|
||||
bool robust_ubo_access);
|
||||
|
||||
void ir3_disk_cache_init(struct ir3_compiler *compiler);
|
||||
|
@ -175,7 +178,7 @@ int ir3_compile_shader_nir(struct ir3_compiler *compiler,
|
|||
static inline unsigned
|
||||
ir3_pointer_size(struct ir3_compiler *compiler)
|
||||
{
|
||||
return (compiler->gpu_id >= 500) ? 2 : 1;
|
||||
return fd_dev_64b(compiler->dev_id) ? 2 : 1;
|
||||
}
|
||||
|
||||
enum ir3_shader_debug {
|
||||
|
|
|
@ -51,12 +51,7 @@ ir3_disk_cache_init(struct ir3_compiler *compiler)
|
|||
if (ir3_shader_debug & IR3_DBG_NOCACHE)
|
||||
return;
|
||||
|
||||
/* array length = print length + nul char + 1 extra to verify it's unused */
|
||||
char renderer[7];
|
||||
ASSERTED int len =
|
||||
snprintf(renderer, sizeof(renderer), "FD%03d", compiler->gpu_id);
|
||||
assert(len == sizeof(renderer) - 2);
|
||||
|
||||
const char *renderer = fd_dev_name(compiler->dev_id);
|
||||
const struct build_id_note *note =
|
||||
build_id_find_nhdr_for_addr(ir3_disk_cache_init);
|
||||
assert(note && build_id_length(note) == 20); /* sha1 */
|
||||
|
|
|
@ -697,7 +697,7 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
|
|||
|
||||
isa_decode(bin, so->info.sizedwords * 4, out,
|
||||
&(struct isa_decode_options){
|
||||
.gpu_id = ir->compiler->gpu_id,
|
||||
.gpu_id = fd_dev_gpu_id(ir->compiler->dev_id),
|
||||
.show_errors = true,
|
||||
.branch_labels = true,
|
||||
});
|
||||
|
|
|
@ -146,7 +146,11 @@ main(int argc, char **argv)
|
|||
struct ir3_compiler *c;
|
||||
int result = 0;
|
||||
|
||||
c = ir3_compiler_create(NULL, 630, false);
|
||||
struct fd_dev_id dev_id = {
|
||||
.gpu_id = 630,
|
||||
};
|
||||
|
||||
c = ir3_compiler_create(NULL, &dev_id, false);
|
||||
|
||||
for (int i = 0; i < ARRAY_SIZE(tests); i++) {
|
||||
const struct test *test = &tests[i];
|
||||
|
|
|
@ -376,6 +376,7 @@ main(int argc, char **argv)
|
|||
}
|
||||
|
||||
struct ir3_compiler *compilers[10] = {};
|
||||
struct fd_dev_id dev_ids[ARRAY_SIZE(compilers)];
|
||||
|
||||
for (int i = 0; i < ARRAY_SIZE(tests); i++) {
|
||||
const struct test *test = &tests[i];
|
||||
|
@ -417,7 +418,8 @@ main(int argc, char **argv)
|
|||
|
||||
unsigned gen = test->gpu_id / 100;
|
||||
if (!compilers[gen]) {
|
||||
compilers[gen] = ir3_compiler_create(NULL, test->gpu_id, false);
|
||||
dev_ids[gen].gpu_id = test->gpu_id;
|
||||
compilers[gen] = ir3_compiler_create(NULL, &dev_ids[gen], false);
|
||||
}
|
||||
|
||||
FILE *fasm =
|
||||
|
|
|
@ -842,7 +842,10 @@ main(int argc, char **argv)
|
|||
find_device();
|
||||
|
||||
const struct fd_perfcntr_group *groups;
|
||||
groups = fd_perfcntrs((dev.chipid >> 24) * 100, &dev.ngroups);
|
||||
struct fd_dev_id dev_id = {
|
||||
.gpu_id = (dev.chipid >> 24) * 100,
|
||||
};
|
||||
groups = fd_perfcntrs(&dev_id, &dev.ngroups);
|
||||
if (!groups) {
|
||||
errx(1, "no perfcntr support");
|
||||
}
|
||||
|
|
|
@ -38,16 +38,16 @@ extern const struct fd_perfcntr_group a6xx_perfcntr_groups[];
|
|||
extern const unsigned a6xx_num_perfcntr_groups;
|
||||
|
||||
const struct fd_perfcntr_group *
|
||||
fd_perfcntrs(unsigned gpu_id, unsigned *count)
|
||||
fd_perfcntrs(const struct fd_dev_id *id, unsigned *count)
|
||||
{
|
||||
switch (gpu_id) {
|
||||
case 200 ... 299:
|
||||
switch (fd_dev_gen(id)) {
|
||||
case 2:
|
||||
*count = a2xx_num_perfcntr_groups;
|
||||
return a2xx_perfcntr_groups;
|
||||
case 500 ... 599:
|
||||
case 5:
|
||||
*count = a5xx_num_perfcntr_groups;
|
||||
return a5xx_perfcntr_groups;
|
||||
case 600 ... 699:
|
||||
case 6:
|
||||
*count = a6xx_num_perfcntr_groups;
|
||||
return a6xx_perfcntr_groups;
|
||||
default:
|
||||
|
|
|
@ -29,6 +29,8 @@
|
|||
|
||||
#include "util/macros.h"
|
||||
|
||||
#include "freedreno_dev_info.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
@ -95,7 +97,7 @@ struct fd_perfcntr_group {
|
|||
const struct fd_perfcntr_countable *countables;
|
||||
};
|
||||
|
||||
const struct fd_perfcntr_group *fd_perfcntrs(unsigned gpu_id, unsigned *count);
|
||||
const struct fd_perfcntr_group *fd_perfcntrs(const struct fd_dev_id *id, unsigned *count);
|
||||
|
||||
#define COUNTER(_sel, _lo, _hi) { \
|
||||
.select_reg = REG(_sel), .counter_reg_lo = REG(_lo), \
|
||||
|
|
|
@ -193,15 +193,15 @@ tu_physical_device_init(struct tu_physical_device *device,
|
|||
{
|
||||
VkResult result = VK_SUCCESS;
|
||||
|
||||
device->name = fd_dev_name(device->gpu_id);
|
||||
device->name = fd_dev_name(&device->dev_id);
|
||||
|
||||
const struct fd_dev_info *info = fd_dev_info(device->gpu_id);
|
||||
const struct fd_dev_info *info = fd_dev_info(&device->dev_id);
|
||||
if (!info) {
|
||||
result = vk_startup_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
|
||||
"device %s is unsupported", device->name);
|
||||
return result;
|
||||
}
|
||||
switch (device->gpu_id / 100) {
|
||||
switch (fd_dev_gen(&device->dev_id)) {
|
||||
case 6:
|
||||
device->info = info;
|
||||
device->ccu_offset_bypass = device->info->num_ccu * A6XX_CCU_DEPTH_SIZE;
|
||||
|
@ -213,7 +213,7 @@ tu_physical_device_init(struct tu_physical_device *device,
|
|||
"device %s is unsupported", device->name);
|
||||
return result;
|
||||
}
|
||||
if (tu_device_get_cache_uuid(device->gpu_id, device->cache_uuid)) {
|
||||
if (tu_device_get_cache_uuid(fd_dev_gpu_id(&device->dev_id), device->cache_uuid)) {
|
||||
result = vk_startup_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
|
||||
"cannot generate UUID");
|
||||
return result;
|
||||
|
@ -229,7 +229,7 @@ tu_physical_device_init(struct tu_physical_device *device,
|
|||
vk_warn_non_conformant_implementation("tu");
|
||||
|
||||
fd_get_driver_uuid(device->driver_uuid);
|
||||
fd_get_device_uuid(device->device_uuid, device->gpu_id);
|
||||
fd_get_device_uuid(device->device_uuid, &device->dev_id);
|
||||
|
||||
struct vk_device_extension_table supported_extensions;
|
||||
get_device_extensions(device, &supported_extensions);
|
||||
|
@ -1328,7 +1328,7 @@ tu_CreateDevice(VkPhysicalDevice physicalDevice,
|
|||
}
|
||||
}
|
||||
|
||||
device->compiler = ir3_compiler_create(NULL, physical_device->gpu_id,
|
||||
device->compiler = ir3_compiler_create(NULL, &physical_device->dev_id,
|
||||
robust_buffer_access2);
|
||||
if (!device->compiler) {
|
||||
result = vk_startup_errorf(physical_device->instance,
|
||||
|
|
|
@ -445,7 +445,7 @@ tu_drm_device_init(struct tu_physical_device *device,
|
|||
device->master_fd = master_fd;
|
||||
device->local_fd = fd;
|
||||
|
||||
if (tu_drm_get_gpu_id(device, &device->gpu_id)) {
|
||||
if (tu_drm_get_gpu_id(device, &device->dev_id.gpu_id)) {
|
||||
result = vk_startup_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
|
||||
"could not get GPU ID");
|
||||
goto fail;
|
||||
|
|
|
@ -239,7 +239,7 @@ tu_enumerate_devices(struct tu_instance *instance)
|
|||
device->master_fd = -1;
|
||||
device->local_fd = fd;
|
||||
|
||||
device->gpu_id =
|
||||
device->dev_id.gpu_id =
|
||||
((info.chip_id >> 24) & 0xff) * 100 +
|
||||
((info.chip_id >> 16) & 0xff) * 10 +
|
||||
((info.chip_id >> 8) & 0xff);
|
||||
|
|
|
@ -204,12 +204,12 @@ struct tu_physical_device
|
|||
int local_fd;
|
||||
int master_fd;
|
||||
|
||||
unsigned gpu_id;
|
||||
uint32_t gmem_size;
|
||||
uint64_t gmem_base;
|
||||
uint32_t ccu_offset_gmem;
|
||||
uint32_t ccu_offset_bypass;
|
||||
|
||||
struct fd_dev_id dev_id;
|
||||
const struct fd_dev_info *info;
|
||||
|
||||
int msm_major_version;
|
||||
|
|
|
@ -268,7 +268,7 @@ tu_CreateQueryPool(VkDevice _device,
|
|||
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
|
||||
|
||||
if (pCreateInfo->queryType == VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR) {
|
||||
pool->perf_group = fd_perfcntrs(device->physical_device->gpu_id,
|
||||
pool->perf_group = fd_perfcntrs(&device->physical_device->dev_id,
|
||||
&pool->perf_group_count);
|
||||
|
||||
pool->counter_index_count = perf_query_info->counterIndexCount;
|
||||
|
@ -1422,7 +1422,7 @@ tu_EnumeratePhysicalDeviceQueueFamilyPerformanceQueryCountersKHR(
|
|||
uint32_t desc_count = *pCounterCount;
|
||||
uint32_t group_count;
|
||||
const struct fd_perfcntr_group *group =
|
||||
fd_perfcntrs(phydev->gpu_id, &group_count);
|
||||
fd_perfcntrs(&phydev->dev_id, &group_count);
|
||||
|
||||
VK_OUTARRAY_MAKE(out, pCounters, pCounterCount);
|
||||
VK_OUTARRAY_MAKE(out_desc, pCounterDescriptions, &desc_count);
|
||||
|
@ -1470,7 +1470,7 @@ tu_GetPhysicalDeviceQueueFamilyPerformanceQueryPassesKHR(
|
|||
uint32_t group_count = 0;
|
||||
uint32_t gid = 0, cid = 0, n_passes;
|
||||
const struct fd_perfcntr_group *group =
|
||||
fd_perfcntrs(phydev->gpu_id, &group_count);
|
||||
fd_perfcntrs(&phydev->dev_id, &group_count);
|
||||
|
||||
uint32_t counters_requested[group_count];
|
||||
memset(counters_requested, 0x0, sizeof(counters_requested));
|
||||
|
|
|
@ -108,7 +108,7 @@ bool fd_binning_enabled = true;
|
|||
static const char *
|
||||
fd_screen_get_name(struct pipe_screen *pscreen)
|
||||
{
|
||||
return fd_dev_name(fd_screen(pscreen)->gpu_id);
|
||||
return fd_dev_name(fd_screen(pscreen)->dev_id);
|
||||
}
|
||||
|
||||
static const char *
|
||||
|
@ -914,7 +914,7 @@ fd_screen_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
|
|||
{
|
||||
struct fd_screen *screen = fd_screen(pscreen);
|
||||
|
||||
fd_get_device_uuid(uuid, screen->gpu_id);
|
||||
fd_get_device_uuid(uuid, screen->dev_id);
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -978,6 +978,8 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro,
|
|||
screen->has_timestamp = true;
|
||||
}
|
||||
|
||||
screen->dev_id = fd_pipe_dev_id(screen->pipe);
|
||||
|
||||
if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
|
||||
DBG("could not get gpu-id");
|
||||
goto fail;
|
||||
|
@ -995,7 +997,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro,
|
|||
((core & 0xff) << 24);
|
||||
}
|
||||
screen->chip_id = val;
|
||||
screen->gen = screen->chip_id >> 24;
|
||||
screen->gen = fd_dev_gen(screen->dev_id);
|
||||
|
||||
if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
|
||||
DBG("could not get # of rings");
|
||||
|
@ -1012,18 +1014,18 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro,
|
|||
|
||||
/* parse driconf configuration now for device specific overrides: */
|
||||
driParseConfigFiles(config->options, config->options_info, 0, "msm",
|
||||
NULL, fd_dev_name(screen->gpu_id), NULL, 0, NULL, 0);
|
||||
NULL, fd_dev_name(screen->dev_id), NULL, 0, NULL, 0);
|
||||
|
||||
struct sysinfo si;
|
||||
sysinfo(&si);
|
||||
screen->ram_size = si.totalram;
|
||||
|
||||
DBG("Pipe Info:");
|
||||
DBG(" GPU-id: %d", screen->gpu_id);
|
||||
DBG(" GPU-id: %s", fd_dev_name(screen->dev_id));
|
||||
DBG(" Chip-id: 0x%08x", screen->chip_id);
|
||||
DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
|
||||
|
||||
const struct fd_dev_info *info = fd_dev_info(screen->gpu_id);
|
||||
const struct fd_dev_info *info = fd_dev_info(screen->dev_id);
|
||||
if (!info) {
|
||||
mesa_loge("unsupported GPU: a%03d", screen->gpu_id);
|
||||
goto fail;
|
||||
|
@ -1071,7 +1073,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro,
|
|||
|
||||
if (FD_DBG(PERFC)) {
|
||||
screen->perfcntr_groups =
|
||||
fd_perfcntrs(screen->gpu_id, &screen->num_perfcntr_groups);
|
||||
fd_perfcntrs(screen->dev_id, &screen->num_perfcntr_groups);
|
||||
}
|
||||
|
||||
/* NOTE: don't enable if we have too old of a kernel to support
|
||||
|
|
|
@ -81,6 +81,7 @@ struct fd_screen {
|
|||
uint64_t gmem_base;
|
||||
uint32_t gmemsize_bytes;
|
||||
|
||||
const struct fd_dev_id *dev_id;
|
||||
uint8_t gen; /* GPU (major) generation */
|
||||
uint32_t gpu_id; /* 220, 305, etc */
|
||||
uint32_t chip_id; /* coreid:8 majorrev:8 minorrev:8 patch:8 */
|
||||
|
|
|
@ -159,15 +159,18 @@ main(int argc, char **argv)
|
|||
usage();
|
||||
}
|
||||
|
||||
struct fd_dev_id dev_id = {
|
||||
.gpu_id = gpu_info->gpu_id,
|
||||
};
|
||||
/* Setup a fake screen with enough GMEM related configuration
|
||||
* to make gmem_stateobj_init() happy:
|
||||
*/
|
||||
struct fd_screen screen = {
|
||||
.gpu_id = gpu_info->gpu_id,
|
||||
.dev_id = &dev_id,
|
||||
.gmemsize_bytes = gpu_info->gmemsize_bytes,
|
||||
};
|
||||
|
||||
screen.info = fd_dev_info(gpu_info->gpu_id);
|
||||
screen.info = fd_dev_info(&dev_id);
|
||||
|
||||
/* And finally run thru all the GMEM keys: */
|
||||
for (int i = 0; i < ARRAY_SIZE(keys); i++) {
|
||||
|
|
|
@ -362,7 +362,10 @@ main(int argc, char **argv)
|
|||
|
||||
nir_shader *nir;
|
||||
|
||||
compiler = ir3_compiler_create(NULL, gpu_id, false);
|
||||
struct fd_dev_id dev_id = {
|
||||
.gpu_id = gpu_id,
|
||||
};
|
||||
compiler = ir3_compiler_create(NULL, &dev_id, false);
|
||||
|
||||
if (from_tgsi) {
|
||||
struct tgsi_token toks[65536];
|
||||
|
|
|
@ -515,7 +515,7 @@ ir3_screen_init(struct pipe_screen *pscreen)
|
|||
{
|
||||
struct fd_screen *screen = fd_screen(pscreen);
|
||||
|
||||
screen->compiler = ir3_compiler_create(screen->dev, screen->gpu_id, false);
|
||||
screen->compiler = ir3_compiler_create(screen->dev, screen->dev_id, false);
|
||||
|
||||
/* TODO do we want to limit things to # of fast cores, or just limit
|
||||
* based on total # of both big and little cores. The little cores
|
||||
|
|
Loading…
Reference in New Issue