i965: Add #defines for Memory Object Control State fields on Gen7-7.5.
The L3 controls are identical on all platforms, but LLC differs: - Ivybridge has a "cache in LLC" flag - Baytrail has no LLC, but instead has a snoop bit: "data accesses in this page must be snooped in the CPU caches." - Haswell has writeback/uncached flags for LLC and eLLC (eDRAM). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
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@ -1730,6 +1730,32 @@ enum brw_wm_barycentric_interp_mode {
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*/
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#define BRW_MAX_NUM_BUFFER_ENTRIES (1 << 27)
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/* Memory Object Control State:
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* Specifying zero for L3 means "uncached in L3", at least on Haswell
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* and Baytrail, since there are no PTE flags for setting L3 cacheability.
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* On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
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* may still respect that.
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*/
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#define GEN7_MOCS_L3 1
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/* Ivybridge only: cache in LLC.
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* Specifying zero here means to use the PTE values set by the kernel;
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* non-zero overrides the PTE values.
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*/
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#define IVB_MOCS_LLC (1 << 1)
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/* Baytrail only: snoop in CPU cache */
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#define BYT_MOCS_SNOOP (1 << 1)
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/* Haswell only: LLC/eLLC controls (write-back or uncached).
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* Specifying zero here means to use the PTE values set by the kernel,
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* which is useful since it offers additional control (write-through
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* cacheing and age). Non-zero overrides the PTE values.
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*/
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#define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
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#define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
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#define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
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#include "intel_chipset.h"
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#endif
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