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r600g: cleanup r600_resource_texture in favor of radeon_surface

This commit is contained in:
Marek Olšák 2012-08-12 18:40:33 +02:00
parent 362a25aac5
commit 773ff5705f
5 changed files with 20 additions and 29 deletions
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10
src/gallium/drivers/r600/evergreen_compute_internal.c
View File

@ -523,7 +523,7 @@ void evergreen_set_tex_resource(
depth = view->base.texture->depth0;
pitch = align(tmp->surface.level[0].nblk_x *
util_format_get_blockwidth(tmp->real_format), 8);
util_format_get_blockwidth(tmp->resource.b.b.format), 8);
array_mode = tmp->array_mode[0];
tile_type = tmp->tile_type;
@ -540,8 +540,8 @@ void evergreen_set_tex_resource(
evergreen_emit_raw_value(res, (S_030004_TEX_HEIGHT(height - 1) |
S_030004_TEX_DEPTH(depth - 1) |
S_030004_ARRAY_MODE(array_mode)));
evergreen_emit_raw_value(res, tmp->offset[0] >> 8);
evergreen_emit_raw_value(res, tmp->offset[0] >> 8);
evergreen_emit_raw_value(res, tmp->surface.level[0].offset >> 8);
evergreen_emit_raw_value(res, tmp->surface.level[0].offset >> 8);
evergreen_emit_raw_value(res, (word4 |
S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
S_030010_ENDIAN_SWAP(endian) |
@ -558,7 +558,9 @@ void evergreen_set_tex_resource(
res->usage = RADEON_USAGE_READ;
res->coher_bo_size = tmp->offset[0] + util_format_get_blockwidth(tmp->real_format)*view->base.texture->width0*height*depth;
res->coher_bo_size = tmp->surface.level[0].offset +
util_format_get_blockwidth(tmp->resource.b.b.format) *
view->base.texture->width0*height*depth;
r600_inval_texture_cache(pipe->ctx);

6
src/gallium/drivers/r600/evergreen_state.c
View File

@ -1090,11 +1090,11 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
S_030004_TEX_DEPTH(depth - 1) |
S_030004_ARRAY_MODE(array_mode));
view->tex_resource_words[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
view->tex_resource_words[2] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
if (state->u.tex.last_level && texture->nr_samples <= 1) {
view->tex_resource_words[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
view->tex_resource_words[3] = (tmp->surface.level[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
} else {
view->tex_resource_words[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
view->tex_resource_words[3] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
}
view->tex_resource_words[4] = (word4 |
S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |

6
src/gallium/drivers/r600/r600_blit.c
View File

@ -178,7 +178,7 @@ void r600_blit_uncompress_depth(struct pipe_context *ctx,
r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
}
surf_tmpl.format = texture->real_format;
surf_tmpl.format = texture->resource.b.b.format;
surf_tmpl.u.tex.level = level;
surf_tmpl.u.tex.first_layer = layer;
surf_tmpl.u.tex.last_layer = layer;
@ -186,7 +186,7 @@ void r600_blit_uncompress_depth(struct pipe_context *ctx,
zsurf = ctx->create_surface(ctx, &texture->resource.b.b, &surf_tmpl);
surf_tmpl.format = flushed_depth_texture->real_format;
surf_tmpl.format = flushed_depth_texture->resource.b.b.format;
surf_tmpl.u.tex.level = level;
surf_tmpl.u.tex.first_layer = layer;
surf_tmpl.u.tex.last_layer = layer;
@ -472,7 +472,7 @@ static void r600_compressed_to_blittable(struct pipe_resource *tex,
struct texture_orig_info *orig)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex;
unsigned pixsize = util_format_get_blocksize(rtex->real_format);
unsigned pixsize = util_format_get_blocksize(rtex->resource.b.b.format);
int new_format;
int new_height, new_width;

8
src/gallium/drivers/r600/r600_resource.h
View File

@ -45,14 +45,6 @@ struct r600_resource_global {
struct r600_resource_texture {
struct r600_resource resource;
/* If this resource is a depth-stencil buffer on evergreen, this contains
* the depth part of the format. There is a separate stencil resource
* for the stencil buffer below. */
enum pipe_format real_format;
unsigned offset[PIPE_MAX_TEXTURE_LEVELS];
unsigned pitch_in_bytes[PIPE_MAX_TEXTURE_LEVELS]; /* transfer */
unsigned layer_size[PIPE_MAX_TEXTURE_LEVELS];
unsigned array_mode[PIPE_MAX_TEXTURE_LEVELS];
unsigned pitch_override;
unsigned size;

19
src/gallium/drivers/r600/r600_texture.c
View File

@ -61,7 +61,8 @@ static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600
unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
unsigned level, unsigned layer)
{
return rtex->offset[level] + layer * rtex->layer_size[level];
return rtex->surface.level[level].offset +
layer * rtex->surface.level[level].slice_size;
}
static int r600_init_surface(struct r600_screen *rscreen,
@ -182,9 +183,6 @@ static int r600_setup_surface(struct pipe_screen *screen,
}
}
for (i = 0; i <= ptex->last_level; i++) {
rtex->offset[i] = rtex->surface.level[i].offset;
rtex->layer_size[i] = rtex->surface.level[i].slice_size;
rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes;
switch (rtex->surface.level[i].mode) {
case RADEON_SURF_MODE_LINEAR_ALIGNED:
rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
@ -223,10 +221,10 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
surface->tile_split,
surface->stencil_tile_split,
surface->mtilea,
rtex->pitch_in_bytes[0]);
rtex->surface.level[0].pitch_bytes);
return rscreen->ws->buffer_get_handle(resource->buf,
rtex->pitch_in_bytes[0], whandle);
rtex->surface.level[0].pitch_bytes, whandle);
}
static void r600_texture_destroy(struct pipe_screen *screen,
@ -277,7 +275,6 @@ r600_texture_create_object(struct pipe_screen *screen,
pipe_reference_init(&resource->b.b.reference, 1);
resource->b.b.screen = screen;
rtex->pitch_override = pitch_in_bytes_override;
rtex->real_format = base->format;
/* don't include stencil-only formats which we don't support for rendering */
rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
@ -519,7 +516,7 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
box->z, box->z + box->depth - 1,
0, 0);
trans->transfer.stride = staging_depth->pitch_in_bytes[level];
trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
trans->staging = (struct r600_resource*)staging_depth;
return &trans->transfer;
@ -555,7 +552,7 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
}
trans->transfer.stride =
((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0];
((struct r600_resource_texture *)trans->staging)->surface.level[0].pitch_bytes;
if (usage & PIPE_TRANSFER_READ) {
r600_copy_to_staging_texture(ctx, trans);
/* Always referenced in the blit. */
@ -563,8 +560,8 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
}
return &trans->transfer;
}
trans->transfer.stride = rtex->pitch_in_bytes[level];
trans->transfer.layer_stride = rtex->layer_size[level];
trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
trans->offset = r600_texture_get_offset(rtex, level, box->z);
return &trans->transfer;
}