ir3: update ir3_const_state comment
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17570>
This commit is contained in:
parent
23220c86d9
commit
76ea28b9d0
|
@ -135,41 +135,27 @@ struct ir3_ubo_analysis_state {
|
||||||
};
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Describes the layout of shader consts. This includes:
|
* Describes the layout of shader consts in the const register file.
|
||||||
* + User consts + driver lowered UBO ranges
|
|
||||||
* + SSBO sizes
|
|
||||||
* + Image sizes/dimensions
|
|
||||||
* + Driver params (ie. IR3_DP_*)
|
|
||||||
* + TFBO addresses (for generations that do not have hardware streamout)
|
|
||||||
* + Lowered immediates
|
|
||||||
*
|
|
||||||
* For consts needed to pass internal values to shader which may or may not
|
|
||||||
* be required, rather than allocating worst-case const space, we scan the
|
|
||||||
* shader and allocate consts as-needed:
|
|
||||||
*
|
|
||||||
* + SSBO sizes: only needed if shader has a get_ssbo_size intrinsic
|
|
||||||
* for a given SSBO
|
|
||||||
*
|
|
||||||
* + Image dimensions: needed to calculate pixel offset, but only for
|
|
||||||
* images that have a image_store intrinsic
|
|
||||||
*
|
*
|
||||||
* Layout of constant registers, each section aligned to vec4. Note
|
* Layout of constant registers, each section aligned to vec4. Note
|
||||||
* that pointer size (ubo, etc) changes depending on generation.
|
* that pointer size (ubo, etc) changes depending on generation.
|
||||||
*
|
*
|
||||||
* user consts
|
* + user consts: only used for turnip push consts
|
||||||
* preamble consts
|
* + lowered UBO ranges
|
||||||
* UBO addresses
|
* + preamble consts
|
||||||
* SSBO sizes
|
* + UBO addresses: turnip is bindless and these are wasted
|
||||||
* image dimensions
|
* + image dimensions: a5xx only; needed to calculate pixel offset, but only
|
||||||
* if (vertex shader) {
|
* for images that have image_{load,store,size,atomic*} intrinsics
|
||||||
* driver params (IR3_DP_VS_COUNT)
|
* + kernel params: cl only
|
||||||
* if (stream_output.num_outputs > 0)
|
* + driver params: these are stage-dependent; see ir3_driver_param
|
||||||
* stream-out addresses
|
* + TFBO addresses: only for vs on a3xx/a4xx
|
||||||
* } else if (compute_shader) {
|
* + primitive params: these are stage-dependent
|
||||||
* kernel params
|
* vs, gs: uvec4(primitive_stride, vertex_stride, 0, 0)
|
||||||
* driver params (IR3_DP_CS_COUNT)
|
* hs, ds: uvec4(primitive_stride, vertex_stride,
|
||||||
* }
|
* patch_stride, patch_vertices_in)
|
||||||
* immediates
|
* uvec4(tess_param_base, tess_factor_base)
|
||||||
|
* + primitive map
|
||||||
|
* + lowered immediates
|
||||||
*
|
*
|
||||||
* Immediates go last mostly because they are inserted in the CP pass
|
* Immediates go last mostly because they are inserted in the CP pass
|
||||||
* after the nir -> ir3 frontend.
|
* after the nir -> ir3 frontend.
|
||||||
|
|
Loading…
Reference in New Issue