panfrost: Merge attribute packing routines
In preparation for streamlining the packing, we need related code in one place. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6326>
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@ -1337,23 +1337,6 @@ panfrost_emit_sampler_descriptors(struct panfrost_batch *batch,
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postfix->sampler_descriptor = T.gpu;
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}
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void
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panfrost_emit_vertex_attr_meta(struct panfrost_batch *batch,
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struct mali_vertex_tiler_postfix *vertex_postfix)
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{
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struct panfrost_context *ctx = batch->ctx;
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if (!ctx->vertex)
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return;
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struct panfrost_vertex_state *so = ctx->vertex;
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panfrost_vertex_state_upd_attr_offs(ctx, vertex_postfix);
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vertex_postfix->attribute_meta = panfrost_pool_upload(&batch->pool, so->hw,
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sizeof(*so->hw) *
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PAN_MAX_ATTRIBUTE);
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}
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void
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panfrost_emit_vertex_data(struct panfrost_batch *batch,
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struct mali_vertex_tiler_postfix *vertex_postfix)
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@ -1456,10 +1439,58 @@ panfrost_emit_vertex_data(struct panfrost_batch *batch,
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panfrost_instance_id(ctx->padded_count, &attrs[k]);
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so->hw[PAN_INSTANCE_ID].index = k++;
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/* Upload whatever we emitted and go */
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/* Fixup offsets for the second pass. Recall that the hardware
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* calculates attribute addresses as:
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*
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* addr = base + (stride * vtx) + src_offset;
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*
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* However, on Mali, base must be aligned to 64-bytes, so we
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* instead let:
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*
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* base' = base & ~63 = base - (base & 63)
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*
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* To compensate when using base' (see emit_vertex_data), we have
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* to adjust src_offset by the masked off piece:
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*
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* addr' = base' + (stride * vtx) + (src_offset + (base & 63))
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* = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
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* = base + (stride * vtx) + src_offset
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* = addr;
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*
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* QED.
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*/
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unsigned start = vertex_postfix->offset_start;
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for (unsigned i = 0; i < so->num_elements; ++i) {
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unsigned vbi = so->pipe[i].vertex_buffer_index;
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struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi];
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/* Adjust by the masked off bits of the offset. Make sure we
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* read src_offset from so->hw (which is not GPU visible)
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* rather than target (which is) due to caching effects */
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unsigned src_offset = so->pipe[i].src_offset;
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/* BOs aligned to 4k so guaranteed aligned to 64 */
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src_offset += (buf->buffer_offset & 63);
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/* Also, somewhat obscurely per-instance data needs to be
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* offset in response to a delayed start in an indexed draw */
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if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start)
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src_offset -= buf->stride * start;
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so->hw[i].src_offset = src_offset;
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}
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vertex_postfix->attributes = panfrost_pool_upload(&batch->pool, attrs,
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k * sizeof(*attrs));
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vertex_postfix->attribute_meta = panfrost_pool_upload(&batch->pool, so->hw,
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sizeof(*so->hw) *
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PAN_MAX_ATTRIBUTE);
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}
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static mali_ptr
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@ -80,10 +80,6 @@ panfrost_emit_sampler_descriptors(struct panfrost_batch *batch,
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enum pipe_shader_type stage,
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struct mali_vertex_tiler_postfix *postfix);
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void
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panfrost_emit_vertex_attr_meta(struct panfrost_batch *batch,
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struct mali_vertex_tiler_postfix *vertex_postfix);
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void
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panfrost_emit_vertex_data(struct panfrost_batch *batch,
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struct mali_vertex_tiler_postfix *vertex_postfix);
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@ -163,61 +163,6 @@ panfrost_writes_point_size(struct panfrost_context *ctx)
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return vs->writes_point_size && ctx->active_prim == PIPE_PRIM_POINTS;
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}
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void
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panfrost_vertex_state_upd_attr_offs(struct panfrost_context *ctx,
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struct mali_vertex_tiler_postfix *vertex_postfix)
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{
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if (!ctx->vertex)
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return;
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struct panfrost_vertex_state *so = ctx->vertex;
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/* Fixup offsets for the second pass. Recall that the hardware
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* calculates attribute addresses as:
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*
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* addr = base + (stride * vtx) + src_offset;
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*
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* However, on Mali, base must be aligned to 64-bytes, so we
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* instead let:
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*
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* base' = base & ~63 = base - (base & 63)
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*
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* To compensate when using base' (see emit_vertex_data), we have
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* to adjust src_offset by the masked off piece:
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*
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* addr' = base' + (stride * vtx) + (src_offset + (base & 63))
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* = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
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* = base + (stride * vtx) + src_offset
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* = addr;
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*
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* QED.
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*/
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unsigned start = vertex_postfix->offset_start;
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for (unsigned i = 0; i < so->num_elements; ++i) {
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unsigned vbi = so->pipe[i].vertex_buffer_index;
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struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi];
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/* Adjust by the masked off bits of the offset. Make sure we
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* read src_offset from so->hw (which is not GPU visible)
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* rather than target (which is) due to caching effects */
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unsigned src_offset = so->pipe[i].src_offset;
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/* BOs aligned to 4k so guaranteed aligned to 64 */
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src_offset += (buf->buffer_offset & 63);
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/* Also, somewhat obscurely per-instance data needs to be
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* offset in response to a delayed start in an indexed draw */
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if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start)
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src_offset -= buf->stride * start;
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so->hw[i].src_offset = src_offset;
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}
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}
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/* Compute number of UBOs active (more specifically, compute the highest UBO
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* number addressable -- if there are gaps, include them in the count anyway).
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* We always include UBO #0 in the count, since we *need* uniforms enabled for
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@ -422,7 +367,6 @@ panfrost_draw_vbo(
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&primitive_size);
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panfrost_emit_shader_meta(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
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panfrost_emit_shader_meta(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
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panfrost_emit_vertex_attr_meta(batch, &vertex_postfix);
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panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
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panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix);
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panfrost_emit_texture_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix);
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@ -309,10 +309,6 @@ panfrost_invalidate_frame(struct panfrost_context *ctx);
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bool
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panfrost_writes_point_size(struct panfrost_context *ctx);
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void
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panfrost_vertex_state_upd_attr_offs(struct panfrost_context *ctx,
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struct mali_vertex_tiler_postfix *vertex_postfix);
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struct panfrost_transfer
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panfrost_vertex_tiler_job(struct panfrost_context *ctx, bool is_tiler);
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