gallium: Rename MUL_ZERO_WINS to LEGACY_MATH_RULES.
This is a clearer name for what it does than MUL_ZERO_WINS, and matches up to the new name in shader_info. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16176>
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@ -424,8 +424,8 @@ The integer capabilities:
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and a larger value would mean that multiple render targets are supported.
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and a larger value would mean that multiple render targets are supported.
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* ``PIPE_CAP_FBFETCH_COHERENT``: Whether framebuffer fetches from the fragment
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* ``PIPE_CAP_FBFETCH_COHERENT``: Whether framebuffer fetches from the fragment
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shader can be guaranteed to be coherent with framebuffer writes.
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shader can be guaranteed to be coherent with framebuffer writes.
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* ``PIPE_CAP_TGSI_MUL_ZERO_WINS``: Whether TGSI shaders support the
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* ``PIPE_CAP_TGSI_LEGACY_MATH_RULES``: Whether TGSI shaders support the
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``TGSI_PROPERTY_MUL_ZERO_WINS`` shader property.
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``TGSI_PROPERTY_LEGACY_MATH_RULES`` shader property.
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* ``PIPE_CAP_DOUBLES``: Whether double precision floating-point operations
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* ``PIPE_CAP_DOUBLES``: Whether double precision floating-point operations
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are supported.
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are supported.
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* ``PIPE_CAP_INT64``: Whether 64-bit integer operations are supported.
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* ``PIPE_CAP_INT64``: Whether 64-bit integer operations are supported.
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@ -3783,8 +3783,8 @@ Threads per block in each dimension, if known at compile time. If the block size
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is known all three should be at least 1. If it is unknown they should all be set
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is known all three should be at least 1. If it is unknown they should all be set
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to 0 or not set.
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to 0 or not set.
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MUL_ZERO_WINS
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LEGACY_MATH_RULES
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"""""""""""""
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"""""""""""""""""
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The MUL TGSI operation (FP32 multiplication) will return 0 if either
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The MUL TGSI operation (FP32 multiplication) will return 0 if either
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of the operands are equal to 0. That means that 0 * Inf = 0. This
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of the operands are equal to 0. That means that 0 * Inf = 0. This
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@ -160,7 +160,7 @@ const char *tgsi_property_names[TGSI_PROPERTY_COUNT] =
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"CS_FIXED_BLOCK_WIDTH",
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"CS_FIXED_BLOCK_WIDTH",
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"CS_FIXED_BLOCK_HEIGHT",
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"CS_FIXED_BLOCK_HEIGHT",
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"CS_FIXED_BLOCK_DEPTH",
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"CS_FIXED_BLOCK_DEPTH",
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"MUL_ZERO_WINS",
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"LEGACY_MATH_RULES",
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"VS_BLIT_SGPRS_AMD",
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"VS_BLIT_SGPRS_AMD",
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"CS_USER_DATA_COMPONENTS_AMD",
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"CS_USER_DATA_COMPONENTS_AMD",
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"LAYER_VIEWPORT_RELATIVE",
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"LAYER_VIEWPORT_RELATIVE",
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@ -307,7 +307,7 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
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case PIPE_CAP_FBFETCH:
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case PIPE_CAP_FBFETCH:
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case PIPE_CAP_FBFETCH_COHERENT:
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case PIPE_CAP_FBFETCH_COHERENT:
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case PIPE_CAP_BLEND_EQUATION_ADVANCED:
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case PIPE_CAP_BLEND_EQUATION_ADVANCED:
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case PIPE_CAP_TGSI_MUL_ZERO_WINS:
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case PIPE_CAP_TGSI_LEGACY_MATH_RULES:
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case PIPE_CAP_DOUBLES:
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case PIPE_CAP_DOUBLES:
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case PIPE_CAP_INT64:
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case PIPE_CAP_INT64:
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case PIPE_CAP_INT64_DIVMOD:
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case PIPE_CAP_INT64_DIVMOD:
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@ -218,7 +218,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_SHADER_CAN_READ_OUTPUTS:
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case PIPE_CAP_SHADER_CAN_READ_OUTPUTS:
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case PIPE_CAP_NATIVE_FENCE_FD:
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case PIPE_CAP_NATIVE_FENCE_FD:
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case PIPE_CAP_FBFETCH:
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case PIPE_CAP_FBFETCH:
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case PIPE_CAP_TGSI_MUL_ZERO_WINS:
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case PIPE_CAP_TGSI_LEGACY_MATH_RULES:
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case PIPE_CAP_DOUBLES:
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case PIPE_CAP_DOUBLES:
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case PIPE_CAP_INT64:
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case PIPE_CAP_INT64:
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case PIPE_CAP_INT64_DIVMOD:
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case PIPE_CAP_INT64_DIVMOD:
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@ -248,7 +248,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_STRING_MARKER:
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case PIPE_CAP_STRING_MARKER:
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case PIPE_CAP_CULL_DISTANCE:
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case PIPE_CAP_CULL_DISTANCE:
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case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
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case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
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case PIPE_CAP_TGSI_MUL_ZERO_WINS:
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case PIPE_CAP_TGSI_LEGACY_MATH_RULES:
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case PIPE_CAP_TGSI_TEX_TXF_LZ:
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case PIPE_CAP_TGSI_TEX_TXF_LZ:
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case PIPE_CAP_SHADER_CLOCK:
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case PIPE_CAP_SHADER_CLOCK:
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case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
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case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
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@ -288,7 +288,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_SHADER_GROUP_VOTE:
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case PIPE_CAP_SHADER_GROUP_VOTE:
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case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
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case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
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case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
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case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
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case PIPE_CAP_TGSI_MUL_ZERO_WINS:
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case PIPE_CAP_TGSI_LEGACY_MATH_RULES:
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case PIPE_CAP_DOUBLES:
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case PIPE_CAP_DOUBLES:
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case PIPE_CAP_INT64:
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case PIPE_CAP_INT64:
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case PIPE_CAP_TGSI_TEX_TXF_LZ:
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case PIPE_CAP_TGSI_TEX_TXF_LZ:
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@ -312,7 +312,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
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case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
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case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
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case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
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case PIPE_CAP_CLEAR_TEXTURE:
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case PIPE_CAP_CLEAR_TEXTURE:
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case PIPE_CAP_TGSI_MUL_ZERO_WINS:
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case PIPE_CAP_TGSI_LEGACY_MATH_RULES:
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case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
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case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
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case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
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case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
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case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
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case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
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@ -4721,7 +4721,7 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
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unsigned op = ctx->inst_info->op;
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unsigned op = ctx->inst_info->op;
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if (op == ALU_OP2_MUL_IEEE &&
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if (op == ALU_OP2_MUL_IEEE &&
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ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
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ctx->info.properties[TGSI_PROPERTY_LEGACY_MATH_RULES])
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op = ALU_OP2_MUL;
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op = ALU_OP2_MUL;
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/* nir_to_tgsi lowers nir_op_isub to UADD + negate, since r600 doesn't support
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/* nir_to_tgsi lowers nir_op_isub to UADD + negate, since r600 doesn't support
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@ -7305,7 +7305,7 @@ static int tgsi_op3_dst(struct r600_shader_ctx *ctx, int dst)
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unsigned op = ctx->inst_info->op;
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unsigned op = ctx->inst_info->op;
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if (op == ALU_OP3_MULADD_IEEE &&
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if (op == ALU_OP3_MULADD_IEEE &&
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ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
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ctx->info.properties[TGSI_PROPERTY_LEGACY_MATH_RULES])
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op = ALU_OP3_MULADD;
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op = ALU_OP3_MULADD;
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for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
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for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
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@ -7355,7 +7355,7 @@ static int tgsi_dp(struct r600_shader_ctx *ctx)
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int i, j, r;
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int i, j, r;
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unsigned op = ctx->inst_info->op;
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unsigned op = ctx->inst_info->op;
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if (op == ALU_OP2_DOT4_IEEE &&
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if (op == ALU_OP2_DOT4_IEEE &&
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ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
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ctx->info.properties[TGSI_PROPERTY_LEGACY_MATH_RULES])
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op = ALU_OP2_DOT4;
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op = ALU_OP2_DOT4;
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for (i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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@ -3666,9 +3666,9 @@ tx_ctor(struct shader_translator *tx, struct pipe_screen *screen, struct nine_sh
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ureg_property(tx->ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
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ureg_property(tx->ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
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}
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}
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tx->mul_zero_wins = GET_CAP(TGSI_MUL_ZERO_WINS);
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tx->mul_zero_wins = GET_CAP(TGSI_LEGACY_MATH_RULES);
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if (tx->mul_zero_wins)
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if (tx->mul_zero_wins)
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ureg_property(tx->ureg, TGSI_PROPERTY_MUL_ZERO_WINS, 1);
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ureg_property(tx->ureg, TGSI_PROPERTY_LEGACY_MATH_RULES, 1);
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/* Add additional definition of constants */
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/* Add additional definition of constants */
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if (info->add_constants_defs.c_combination) {
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if (info->add_constants_defs.c_combination) {
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@ -3894,7 +3894,7 @@ nine_ureg_create_shader(struct ureg_program *ureg,
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enum pipe_shader_type shader_type = ((struct tgsi_processor *) &tgsi_tokens[1])->Processor;
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enum pipe_shader_type shader_type = ((struct tgsi_processor *) &tgsi_tokens[1])->Processor;
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/* NIR doesn't have mul_zero_wins */
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/* NIR doesn't have mul_zero_wins */
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bool ttn_supported = !GET_CAP(TGSI_MUL_ZERO_WINS);
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bool ttn_supported = !GET_CAP(TGSI_LEGACY_MATH_RULES);
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int preferred_ir = screen->get_shader_param(screen, shader_type, PIPE_SHADER_CAP_PREFERRED_IR);
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int preferred_ir = screen->get_shader_param(screen, shader_type, PIPE_SHADER_CAP_PREFERRED_IR);
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int supported_irs = screen->get_shader_param(screen, shader_type, PIPE_SHADER_CAP_SUPPORTED_IRS);
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int supported_irs = screen->get_shader_param(screen, shader_type, PIPE_SHADER_CAP_SUPPORTED_IRS);
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bool prefer_nir = (preferred_ir == PIPE_SHADER_IR_NIR);
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bool prefer_nir = (preferred_ir == PIPE_SHADER_IR_NIR);
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@ -891,7 +891,7 @@ enum pipe_cap
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PIPE_CAP_NATIVE_FENCE_FD,
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PIPE_CAP_NATIVE_FENCE_FD,
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PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS,
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PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS,
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PIPE_CAP_FBFETCH,
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PIPE_CAP_FBFETCH,
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PIPE_CAP_TGSI_MUL_ZERO_WINS,
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PIPE_CAP_TGSI_LEGACY_MATH_RULES,
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PIPE_CAP_DOUBLES,
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PIPE_CAP_DOUBLES,
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PIPE_CAP_INT64,
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PIPE_CAP_INT64,
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PIPE_CAP_INT64_DIVMOD,
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PIPE_CAP_INT64_DIVMOD,
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@ -298,7 +298,7 @@ enum tgsi_property_name {
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TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
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TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
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TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
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TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
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TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
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TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
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TGSI_PROPERTY_MUL_ZERO_WINS,
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TGSI_PROPERTY_LEGACY_MATH_RULES,
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TGSI_PROPERTY_VS_BLIT_SGPRS_AMD,
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TGSI_PROPERTY_VS_BLIT_SGPRS_AMD,
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TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD,
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TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD,
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TGSI_PROPERTY_LAYER_VIEWPORT_RELATIVE,
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TGSI_PROPERTY_LAYER_VIEWPORT_RELATIVE,
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@ -1233,7 +1233,7 @@ void Source::scanProperty(const struct tgsi_full_property *prop)
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case TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE:
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case TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE:
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info_out->prop.fp.postDepthCoverage = prop->u[0].Data;
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info_out->prop.fp.postDepthCoverage = prop->u[0].Data;
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break;
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break;
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case TGSI_PROPERTY_MUL_ZERO_WINS:
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case TGSI_PROPERTY_LEGACY_MATH_RULES:
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info->io.mul_zero_wins = prop->u[0].Data;
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info->io.mul_zero_wins = prop->u[0].Data;
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break;
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break;
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case TGSI_PROPERTY_LAYER_VIEWPORT_RELATIVE:
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case TGSI_PROPERTY_LAYER_VIEWPORT_RELATIVE:
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