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Implement x86_64 atomics for compilers w/o intrinsics. 

Really old gcc's (3.3, at least) don't have support for the
intrinsics we need.  This implements a fallback for that case.
This commit is contained in:
Tom Fogal 2010-09-26 18:57:59 -06:00
parent 0c86e1f294
commit 76a60faf52
1 changed files with 47 additions and 0 deletions
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47
src/gallium/auxiliary/util/u_atomic.h
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@ -29,6 +29,8 @@
#define PIPE_ATOMIC_ASM_MSVC_X86
#elif (defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86))
#define PIPE_ATOMIC_ASM_GCC_X86
#elif (defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64))
#define PIPE_ATOMIC_ASM_GCC_X86_64
#elif defined(PIPE_CC_GCC) && (PIPE_CC_GCC_VERSION >= 401)
#define PIPE_ATOMIC_GCC_INTRINSIC
#else
@ -36,6 +38,51 @@
#endif
#if defined(PIPE_ATOMIC_ASM_GCC_X86_64)
#define PIPE_ATOMIC "GCC x86_64 assembly"
#ifdef __cplusplus
extern "C" {
#endif
#define p_atomic_set(_v, _i) (*(_v) = (_i))
#define p_atomic_read(_v) (*(_v))
static INLINE boolean
p_atomic_dec_zero(int32_t *v)
{
unsigned char c;
__asm__ __volatile__("lock; decl %0; sete %1":"+m"(*v), "=qm"(c)
::"memory");
return c != 0;
}
static INLINE void
p_atomic_inc(int32_t *v)
{
__asm__ __volatile__("lock; incl %0":"+m"(*v));
}
static INLINE void
p_atomic_dec(int32_t *v)
{
__asm__ __volatile__("lock; decl %0":"+m"(*v));
}
static INLINE int32_t
p_atomic_cmpxchg(int32_t *v, int32_t old, int32_t _new)
{
return __sync_val_compare_and_swap(v, old, _new);
}
#ifdef __cplusplus
}
#endif
#endif /* PIPE_ATOMIC_ASM_GCC_X86_64 */
#if defined(PIPE_ATOMIC_ASM_GCC_X86)