broadcom/compiler: add lowering pass to scalarize non 32-bit general load/store
V3D hardware doesn't support vector access for general TMU load/store operations like the ones we use for UBO and SSBO, so we need to split these to scalar operations. It should be noted that we also have a vectorization pass (which runs later, during optimization), that may reconstruct some of these into 32-bit operations when possible (i.e. when the resulting operation is 32-bit aligned). Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
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@ -39,6 +39,7 @@ libbroadcom_compiler_files = files(
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'v3d_nir_lower_io.c',
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'v3d_nir_lower_image_load_store.c',
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'v3d_nir_lower_line_smooth.c',
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'v3d_nir_lower_load_store_bitsize.c',
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'v3d_nir_lower_logic_ops.c',
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'v3d_nir_lower_robust_buffer_access.c',
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'v3d_nir_lower_scratch.c',
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@ -1109,6 +1109,7 @@ void v3d_nir_lower_robust_buffer_access(nir_shader *shader, struct v3d_compile *
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void v3d_nir_lower_scratch(nir_shader *s);
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void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
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void v3d_nir_lower_image_load_store(nir_shader *s);
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void v3d_nir_lower_load_store_bitsize(nir_shader *s, struct v3d_compile *c);
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void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
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void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
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@ -0,0 +1,251 @@
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/*
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* Copyright © 2021 Raspberry Pi
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "compiler/v3d_compiler.h"
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#include "compiler/nir/nir_builder.h"
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/**
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* The V3D TMU unit can only do 32-bit general vector access so for anything
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* else we need to split vector load/store instructions to scalar.
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*
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* Note that a vectorization pass after this lowering may be able to
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* re-vectorize some of these using 32-bit load/store instructions instead,
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* which we do support.
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*/
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static int
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value_src(nir_intrinsic_op intrinsic)
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{
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switch (intrinsic) {
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case nir_intrinsic_store_ssbo:
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case nir_intrinsic_store_scratch:
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return 0;
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default:
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unreachable("Unsupported intrinsic");
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}
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}
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static int
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offset_src(nir_intrinsic_op intrinsic)
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{
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switch (intrinsic) {
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case nir_intrinsic_load_uniform:
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case nir_intrinsic_load_shared:
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case nir_intrinsic_load_scratch:
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return 0;
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case nir_intrinsic_load_ubo:
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case nir_intrinsic_load_ssbo:
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case nir_intrinsic_store_scratch:
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return 1;
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case nir_intrinsic_store_ssbo:
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return 2;
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default:
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unreachable("Unsupported intrinsic");
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}
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}
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static nir_intrinsic_instr *
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init_scalar_intrinsic(nir_builder *b,
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nir_intrinsic_instr *intr,
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uint32_t component,
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nir_ssa_def *offset,
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uint32_t bit_size,
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nir_ssa_def **scalar_offset)
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{
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nir_intrinsic_instr *new_intr =
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nir_intrinsic_instr_create(b->shader, intr->intrinsic);
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nir_intrinsic_copy_const_indices(new_intr, intr);
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const int offset_units = bit_size / 8;
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assert(offset_units >= 1);
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if (nir_intrinsic_has_align_mul(intr)) {
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assert(nir_intrinsic_has_align_offset(intr));
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unsigned align_mul = nir_intrinsic_align_mul(intr);
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unsigned align_off = nir_intrinsic_align_offset(intr);
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align_off += offset_units * component;
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align_off = align_off % align_mul;
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nir_intrinsic_set_align(new_intr, align_mul, align_off);
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}
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*scalar_offset = offset;
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unsigned offset_adj = offset_units * component;
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if (nir_intrinsic_has_base(intr)) {
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nir_intrinsic_set_base(
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new_intr, nir_intrinsic_base(intr) + offset_adj);
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} else {
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*scalar_offset =
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nir_iadd(b, offset,
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nir_imm_intN_t(b, offset_adj,
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offset->bit_size));
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}
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new_intr->num_components = 1;
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return new_intr;
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}
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static bool
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lower_load_bitsize(struct v3d_compile *c,
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nir_builder *b,
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nir_intrinsic_instr *intr)
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{
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uint32_t bit_size = nir_dest_bit_size(intr->dest);
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if (bit_size == 32)
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return false;
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/* No need to split if it is already scalar */
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int num_comp = nir_intrinsic_dest_components(intr);
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if (num_comp <= 1)
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return false;
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b->cursor = nir_before_instr(&intr->instr);
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unsigned offset_idx = offset_src(intr->intrinsic);
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nir_ssa_def *offset = nir_ssa_for_src(b, intr->src[offset_idx], 1);
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/* Split vector store to multiple scalar loads */
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nir_ssa_def *dest_components[4] = { NULL };
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const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
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for (int component = 0; component < num_comp; component++) {
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nir_ssa_def *scalar_offset;
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nir_intrinsic_instr *new_intr =
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init_scalar_intrinsic(b, intr, component, offset,
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bit_size, &scalar_offset);
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for (unsigned i = 0; i < info->num_srcs; i++) {
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if (i == offset_idx) {
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new_intr->src[i] = nir_src_for_ssa(scalar_offset);
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} else {
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new_intr->src[i] = intr->src[i];
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}
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}
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nir_ssa_dest_init(&new_intr->instr, &new_intr->dest,
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1, bit_size, NULL);
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dest_components[component] = &new_intr->dest.ssa;
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nir_builder_instr_insert(b, &new_intr->instr);
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}
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nir_ssa_def *new_dst = nir_vec(b, dest_components, num_comp);
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nir_ssa_def_rewrite_uses(&intr->dest.ssa, new_dst);
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nir_instr_remove(&intr->instr);
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return true;
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}
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static bool
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lower_store_bitsize(struct v3d_compile *c,
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nir_builder *b,
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nir_intrinsic_instr *intr)
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{
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/* No need to split if it is already scalar */
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int value_idx = value_src(intr->intrinsic);
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int num_comp = nir_intrinsic_src_components(intr, value_idx);
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if (num_comp <= 1)
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return false;
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/* No need to split if it is 32-bit */
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if (nir_src_bit_size(intr->src[value_idx]) == 32)
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return false;
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nir_ssa_def *value = nir_ssa_for_src(b, intr->src[value_idx], num_comp);
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b->cursor = nir_before_instr(&intr->instr);
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unsigned offset_idx = offset_src(intr->intrinsic);
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nir_ssa_def *offset = nir_ssa_for_src(b, intr->src[offset_idx], 1);
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/* Split vector store to multiple scalar stores */
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const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
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unsigned wrmask = nir_intrinsic_write_mask(intr);
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while (wrmask) {
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unsigned component = ffs(wrmask) - 1;
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nir_ssa_def *scalar_offset;
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nir_intrinsic_instr *new_intr =
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init_scalar_intrinsic(b, intr, component, offset,
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value->bit_size, &scalar_offset);
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nir_intrinsic_set_write_mask(new_intr, 0x1);
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for (unsigned i = 0; i < info->num_srcs; i++) {
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if (i == value_idx) {
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nir_ssa_def *scalar_value =
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nir_channels(b, value, 1 << component);
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new_intr->src[i] = nir_src_for_ssa(scalar_value);
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} else if (i == offset_idx) {
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new_intr->src[i] = nir_src_for_ssa(scalar_offset);
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} else {
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new_intr->src[i] = intr->src[i];
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}
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}
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nir_builder_instr_insert(b, &new_intr->instr);
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wrmask &= ~(1 << component);
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}
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nir_instr_remove(&intr->instr);
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return true;
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}
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static bool
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lower_load_store_bitsize(nir_builder *b, nir_instr *instr, void *data)
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{
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struct v3d_compile *c = (struct v3d_compile *) data;
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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switch (intr->intrinsic) {
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case nir_intrinsic_load_ssbo:
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case nir_intrinsic_load_ubo:
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case nir_intrinsic_load_uniform:
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case nir_intrinsic_load_scratch:
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return lower_load_bitsize(c, b, intr);
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case nir_intrinsic_store_ssbo:
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case nir_intrinsic_store_scratch:
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return lower_store_bitsize(c, b, intr);
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default:
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return false;
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}
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}
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void
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v3d_nir_lower_load_store_bitsize(nir_shader *s, struct v3d_compile *c)
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{
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nir_shader_instructions_pass(s,
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lower_load_store_bitsize,
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nir_metadata_block_index |
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nir_metadata_dominance,
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c);
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}
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@ -1510,6 +1510,8 @@ v3d_attempt_compile(struct v3d_compile *c)
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NIR_PASS_V(c->s, nir_lower_wrmasks, should_split_wrmask, c->s);
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NIR_PASS_V(c->s, v3d_nir_lower_load_store_bitsize, c);
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NIR_PASS_V(c->s, v3d_nir_lower_subgroup_intrinsics, c);
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v3d_optimize_nir(c, c->s);
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