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intel/compiler: Add support to handle 64-bit atomics with A32 messages 

v1: (Jason)
- Fix parentheses

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12566>
This commit is contained in:
Sagar Ghuge 2021-08-30 18:59:51 -07:00 committed by Marge Bot
parent 9ffd05b41e
commit 75e28b8777
2 changed files with 8 additions and 5 deletions
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10
src/intel/compiler/brw_fs.cpp
View File

@ -6004,7 +6004,8 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst)
/* Calculate the total number of components of the payload. */
const unsigned addr_sz = inst->components_read(SURFACE_LOGICAL_SRC_ADDRESS);
const unsigned src_sz = inst->components_read(SURFACE_LOGICAL_SRC_DATA);
const unsigned src_comps = inst->components_read(SURFACE_LOGICAL_SRC_DATA);
const unsigned src_sz = type_sz(src.type);
const bool has_side_effects = inst->has_side_effects();
@ -6012,8 +6013,8 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst)
fs_reg payload, payload2;
payload = bld.move_to_vgrf(addr, addr_sz);
if (src.file != BAD_FILE) {
payload2 = bld.move_to_vgrf(src, src_sz);
ex_mlen = src_sz * (inst->exec_size / 8);
payload2 = bld.move_to_vgrf(src, src_comps);
ex_mlen = (src_comps * src_sz * inst->exec_size) / REG_SIZE;
}
/* Predicate the instruction on the sample mask if needed */
@ -6071,7 +6072,8 @@ lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst)
inst->desc = lsc_msg_desc(devinfo, opcode, inst->exec_size,
surf_type, LSC_ADDR_SIZE_A32,
1 /* num_coordinates */,
LSC_DATA_SIZE_D32, 1 /* num_channels */,
lsc_bits_to_data_size(src_sz * 8),
1 /* num_channels */,
false /* transpose */,
LSC_CACHE_STORE_L1UC_L3WB,
!inst->dst.is_null());

3
src/intel/compiler/brw_fs_nir.cpp
View File

@ -5750,7 +5750,8 @@ fs_visitor::nir_emit_ssbo_atomic(const fs_builder &bld,
* appear to exist. However, if you look at Vol 2a, there are no message
* descriptors provided for Qword atomic ops except for A64 messages.
*/
assert(nir_dest_bit_size(instr->dest) == 32);
assert(nir_dest_bit_size(instr->dest) == 32 ||
(nir_dest_bit_size(instr->dest) == 64 && devinfo->has_lsc));
fs_reg dest;
if (nir_intrinsic_infos[instr->intrinsic].has_dest)