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radeonsi: align command buffer starting address to fix some Raven hangs 

Cc: 17.3 18.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák 2018-03-06 19:07:58 -05:00
parent 5b68a7297d
commit 75c5d25f0f
5 changed files with 28 additions and 5 deletions
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21
src/amd/common/ac_gpu_info.c
View File

@ -98,7 +98,9 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
{
struct amdgpu_buffer_size_alignments alignment_info = {};
struct amdgpu_heap_info vram, vram_vis, gtt;
struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_enc = {};
struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
int r, i, j;
drmDevicePtr devinfo;
@ -154,6 +156,12 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
return false;
}
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
return false;
}
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
@ -340,6 +348,17 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
if (info->chip_class == SI)
info->gfx_ib_pad_with_type2 = TRUE;
unsigned ib_align = 0;
ib_align = MAX2(ib_align, gfx.ib_start_alignment);
ib_align = MAX2(ib_align, compute.ib_start_alignment);
ib_align = MAX2(ib_align, dma.ib_start_alignment);
ib_align = MAX2(ib_align, uvd.ib_start_alignment);
ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
ib_align = MAX2(ib_align, vce.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
info->ib_start_alignment = ib_align;
return true;
}

1
src/amd/common/ac_gpu_info.h
View File

@ -62,6 +62,7 @@ struct radeon_info {
bool has_virtual_memory;
bool gfx_ib_pad_with_type2;
bool has_hw_decode;
unsigned ib_start_alignment;
uint32_t num_sdma_rings;
uint32_t num_compute_rings;
uint32_t uvd_fw_version;

5
src/gallium/drivers/radeonsi/si_pm4.c
View File

@ -167,8 +167,9 @@ void si_pm4_upload_indirect_buffer(struct si_context *sctx,
r600_resource_reference(&state->indirect_buffer, NULL);
state->indirect_buffer = (struct r600_resource*)
pipe_buffer_create(screen, 0,
PIPE_USAGE_DEFAULT, aligned_ndw * 4);
si_aligned_buffer_create(screen, 0,
PIPE_USAGE_DEFAULT, aligned_ndw * 4,
sctx->screen->info.ib_start_alignment);
if (!state->indirect_buffer)
return;

5
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
View File

@ -800,10 +800,11 @@ static void amdgpu_set_ib_size(struct amdgpu_ib *ib)
}
}
static void amdgpu_ib_finalize(struct amdgpu_ib *ib)
static void amdgpu_ib_finalize(struct amdgpu_winsys *ws, struct amdgpu_ib *ib)
{
amdgpu_set_ib_size(ib);
ib->used_ib_space += ib->base.current.cdw * 4;
ib->used_ib_space = align(ib->used_ib_space, ws->info.ib_start_alignment);
ib->max_ib_size = MAX2(ib->max_ib_size, ib->base.prev_dw + ib->base.current.cdw);
}
@ -1561,7 +1562,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
struct amdgpu_cs_context *cur = cs->csc;
/* Set IB sizes. */
amdgpu_ib_finalize(&cs->main);
amdgpu_ib_finalize(ws, &cs->main);
/* Create a fence. */
amdgpu_fence_reference(&cur->fence, NULL);

1
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View File

@ -527,6 +527,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
(ws->info.family == CHIP_HAWAII &&
ws->accel_working2 < 3);
ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
ws->info.ib_start_alignment = 4096;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;