anv: support blending logic op dynamic state
Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10366>
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@ -104,6 +104,7 @@ const struct anv_dynamic_state default_dynamic_state = {
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.raster_discard = 0,
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.depth_bias_enable = 0,
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.primitive_restart_enable = 0,
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.logic_op = 0,
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};
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/**
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@ -195,6 +196,7 @@ anv_dynamic_state_copy(struct anv_dynamic_state *dest,
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ANV_CMP_COPY(raster_discard, ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE);
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ANV_CMP_COPY(depth_bias_enable, ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS_ENABLE);
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ANV_CMP_COPY(primitive_restart_enable, ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE);
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ANV_CMP_COPY(logic_op, ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP);
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if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS) {
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dest->sample_locations.samples = src->sample_locations.samples;
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@ -544,6 +546,17 @@ void anv_CmdSetPrimitiveRestartEnableEXT(
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE;
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}
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void anv_CmdSetLogicOpEXT(
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VkCommandBuffer commandBuffer,
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VkLogicOp logicOp)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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cmd_buffer->state.gfx.dynamic.logic_op = logicOp;
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP;
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}
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void anv_CmdSetViewport(
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VkCommandBuffer commandBuffer,
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uint32_t firstViewport,
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@ -2182,7 +2182,8 @@ copy_non_dynamic_state(struct anv_graphics_pipeline *pipeline,
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(ANV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS |
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ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
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ANV_CMD_DIRTY_DYNAMIC_SHADING_RATE |
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ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE);
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ANV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP);
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}
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static void
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@ -2679,6 +2679,7 @@ struct anv_dynamic_state {
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bool raster_discard;
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bool depth_bias_enable;
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bool primitive_restart_enable;
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VkLogicOp logic_op;
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bool dyn_vbo_stride;
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bool dyn_vbo_size;
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@ -1217,7 +1217,8 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
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GENX(BLEND_STATE_ENTRY_length) * surface_count;
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uint32_t *blend_state_start, *state_pos;
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if (dynamic_states & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE) {
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if (dynamic_states & (ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
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ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
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const struct intel_device_info *devinfo = &pipeline->base.device->info;
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blend_state_start = devinfo->ver >= 8 ?
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pipeline->gfx8.blend_state : pipeline->gfx7.blend_state;
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@ -1263,7 +1264,9 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
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.AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
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#endif
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.LogicOpEnable = info->logicOpEnable,
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.LogicOpFunction = genX(vk_to_intel_logic_op)[info->logicOp],
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.LogicOpFunction = dynamic_states & ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP ?
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0: genX(vk_to_intel_logic_op)[info->logicOp],
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/* Vulkan specification 1.2.168, VkLogicOp:
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*
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* "Logical operations are controlled by the logicOpEnable and
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@ -1370,7 +1373,8 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
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blend.AlphaTestEnable = false;
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blend.IndependentAlphaBlendEnable = blend_state.IndependentAlphaBlendEnable;
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if (dynamic_states & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE) {
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if (dynamic_states & (ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
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ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
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GENX(3DSTATE_PS_BLEND_pack)(NULL, pipeline->gfx8.ps_blend, &blend);
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} else {
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anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS_BLEND), _blend)
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@ -1382,7 +1386,8 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
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GENX(BLEND_STATE_pack)(NULL, blend_state_start, &blend_state);
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if (!(dynamic_states & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE)) {
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if (!(dynamic_states & (ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
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ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP))) {
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anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
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bsp.BlendStatePointer = pipeline->blend_state.offset;
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#if GFX_VER >= 8
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@ -356,21 +356,27 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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cmd_buffer->state.gfx.dynamic.sample_locations.locations);
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}
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE) {
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE ||
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cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP) {
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const uint8_t color_writes = cmd_buffer->state.gfx.dynamic.color_writes;
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/* 3DSTATE_WM in the hope we can avoid spawning fragment shaders
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* threads.
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*/
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uint32_t dwords[GENX(3DSTATE_WM_length)];
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struct GENX(3DSTATE_WM) wm = {
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GENX(3DSTATE_WM_header),
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bool dirty_color_blend =
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cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE;
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.ThreadDispatchEnable = pipeline->force_fragment_thread_dispatch ||
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color_writes,
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};
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GENX(3DSTATE_WM_pack)(NULL, dwords, &wm);
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if (dirty_color_blend) {
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uint32_t dwords[GENX(3DSTATE_WM_length)];
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struct GENX(3DSTATE_WM) wm = {
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GENX(3DSTATE_WM_header),
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anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx7.wm);
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.ThreadDispatchEnable = pipeline->force_fragment_thread_dispatch ||
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color_writes,
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};
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GENX(3DSTATE_WM_pack)(NULL, dwords, &wm);
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anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx7.wm);
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}
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/* Blend states of each RT */
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uint32_t surface_count = 0;
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@ -388,14 +394,20 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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/* Skip this part */
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dws += GENX(BLEND_STATE_length);
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bool dirty_logic_op =
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cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP;
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for (uint32_t i = 0; i < surface_count; i++) {
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struct anv_pipeline_binding *binding = &map->surface_to_descriptor[i];
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bool write_disabled = (color_writes & (1u << binding->index)) == 0;
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bool write_disabled =
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dirty_color_blend && (color_writes & (1u << binding->index)) == 0;
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struct GENX(BLEND_STATE_ENTRY) entry = {
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.WriteDisableAlpha = write_disabled,
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.WriteDisableRed = write_disabled,
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.WriteDisableGreen = write_disabled,
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.WriteDisableBlue = write_disabled,
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.LogicOpFunction =
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dirty_logic_op ? genX(vk_to_intel_logic_op)[d->logic_op] : 0,
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};
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GENX(BLEND_STATE_ENTRY_pack)(NULL, dws, &entry);
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dws += GENX(BLEND_STATE_ENTRY_length);
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@ -659,32 +659,38 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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cmd_buffer->state.gfx.dynamic.sample_locations.locations);
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}
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE) {
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE ||
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cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP) {
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const uint8_t color_writes = cmd_buffer->state.gfx.dynamic.color_writes;
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/* 3DSTATE_WM in the hope we can avoid spawning fragment shaders
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* threads.
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*/
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uint32_t dwords[MAX2(GENX(3DSTATE_WM_length),
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GENX(3DSTATE_PS_BLEND_length))];
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struct GENX(3DSTATE_WM) wm = {
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GENX(3DSTATE_WM_header),
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bool dirty_color_blend =
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cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE;
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.ForceThreadDispatchEnable = (pipeline->force_fragment_thread_dispatch ||
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!color_writes) ? ForceON : 0,
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};
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GENX(3DSTATE_WM_pack)(NULL, dwords, &wm);
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if (dirty_color_blend) {
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uint32_t dwords[MAX2(GENX(3DSTATE_WM_length),
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GENX(3DSTATE_PS_BLEND_length))];
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struct GENX(3DSTATE_WM) wm = {
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GENX(3DSTATE_WM_header),
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anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx8.wm);
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.ForceThreadDispatchEnable = (pipeline->force_fragment_thread_dispatch ||
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!color_writes) ? ForceON : 0,
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};
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GENX(3DSTATE_WM_pack)(NULL, dwords, &wm);
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/* 3DSTATE_PS_BLEND to be consistent with the rest of the
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* BLEND_STATE_ENTRY.
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*/
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struct GENX(3DSTATE_PS_BLEND) ps_blend = {
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GENX(3DSTATE_PS_BLEND_header),
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.HasWriteableRT = color_writes != 0,
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};
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GENX(3DSTATE_PS_BLEND_pack)(NULL, dwords, &ps_blend);
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anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx8.ps_blend);
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anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx8.wm);
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/* 3DSTATE_PS_BLEND to be consistent with the rest of the
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* BLEND_STATE_ENTRY.
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*/
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struct GENX(3DSTATE_PS_BLEND) ps_blend = {
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GENX(3DSTATE_PS_BLEND_header),
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.HasWriteableRT = color_writes != 0,
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};
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GENX(3DSTATE_PS_BLEND_pack)(NULL, dwords, &ps_blend);
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anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx8.ps_blend);
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}
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/* Blend states of each RT */
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uint32_t surface_count = 0;
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@ -702,14 +708,20 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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/* Skip this part */
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dws += GENX(BLEND_STATE_length);
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bool dirty_logic_op =
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cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP;
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for (uint32_t i = 0; i < surface_count; i++) {
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struct anv_pipeline_binding *binding = &map->surface_to_descriptor[i];
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bool write_disabled = (color_writes & (1u << binding->index)) == 0;
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bool write_disabled =
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dirty_color_blend && (color_writes & (1u << binding->index)) == 0;
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struct GENX(BLEND_STATE_ENTRY) entry = {
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.WriteDisableAlpha = write_disabled,
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.WriteDisableRed = write_disabled,
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.WriteDisableGreen = write_disabled,
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.WriteDisableBlue = write_disabled,
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.LogicOpFunction =
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dirty_logic_op ? genX(vk_to_intel_logic_op)[d->logic_op] : 0,
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};
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GENX(BLEND_STATE_ENTRY_pack)(NULL, dws, &entry);
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dws += GENX(BLEND_STATE_ENTRY_length);
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