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i965/fs: Use the nir info instead of pulling things out of [shader_]prog 

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jason Ekstrand 2015-10-01 15:12:59 -07:00
parent b62e36d18f
commit 756613ed35
3 changed files with 19 additions and 20 deletions
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29
src/mesa/drivers/dri/i965/brw_fs.cpp
View File

@ -1401,7 +1401,7 @@ fs_visitor::calculate_urb_setup()
int urb_next = 0;
/* Figure out where each of the incoming setup attributes lands. */
if (devinfo->gen >= 6) {
if (_mesa_bitcount_64(prog->InputsRead &
if (_mesa_bitcount_64(nir->info.inputs_read &
BRW_FS_VARYING_INPUT_MASK) <= 16) {
/* The SF/SBE pipeline stage can do arbitrary rearrangement of the
* first 16 varying inputs, so we can put them wherever we want.
@ -1413,7 +1413,7 @@ fs_visitor::calculate_urb_setup()
* a different vertex (or geometry) shader.
*/
for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) {
if (prog->InputsRead & BRW_FS_VARYING_INPUT_MASK &
if (nir->info.inputs_read & BRW_FS_VARYING_INPUT_MASK &
BITFIELD64_BIT(i)) {
prog_data->urb_setup[i] = urb_next++;
}
@ -1427,7 +1427,7 @@ fs_visitor::calculate_urb_setup()
struct brw_vue_map prev_stage_vue_map;
brw_compute_vue_map(devinfo, &prev_stage_vue_map,
key->input_slots_valid,
shader_prog->SeparateShader);
nir->info.separate_shader);
int first_slot = 2 * BRW_SF_URB_ENTRY_READ_OFFSET;
assert(prev_stage_vue_map.num_slots <= first_slot + 32);
for (int slot = first_slot; slot < prev_stage_vue_map.num_slots;
@ -1437,7 +1437,7 @@ fs_visitor::calculate_urb_setup()
* unused.
*/
if (varying != BRW_VARYING_SLOT_COUNT &&
(prog->InputsRead & BRW_FS_VARYING_INPUT_MASK &
(nir->info.inputs_read & BRW_FS_VARYING_INPUT_MASK &
BITFIELD64_BIT(varying))) {
prog_data->urb_setup[varying] = slot - first_slot;
}
@ -1470,7 +1470,7 @@ fs_visitor::calculate_urb_setup()
*
* See compile_sf_prog() for more info.
*/
if (prog->InputsRead & BITFIELD64_BIT(VARYING_SLOT_PNTC))
if (nir->info.inputs_read & BITFIELD64_BIT(VARYING_SLOT_PNTC))
prog_data->urb_setup[VARYING_SLOT_PNTC] = urb_next++;
}
@ -4634,7 +4634,7 @@ void
fs_visitor::setup_payload_gen6()
{
bool uses_depth =
(prog->InputsRead & (1 << VARYING_SLOT_POS)) != 0;
(nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
unsigned barycentric_interp_modes =
(stage == MESA_SHADER_FRAGMENT) ?
((brw_wm_prog_data*) this->prog_data)->barycentric_interp_modes : 0;
@ -4693,7 +4693,7 @@ fs_visitor::setup_payload_gen6()
}
/* R32: MSAA input coverage mask */
if (prog->SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
if (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) {
assert(devinfo->gen >= 7);
payload.sample_mask_in_reg = payload.num_regs;
payload.num_regs++;
@ -4706,7 +4706,7 @@ fs_visitor::setup_payload_gen6()
/* R34-: bary for 32-pixel. */
/* R58-59: interp W for 32-pixel. */
if (prog->OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
source_depth_to_render_target = true;
}
}
@ -4725,7 +4725,7 @@ fs_visitor::setup_cs_payload()
payload.num_regs = 1;
if (prog->SystemValuesRead & SYSTEM_BIT_LOCAL_INVOCATION_ID) {
if (nir->info.system_values_read & SYSTEM_BIT_LOCAL_INVOCATION_ID) {
const unsigned local_id_dwords =
brw_cs_prog_local_id_payload_dwords(dispatch_width);
assert((local_id_dwords & 0x7) == 0);
@ -4786,8 +4786,8 @@ fs_visitor::optimize()
\
if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
char filename[64]; \
snprintf(filename, 64, "%s%d-%04d-%02d-%02d-" #pass, \
stage_abbrev, dispatch_width, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
\
backend_shader::dump_instructions(filename); \
} \
@ -4800,9 +4800,8 @@ fs_visitor::optimize()
if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER)) {
char filename[64];
snprintf(filename, 64, "%s%d-%04d-00-start",
stage_abbrev, dispatch_width,
shader_prog ? shader_prog->Name : 0);
snprintf(filename, 64, "%s%d-%s-00-start",
stage_abbrev, dispatch_width, nir->info.name);
backend_shader::dump_instructions(filename);
}
@ -5003,7 +5002,7 @@ fs_visitor::run_fs(bool do_rep_send)
emit_shader_time_begin();
calculate_urb_setup();
if (prog->InputsRead > 0) {
if (nir->info.inputs_read > 0) {
if (devinfo->gen < 6)
emit_interpolation_setup_gen4();
else

8
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
View File

@ -1440,7 +1440,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
*/
brw_mark_surface_used(prog_data,
stage_prog_data->binding_table.ubo_start +
shader_prog->NumBufferInterfaceBlocks - 1);
nir->info.num_ssbos - 1);
}
if (has_indirect) {
@ -1503,7 +1503,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
*/
brw_mark_surface_used(prog_data,
stage_prog_data->binding_table.ubo_start +
shader_prog->NumBufferInterfaceBlocks - 1);
nir->info.num_ssbos - 1);
}
/* Get the offset to read from */
@ -1696,7 +1696,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
brw_mark_surface_used(prog_data,
stage_prog_data->binding_table.ubo_start +
shader_prog->NumBufferInterfaceBlocks - 1);
nir->info.num_ssbos - 1);
}
/* Offset */
@ -1890,7 +1890,7 @@ fs_visitor::nir_emit_ssbo_atomic(const fs_builder &bld,
*/
brw_mark_surface_used(prog_data,
stage_prog_data->binding_table.ubo_start +
shader_prog->NumBufferInterfaceBlocks - 1);
nir->info.num_ssbos - 1);
}
fs_reg offset = get_nir_src(instr->src[1]);

2
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
View File

@ -698,7 +698,7 @@ fs_visitor::emit_single_fb_write(const fs_builder &bld,
fs_reg src_depth;
if (source_depth_to_render_target) {
if (prog->OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
src_depth = frag_depth;
else
src_depth = fs_reg(brw_vec8_grf(payload.source_depth_reg, 0));