r300-gallium: Moar vert shader emit.
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ddd0c94f04
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7540c847f1
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@ -329,10 +329,26 @@ void r300_emit_vertex_shader(struct r300_context* r300,
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struct r300_vertex_shader* vs)
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struct r300_vertex_shader* vs)
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{
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{
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CS_LOCALS(r300);
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CS_LOCALS(r300);
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struct r300_screen* r300screen = r300_screen(r300->context.screen);
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int i;
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int i;
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BEGIN_CS(1 + (vs->instruction_count * 4));
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if (!r300screen->caps->has_tcl) {
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debug_printf("r300: Implementation error: emit_vertex_shader called,"
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" but has_tcl is FALSE!\n");
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return;
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}
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BEGIN_CS(13 + (vs->instruction_count * 4));
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OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
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OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) |
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R300_PVS_LAST_INST(vs->instruction_count - 1));
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OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, vs->instruction_count - 1);
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/* XXX */
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OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x0);
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OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
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OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, vs->instruction_count * 4);
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OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, vs->instruction_count * 4);
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for (i = 0; i < vs->instruction_count; i++) {
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for (i = 0; i < vs->instruction_count; i++) {
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OUT_CS(vs->instructions[i].inst0);
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OUT_CS(vs->instructions[i].inst0);
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@ -340,6 +356,11 @@ void r300_emit_vertex_shader(struct r300_context* r300,
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OUT_CS(vs->instructions[i].inst2);
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OUT_CS(vs->instructions[i].inst2);
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OUT_CS(vs->instructions[i].inst3);
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OUT_CS(vs->instructions[i].inst3);
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}
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}
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OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(10) |
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R300_PVS_NUM_CNTLRS(5) |
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R300_PVS_NUM_FPUS(r300screen->caps->num_vert_fpus) |
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R300_PVS_VF_MAX_VTX_NUM(12));
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END_CS;
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END_CS;
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}
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}
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@ -73,6 +73,10 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
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# define R300_PVS_NUM_CNTLRS_SHIFT 4
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# define R300_PVS_NUM_CNTLRS_SHIFT 4
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# define R300_PVS_NUM_FPUS_SHIFT 8
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# define R300_PVS_NUM_FPUS_SHIFT 8
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# define R300_VF_MAX_VTX_NUM_SHIFT 18
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# define R300_VF_MAX_VTX_NUM_SHIFT 18
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# define R300_PVS_NUM_SLOTS(x) ((x) << 0)
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# define R300_PVS_NUM_CNTLRS(x) ((x) << 4)
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# define R300_PVS_NUM_FPUS(x) ((x) << 8)
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# define R300_PVS_VF_MAX_VTX_NUM(x) ((x) << 18)
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# define R300_GL_CLIP_SPACE_DEF (0 << 22)
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# define R300_GL_CLIP_SPACE_DEF (0 << 22)
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# define R300_DX_CLIP_SPACE_DEF (1 << 22)
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# define R300_DX_CLIP_SPACE_DEF (1 << 22)
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# define R500_TCL_STATE_OPTIMIZATION (1 << 23)
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# define R500_TCL_STATE_OPTIMIZATION (1 << 23)
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@ -506,6 +510,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
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# define R300_PVS_FIRST_INST_SHIFT 0
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# define R300_PVS_FIRST_INST_SHIFT 0
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# define R300_PVS_XYZW_VALID_INST_SHIFT 10
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# define R300_PVS_XYZW_VALID_INST_SHIFT 10
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# define R300_PVS_LAST_INST_SHIFT 20
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# define R300_PVS_LAST_INST_SHIFT 20
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# define R300_PVS_FIRST_INST(x) ((x) << 0)
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# define R300_PVS_LAST_INST(x) ((x) << 20)
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/* Addresses are relative the the vertex program parameters area. */
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/* Addresses are relative the the vertex program parameters area. */
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#define R300_VAP_PVS_CONST_CNTL 0x22D4
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#define R300_VAP_PVS_CONST_CNTL 0x22D4
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# define R300_PVS_CONST_BASE_OFFSET_SHIFT 0
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# define R300_PVS_CONST_BASE_OFFSET_SHIFT 0
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@ -86,7 +86,7 @@ void r300_emit_invariant_state(struct r300_context* r300)
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END_CS;
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END_CS;
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/* XXX unsorted stuff from surface_fill */
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/* XXX unsorted stuff from surface_fill */
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BEGIN_CS(81 + (caps->has_tcl ? 26 : 0));
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BEGIN_CS(79 + (caps->has_tcl ? 7 : 0));
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/* Flush PVS. */
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/* Flush PVS. */
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OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
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OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
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@ -67,6 +67,7 @@ struct r300_vs_asm {
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};
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};
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static struct r300_vertex_shader r300_passthrough_vertex_shader = {
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static struct r300_vertex_shader r300_passthrough_vertex_shader = {
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/* XXX translate these back into normal instructions */
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.instruction_count = 2,
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.instruction_count = 2,
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.instructions[0].inst0 = 0xF00203,
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.instructions[0].inst0 = 0xF00203,
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.instructions[0].inst1 = 0xD10001,
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.instructions[0].inst1 = 0xD10001,
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@ -42,22 +42,12 @@ static void r300_surface_setup(struct pipe_context* pipe,
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/* XXX these magic numbers should be explained when
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/* XXX these magic numbers should be explained when
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* this becomes a cached state object */
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* this becomes a cached state object */
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if (caps->has_tcl) {
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if (caps->has_tcl) {
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OUT_CS_REG(R300_VAP_CNTL, 0xA |
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(0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
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(0xB << R300_VF_MAX_VTX_NUM_SHIFT) |
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(caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
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OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000);
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OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000);
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OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001);
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/* XXX translate these back into normal instructions */
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OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1);
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OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0);
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r300_emit_vertex_shader(r300, &r300_passthrough_vertex_shader);
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r300_emit_vertex_shader(r300, &r300_passthrough_vertex_shader);
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} else {
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} else {
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OUT_CS_REG(R300_VAP_CNTL, 0xA |
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OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(5) |
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(0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
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R300_PVS_NUM_CNTLRS(5) |
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(0x5 << R300_VF_MAX_VTX_NUM_SHIFT) |
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R300_PVS_NUM_FPUS(caps->num_vert_fpus) |
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(caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
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R300_PVS_VF_MAX_VTX_NUM(12));
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}
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}
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BEGIN_CS(15);
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BEGIN_CS(15);
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