intel/isl: Refactor isl_surf_get_ccs_surf
This refactor breaks out a new isl_surf_supports_ccs function which does most of the validity checking. The isl_surf_get_ccs_surf function calls this function and then dives right into constructing the CCS aux_surf. Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4100>
This commit is contained in:
parent
3eb1993625
commit
752eefdb3d
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@ -1920,6 +1920,161 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
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.tiling_flags = ISL_TILING_Y0_BIT);
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.tiling_flags = ISL_TILING_Y0_BIT);
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}
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}
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bool
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isl_surf_supports_ccs(const struct isl_device *dev,
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const struct isl_surf *surf)
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{
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/* CCS support does not exist prior to Gen7 */
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if (ISL_DEV_GEN(dev) <= 6)
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return false;
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if (surf->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
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return false;
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if (isl_format_is_compressed(surf->format))
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return false;
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if (!isl_is_pow2(isl_format_get_layout(surf->format)->bpb))
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return false;
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "Fast Color Clear" bullet (p326):
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*
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* - Support is limited to tiled render targets.
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*
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* From the Skylake documentation, it is made clear that X-tiling is no
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* longer supported:
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*
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* - MCS and Lossless compression is supported for
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* TiledY/TileYs/TileYf non-MSRTs only.
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*
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* From the BSpec (44930) for Gen12:
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*
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* Linear CCS is only allowed for Untyped Buffers but only via HDC
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* Data-Port messages.
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*
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* We never use untyped messages on surfaces created by ISL on Gen9+ so
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* this means linear is out on Gen12+ as well.
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*/
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if (surf->tiling == ISL_TILING_LINEAR)
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return false;
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if (ISL_DEV_GEN(dev) >= 12) {
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if (isl_surf_usage_is_stencil(surf->usage) && surf->samples > 1)
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return false;
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/* [TGL+] CCS can only be added to a non-D16-formatted depth buffer if
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* it has HiZ. If not for GEN:BUG:1406512483 "deprecate compression
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* enable states", D16 would be supported. Supporting D16 requires being
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* able to specify that the control surface is present and
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* simultaneously disabling compression. The above bug makes it so that
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* it's not possible to specify this configuration.
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*
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* Note: ISL Doesn't currently support depth CCS without HiZ at all.
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*/
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if (isl_surf_usage_is_depth(surf->usage) &&
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surf->format == ISL_FORMAT_R16_UNORM) {
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return false;
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}
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/* On Gen12, 8BPP surfaces cannot be compressed if any level is not
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* 32Bx4row-aligned. For now, just reject the cases where alignment
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* matters.
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*/
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if (isl_format_get_layout(surf->format)->bpb == 8 && surf->levels >= 3) {
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isl_finishme("%s:%s: CCS for 8BPP textures with 3+ miplevels is "
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"disabled, but support for more levels is possible.",
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__FILE__, __func__);
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return false;
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}
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/* On Gen12, all CCS-compressed surface pitches must be multiples of
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* 512B.
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*/
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if (surf->row_pitch_B % 512 != 0)
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return false;
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/* According to GEN:BUG:1406738321, 3D textures need a blit to a new
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* surface in order to perform a resolve. For now, just disable CCS.
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*/
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if (surf->dim == ISL_SURF_DIM_3D) {
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isl_finishme("%s:%s: CCS for 3D textures is disabled, but a workaround"
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" is available.", __FILE__, __func__);
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return false;
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}
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/* GEN:BUG:1207137018
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*
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* TODO: implement following workaround currently covered by the
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* restriction above. If following conditions are met:
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*
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* - RENDER_SURFACE_STATE.Surface Type == 3D
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* - RENDER_SURFACE_STATE.Auxiliary Surface Mode != AUX_NONE
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* - RENDER_SURFACE_STATE.Tiled ResourceMode is TYF or TYS
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*
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* Set the value of RENDER_SURFACE_STATE.Mip Tail Start LOD to a mip
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* that larger than those present in the surface (i.e. 15)
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*/
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/* TODO: Handle the other tiling formats */
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if (surf->tiling != ISL_TILING_Y0)
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return false;
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} else {
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/* ISL_DEV_GEN(dev) < 12 */
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if (surf->samples > 1)
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return false;
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/* CCS is only for color images on Gen7-11 */
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if (isl_surf_usage_is_depth_or_stencil(surf->usage))
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return false;
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/* The PRM doesn't say this explicitly, but fast-clears don't appear to
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* work for 3D textures until gen9 where the layout of 3D textures
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* changes to match 2D array textures.
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*/
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if (ISL_DEV_GEN(dev) <= 8 && surf->dim != ISL_SURF_DIM_2D)
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return false;
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/* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
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* Non-MultiSampler Render Target Restrictions):
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*
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* "Support is for non-mip-mapped and non-array surface types only."
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*
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* This restriction is lifted on gen8+. Technically, it may be possible
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* to create a CCS for an arrayed or mipmapped image and only enable
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* CCS_D when rendering to the base slice. However, there is no
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* documentation tell us what the hardware would do in that case or what
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* it does if you walk off the bases slice. (Does it ignore CCS or does
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* it start scribbling over random memory?) We play it safe and just
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* follow the docs and don't allow CCS_D for arrayed or mip-mapped
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* surfaces.
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*/
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if (ISL_DEV_GEN(dev) <= 7 &&
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(surf->levels > 1 || surf->logical_level0_px.array_len > 1))
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return false;
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "Fast Color Clear" bullet (p326):
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*
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* - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
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* 64bpp, and 128bpp.
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*/
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if (isl_format_get_layout(surf->format)->bpb < 32)
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return false;
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/* From the Skylake documentation, it is made clear that X-tiling is no
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* longer supported:
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*
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* - MCS and Lossless compression is supported for
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* TiledY/TileYs/TileYf non-MSRTs only.
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*/
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if (ISL_DEV_GEN(dev) >= 9 && !isl_tiling_is_any_y(surf->tiling))
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return false;
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}
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return true;
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}
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bool
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bool
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isl_surf_get_ccs_surf(const struct isl_device *dev,
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isl_surf_get_ccs_surf(const struct isl_device *dev,
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const struct isl_surf *surf,
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const struct isl_surf *surf,
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@ -1939,127 +2094,11 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
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if (aux_surf->usage & ISL_SURF_USAGE_CCS_BIT)
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if (aux_surf->usage & ISL_SURF_USAGE_CCS_BIT)
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return false;
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return false;
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if (ISL_DEV_GEN(dev) < 12 && surf->samples > 1)
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if (!isl_surf_supports_ccs(dev, surf))
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return false;
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return false;
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/* CCS support does not exist prior to Gen7 */
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if (ISL_DEV_GEN(dev) <= 6)
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return false;
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if (surf->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
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return false;
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/* Allow CCS for single-sampled stencil buffers Gen12+. */
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if (isl_surf_usage_is_stencil(surf->usage) &&
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(ISL_DEV_GEN(dev) < 12 || surf->samples > 1))
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return false;
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/* [TGL+] CCS can only be added to a non-D16-formatted depth buffer if it
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* has HiZ. If not for GEN:BUG:1406512483 "deprecate compression enable
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* states", D16 would be supported. Supporting D16 requires being able to
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* specify that the control surface is present and simultaneously disabling
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* compression. The above bug makes it so that it's not possible to specify
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* this configuration.
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*/
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if (isl_surf_usage_is_depth(surf->usage) && (aux_surf->size_B == 0 ||
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ISL_DEV_GEN(dev) < 12 || surf->format == ISL_FORMAT_R16_UNORM)) {
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return false;
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}
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/* The PRM doesn't say this explicitly, but fast-clears don't appear to
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* work for 3D textures until gen9 where the layout of 3D textures changes
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* to match 2D array textures.
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*/
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if (ISL_DEV_GEN(dev) <= 8 && surf->dim != ISL_SURF_DIM_2D)
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return false;
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/* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
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* Non-MultiSampler Render Target Restrictions):
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*
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* "Support is for non-mip-mapped and non-array surface types only."
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*
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* This restriction is lifted on gen8+. Technically, it may be possible to
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* create a CCS for an arrayed or mipmapped image and only enable CCS_D
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* when rendering to the base slice. However, there is no documentation
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* tell us what the hardware would do in that case or what it does if you
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* walk off the bases slice. (Does it ignore CCS or does it start
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* scribbling over random memory?) We play it safe and just follow the
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* docs and don't allow CCS_D for arrayed or mip-mapped surfaces.
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*/
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if (ISL_DEV_GEN(dev) <= 7 &&
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(surf->levels > 1 || surf->logical_level0_px.array_len > 1))
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return false;
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/* On Gen12, 8BPP surfaces cannot be compressed if any level is not
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* 32Bx4row-aligned. For now, just reject the cases where alignment
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* matters.
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*/
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if (ISL_DEV_GEN(dev) >= 12 &&
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isl_format_get_layout(surf->format)->bpb == 8 && surf->levels >= 3) {
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isl_finishme("%s:%s: CCS for 8BPP textures with 3+ miplevels is "
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"disabled, but support for more levels is possible.",
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__FILE__, __func__);
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return false;
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}
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/* On Gen12, all CCS-compressed surface pitches must be multiples of 512B.
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*/
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if (ISL_DEV_GEN(dev) >= 12 && surf->row_pitch_B % 512 != 0)
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return false;
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if (isl_format_is_compressed(surf->format))
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return false;
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/* According to GEN:BUG:1406738321, 3D textures need a blit to a new
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* surface in order to perform a resolve. For now, just disable CCS.
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*/
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if (ISL_DEV_GEN(dev) >= 12 && surf->dim == ISL_SURF_DIM_3D) {
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isl_finishme("%s:%s: CCS for 3D textures is disabled, but a workaround"
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" is available.", __FILE__, __func__);
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return false;
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}
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/* GEN:BUG:1207137018
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*
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* TODO: implement following workaround currently covered by the restriction
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* above. If following conditions are met:
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*
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* - RENDER_SURFACE_STATE.Surface Type == 3D
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* - RENDER_SURFACE_STATE.Auxiliary Surface Mode != AUX_NONE
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* - RENDER_SURFACE_STATE.Tiled ResourceMode is TYF or TYS
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*
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* Set the value of RENDER_SURFACE_STATE.Mip Tail Start LOD to a mip that
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* larger than those present in the surface (i.e. 15)
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*/
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/* TODO: More conditions where it can fail. */
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/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
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* Target(s)", beneath the "Fast Color Clear" bullet (p326):
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*
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* - Support is limited to tiled render targets.
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* - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
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* 64bpp, and 128bpp.
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*
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* From the Skylake documentation, it is made clear that X-tiling is no
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* longer supported:
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*
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* - MCS and Lossless compression is supported for
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* TiledY/TileYs/TileYf non-MSRTs only.
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*/
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enum isl_format ccs_format;
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if (ISL_DEV_GEN(dev) >= 12) {
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if (ISL_DEV_GEN(dev) >= 12) {
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/* TODO: Handle the other tiling formats */
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enum isl_format ccs_format;
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if (surf->tiling != ISL_TILING_Y0)
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return false;
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/* BSpec 44930:
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*
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* Linear CCS is only allowed for Untyped Buffers but only via HDC
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* Data-Port messages.
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*/
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assert(surf->tiling != ISL_TILING_LINEAR);
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switch (isl_format_get_layout(surf->format)->bpb) {
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switch (isl_format_get_layout(surf->format)->bpb) {
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case 8: ccs_format = ISL_FORMAT_GEN12_CCS_8BPP_Y0; break;
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case 8: ccs_format = ISL_FORMAT_GEN12_CCS_8BPP_Y0; break;
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case 16: ccs_format = ISL_FORMAT_GEN12_CCS_16BPP_Y0; break;
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case 16: ccs_format = ISL_FORMAT_GEN12_CCS_16BPP_Y0; break;
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@ -2069,38 +2108,7 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
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default:
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default:
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return false;
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return false;
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}
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}
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} else if (ISL_DEV_GEN(dev) >= 9) {
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if (!isl_tiling_is_any_y(surf->tiling))
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return false;
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switch (isl_format_get_layout(surf->format)->bpb) {
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case 32: ccs_format = ISL_FORMAT_GEN9_CCS_32BPP; break;
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case 64: ccs_format = ISL_FORMAT_GEN9_CCS_64BPP; break;
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case 128: ccs_format = ISL_FORMAT_GEN9_CCS_128BPP; break;
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default:
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return false;
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}
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} else if (surf->tiling == ISL_TILING_Y0) {
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switch (isl_format_get_layout(surf->format)->bpb) {
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case 32: ccs_format = ISL_FORMAT_GEN7_CCS_32BPP_Y; break;
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case 64: ccs_format = ISL_FORMAT_GEN7_CCS_64BPP_Y; break;
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case 128: ccs_format = ISL_FORMAT_GEN7_CCS_128BPP_Y; break;
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default:
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return false;
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}
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} else if (surf->tiling == ISL_TILING_X) {
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switch (isl_format_get_layout(surf->format)->bpb) {
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case 32: ccs_format = ISL_FORMAT_GEN7_CCS_32BPP_X; break;
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case 64: ccs_format = ISL_FORMAT_GEN7_CCS_64BPP_X; break;
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case 128: ccs_format = ISL_FORMAT_GEN7_CCS_128BPP_X; break;
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default:
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return false;
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}
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} else {
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return false;
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}
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if (ISL_DEV_GEN(dev) >= 12) {
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/* On Gen12, the CCS is a scaled-down version of the main surface. We
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/* On Gen12, the CCS is a scaled-down version of the main surface. We
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* model this as the CCS compressing a 2D-view of the entire surface.
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* model this as the CCS compressing a 2D-view of the entire surface.
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*/
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*/
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||||||
|
@ -2122,6 +2130,33 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
|
||||||
assert(!ok || ccs_surf->size_B == surf->size_B / 256);
|
assert(!ok || ccs_surf->size_B == surf->size_B / 256);
|
||||||
return ok;
|
return ok;
|
||||||
} else {
|
} else {
|
||||||
|
enum isl_format ccs_format;
|
||||||
|
if (ISL_DEV_GEN(dev) >= 9) {
|
||||||
|
switch (isl_format_get_layout(surf->format)->bpb) {
|
||||||
|
case 32: ccs_format = ISL_FORMAT_GEN9_CCS_32BPP; break;
|
||||||
|
case 64: ccs_format = ISL_FORMAT_GEN9_CCS_64BPP; break;
|
||||||
|
case 128: ccs_format = ISL_FORMAT_GEN9_CCS_128BPP; break;
|
||||||
|
default: unreachable("Unsupported CCS format");
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
} else if (surf->tiling == ISL_TILING_Y0) {
|
||||||
|
switch (isl_format_get_layout(surf->format)->bpb) {
|
||||||
|
case 32: ccs_format = ISL_FORMAT_GEN7_CCS_32BPP_Y; break;
|
||||||
|
case 64: ccs_format = ISL_FORMAT_GEN7_CCS_64BPP_Y; break;
|
||||||
|
case 128: ccs_format = ISL_FORMAT_GEN7_CCS_128BPP_Y; break;
|
||||||
|
default: unreachable("Unsupported CCS format");
|
||||||
|
}
|
||||||
|
} else if (surf->tiling == ISL_TILING_X) {
|
||||||
|
switch (isl_format_get_layout(surf->format)->bpb) {
|
||||||
|
case 32: ccs_format = ISL_FORMAT_GEN7_CCS_32BPP_X; break;
|
||||||
|
case 64: ccs_format = ISL_FORMAT_GEN7_CCS_64BPP_X; break;
|
||||||
|
case 128: ccs_format = ISL_FORMAT_GEN7_CCS_128BPP_X; break;
|
||||||
|
default: unreachable("Unsupported CCS format");
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
unreachable("Invalid tiling format");
|
||||||
|
}
|
||||||
|
|
||||||
return isl_surf_init(dev, aux_surf,
|
return isl_surf_init(dev, aux_surf,
|
||||||
.dim = surf->dim,
|
.dim = surf->dim,
|
||||||
.format = ccs_format,
|
.format = ccs_format,
|
||||||
|
|
|
@ -1987,6 +1987,10 @@ void
|
||||||
isl_surf_get_tile_info(const struct isl_surf *surf,
|
isl_surf_get_tile_info(const struct isl_surf *surf,
|
||||||
struct isl_tile_info *tile_info);
|
struct isl_tile_info *tile_info);
|
||||||
|
|
||||||
|
bool
|
||||||
|
isl_surf_supports_ccs(const struct isl_device *dev,
|
||||||
|
const struct isl_surf *surf);
|
||||||
|
|
||||||
bool
|
bool
|
||||||
isl_surf_get_hiz_surf(const struct isl_device *dev,
|
isl_surf_get_hiz_surf(const struct isl_device *dev,
|
||||||
const struct isl_surf *surf,
|
const struct isl_surf *surf,
|
||||||
|
|
Loading…
Reference in New Issue