freedreno/a6xx: Fix a6xx gen4 compute shaders
I believe the addition of these new regs is related to the changes made for LPAC ring, so let's key off of that. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
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@ -117,6 +117,8 @@ struct fd_dev_info {
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*/
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bool has_ccu_flush_bug;
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bool has_lpac;
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struct {
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uint32_t RB_UNKNOWN_8E04_blit;
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uint32_t PC_POWER_CNTL;
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@ -238,6 +238,7 @@ a6xx_gen4 = dict(
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has_sample_locations = True,
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has_cp_reg_write = False,
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has_8bpp_ubwc = False,
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has_lpac = True,
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)
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add_gpus([
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@ -75,6 +75,12 @@ cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
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OUT_RING(ring, A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(shared_size) |
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A6XX_SP_CS_UNKNOWN_A9B1_UNK6);
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if (ctx->screen->info->a6xx.has_lpac) {
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OUT_PKT4(ring, REG_A6XX_HLSQ_CS_UNKNOWN_B9D0, 1);
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OUT_RING(ring, A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(shared_size) |
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A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6);
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}
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uint32_t local_invocation_id, work_group_id;
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local_invocation_id =
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ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
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@ -88,6 +94,16 @@ cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
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OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
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A6XX_HLSQ_CS_CNTL_1_THREADSIZE(thrsz));
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if (ctx->screen->info->a6xx.has_lpac) {
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OUT_PKT4(ring, REG_A6XX_SP_CS_CNTL_0, 2);
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OUT_RING(ring, A6XX_SP_CS_CNTL_0_WGIDCONSTID(work_group_id) |
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A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
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A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
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A6XX_SP_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
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OUT_RING(ring, A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
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A6XX_SP_CS_CNTL_1_THREADSIZE(thrsz));
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}
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OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START, 2);
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OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
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