iris: Remove render cache hash table-based synchronization.
The render cache hash table is now *mostly* redundant with the more general seqno matrix-based cache tracking mechanism. Most hash table operations are now gone except for the format mismatch checks done in iris_cache_flush_for_render(). Redundant code removed as a separate patch for bisectability. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3875>
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@ -399,8 +399,6 @@ iris_batch_reset(struct iris_batch *batch)
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iris_batch_add_syncobj(batch, syncobj, I915_EXEC_FENCE_SIGNAL);
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iris_syncobj_reference(screen, &syncobj, NULL);
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iris_cache_sets_clear(batch);
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assert(!batch->sync_region_depth);
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iris_batch_sync_boundary(batch);
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iris_batch_mark_reset_sync(batch);
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@ -367,12 +367,6 @@ iris_blorp_exec(struct blorp_batch *blorp_batch,
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ice->state.dirty |= ~skip_bits;
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ice->state.stage_dirty |= ~skip_stage_bits;
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if (params->dst.enabled) {
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iris_render_cache_add_bo(batch, params->dst.addr.buffer,
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params->dst.view.format,
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params->dst.aux_usage);
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}
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if (params->src.enabled)
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iris_bo_bump_seqno(params->src.addr.buffer, batch->next_seqno,
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IRIS_DOMAIN_OTHER_READ);
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@ -910,17 +910,12 @@ void iris_predraw_resolve_framebuffer(struct iris_context *ice,
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bool *draw_aux_buffer_disabled);
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void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
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struct iris_batch *batch);
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void iris_cache_sets_clear(struct iris_batch *batch);
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void iris_flush_depth_and_render_caches(struct iris_batch *batch);
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void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
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void iris_cache_flush_for_render(struct iris_batch *batch,
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struct iris_bo *bo,
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enum isl_format format,
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enum isl_aux_usage aux_usage);
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void iris_render_cache_add_bo(struct iris_batch *batch,
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struct iris_bo *bo,
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enum isl_format format,
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enum isl_aux_usage aux_usage);
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void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
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int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
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struct pipe_driver_query_info *info);
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@ -306,8 +306,7 @@ iris_texture_barrier(struct pipe_context *ctx, unsigned flags)
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struct iris_batch *render_batch = &ice->batches[IRIS_BATCH_RENDER];
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struct iris_batch *compute_batch = &ice->batches[IRIS_BATCH_COMPUTE];
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if (render_batch->contains_draw ||
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render_batch->cache.render->entries) {
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if (render_batch->contains_draw) {
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iris_batch_maybe_flush(render_batch, 48);
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iris_emit_pipe_control_flush(render_batch,
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"API: texture barrier (1/2)",
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@ -353,8 +352,7 @@ iris_memory_barrier(struct pipe_context *ctx, unsigned flags)
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}
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for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
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if (ice->batches[i].contains_draw ||
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ice->batches[i].cache.render->entries) {
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if (ice->batches[i].contains_draw) {
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iris_batch_maybe_flush(&ice->batches[i], 24);
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iris_emit_pipe_control_flush(&ice->batches[i], "API: memory barrier",
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bits);
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@ -319,9 +319,6 @@ iris_postdraw_update_resolve_tracking(struct iris_context *ice,
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struct iris_resource *res = (void *) surf->base.texture;
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enum isl_aux_usage aux_usage = ice->state.draw_aux_usage[i];
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iris_render_cache_add_bo(batch, res->bo, surf->view.format,
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aux_usage);
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if (may_have_resolved_color) {
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union pipe_surface_desc *desc = &surf->base.u;
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unsigned num_layers =
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@ -333,16 +330,6 @@ iris_postdraw_update_resolve_tracking(struct iris_context *ice,
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}
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}
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/**
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* Clear the cache-tracking sets.
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*/
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void
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iris_cache_sets_clear(struct iris_batch *batch)
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{
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hash_table_foreach(batch->cache.render, render_entry)
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_mesa_hash_table_remove(batch->cache.render, render_entry);
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}
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/**
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* Emits an appropriate flush for a BO if it has been rendered to within the
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* same batchbuffer as a read that's about to be emitted.
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@ -368,17 +355,12 @@ iris_flush_depth_and_render_caches(struct iris_batch *batch)
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"cache tracker: render-to-texture",
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PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
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PIPE_CONTROL_CONST_CACHE_INVALIDATE);
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iris_cache_sets_clear(batch);
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}
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void
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iris_cache_flush_for_read(struct iris_batch *batch,
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struct iris_bo *bo)
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{
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if (_mesa_hash_table_search_pre_hashed(batch->cache.render, bo->hash, bo))
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iris_flush_depth_and_render_caches(batch);
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iris_emit_buffer_barrier_for(batch, bo, IRIS_DOMAIN_OTHER_READ);
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}
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@ -421,38 +403,19 @@ iris_cache_flush_for_render(struct iris_batch *batch,
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*/
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struct hash_entry *entry =
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_mesa_hash_table_search_pre_hashed(batch->cache.render, bo->hash, bo);
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if (entry && entry->data != format_aux_tuple(format, aux_usage))
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iris_flush_depth_and_render_caches(batch);
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}
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void
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iris_render_cache_add_bo(struct iris_batch *batch,
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struct iris_bo *bo,
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enum isl_format format,
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enum isl_aux_usage aux_usage)
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{
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#ifndef NDEBUG
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struct hash_entry *entry =
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_mesa_hash_table_search_pre_hashed(batch->cache.render, bo->hash, bo);
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if (entry) {
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/* Otherwise, someone didn't do a flush_for_render and that would be
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* very bad indeed.
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*/
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assert(entry->data == format_aux_tuple(format, aux_usage));
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}
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#endif
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if (!entry) {
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_mesa_hash_table_insert_pre_hashed(batch->cache.render, bo->hash, bo,
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format_aux_tuple(format, aux_usage));
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} else if (entry->data != format_aux_tuple(format, aux_usage)) {
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iris_flush_depth_and_render_caches(batch);
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entry->data = format_aux_tuple(format, aux_usage);
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}
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}
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void
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iris_cache_flush_for_depth(struct iris_batch *batch,
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struct iris_bo *bo)
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{
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if (_mesa_hash_table_search_pre_hashed(batch->cache.render, bo->hash, bo))
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iris_flush_depth_and_render_caches(batch);
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iris_emit_buffer_barrier_for(batch, bo, IRIS_DOMAIN_DEPTH_WRITE);
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}
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