[r300] Sync the names for Z-Buffer registers with the AMD spec
This patch tries to get the Z-Buffer register names in sync with the AMD spec so that talking to AMD engineers is much simpler.
This commit is contained in:
parent
1b51c135fc
commit
74ae5a875d
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@ -429,9 +429,9 @@ void r300InitCmdBuf(r300ContextPtr r300)
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cmdpacket0(R300_RB3D_ZSTENCIL_CNTL_0, 3);
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cmdpacket0(R300_RB3D_ZSTENCIL_CNTL_0, 3);
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ALLOC_STATE(zstencil_format, always, 5, 0);
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ALLOC_STATE(zstencil_format, always, 5, 0);
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r300->hw.zstencil_format.cmd[0] =
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r300->hw.zstencil_format.cmd[0] =
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cmdpacket0(R300_RB3D_ZSTENCIL_FORMAT, 4);
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cmdpacket0(ZB_FORMAT, 4);
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ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
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ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
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r300->hw.zb.cmd[R300_ZB_CMD_0] = cmdpacket0(R300_RB3D_DEPTHOFFSET, 2);
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r300->hw.zb.cmd[R300_ZB_CMD_0] = cmdpacket0(ZB_DEPTHOFFSET, 2);
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ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
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ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
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r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(ZB_DEPTHCLEARVALUE, 1);
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r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(ZB_DEPTHCLEARVALUE, 1);
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ALLOC_STATE(unk4F30, always, 3, 0);
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ALLOC_STATE(unk4F30, always, 3, 0);
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@ -544,8 +544,8 @@ void r300EmitCacheFlush(r300ContextPtr rmesa)
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reg_start(R300_RB3D_DSTCACHE_CTLSTAT, 0);
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reg_start(R300_RB3D_DSTCACHE_CTLSTAT, 0);
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e32(R300_RB3D_DSTCACHE_UNKNOWN_0A);
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e32(R300_RB3D_DSTCACHE_UNKNOWN_0A);
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reg_start(R300_RB3D_ZCACHE_CTLSTAT, 0);
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reg_start(ZB_ZCACHE_CTLSTAT, 0);
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e32(R300_RB3D_ZCACHE_UNKNOWN_03);
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e32(ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
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}
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}
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@ -1688,19 +1688,24 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
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# define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21
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# define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21
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# define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24
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# define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24
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#define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08
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#define ZB_STENCILREFMASK 0x4f08
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# define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0
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# define ZB_STENCILREFMASK_STENCILREF_SHIFT 0
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# define R300_RB3D_ZS2_STENCIL_MASK 0xFF
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# define ZB_STENCILREFMASK_STENCILREF_MASK 0x000000ff
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# define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8
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# define ZB_STENCILREFMASK_STENCILMASK_SHIFT 8
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# define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16
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# define ZB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00
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# define ZB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16
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# define ZB_STENCILREFMASK_STENCILWRITEMASK_MASK 0xffff0000
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/* gap */
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/* gap */
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#define R300_RB3D_ZSTENCIL_FORMAT 0x4F10
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#define ZB_FORMAT 0x4f10
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# define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
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# define ZB_FORMAR_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
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# define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
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# define ZB_FORMAR_DEPTHFORMAT_16BIT_13E3 (1 << 0)
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/* 16 bit format or some aditional bit ? */
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# define ZB_FORMAR_DEPTHFORMAT_24BIT_INT_Z (2 << 0)
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# define R300_DEPTH_FORMAT_UNK32 (32 << 0)
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/* reserved up to (15 << 0) */
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# define ZB_FORMAR_INVERT_13E3_LEADING_ONES (0 << 4)
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# define ZB_FORMAR_INVERT_13E3_LEADING_ZEROS (1 << 4)
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# define ZB_FORMAR_PEQ8_UNUSED (1 << 5)
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#define R300_RB3D_EARLY_Z 0x4F14
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#define R300_RB3D_EARLY_Z 0x4F14
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# define R300_EARLY_Z_DISABLE (0 << 0)
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# define R300_EARLY_Z_DISABLE (0 << 0)
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@ -1708,9 +1713,13 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
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/* gap */
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/* gap */
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#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */
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#define ZB_ZCACHE_CTLSTAT 0x4f18
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# define R300_RB3D_ZCACHE_UNKNOWN_01 0x1
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# define ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
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# define R300_RB3D_ZCACHE_UNKNOWN_03 0x3
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# define ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
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# define ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
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# define ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
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# define ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 1)
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# define ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 1)
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#define R300_ZB_BW_CNTL 0x4f1c
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#define R300_ZB_BW_CNTL 0x4f1c
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# define R300_HIZ_DISABLE (0 << 0)
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# define R300_HIZ_DISABLE (0 << 0)
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@ -1756,14 +1765,23 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
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/* gap */
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/* gap */
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#define R300_RB3D_DEPTHOFFSET 0x4F20
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/* Z Buffer Address Offset.
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#define R300_RB3D_DEPTHPITCH 0x4F24
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* Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
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# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */
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*/
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# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */
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#define ZB_DEPTHOFFSET 0x4f20
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# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */
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# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
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/* Z Buffer Pitch and Endian Control */
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# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
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#define ZB_DEPTHPITCH 0x4f24
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# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
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# define R300_DEPTHPITCH_MASK 0x00001FF8 /* TODO: should be (13:2) */
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# define ZB_DEPTHPITCH_DEPTHMACROTILE_DISABLE (0 << 16)
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# define ZB_DEPTHPITCH_DEPTHMACROTILE_ENABLE (1 << 16)
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# define ZB_DEPTHPITCH_DEPTHMICROTILE_LINEAR (0 << 17)
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# define ZB_DEPTHPITCH_DEPTHMICROTILE_TILED (1 << 17)
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# define ZB_DEPTHPITCH_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
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# define ZB_DEPTHPITCH_DEPTHENDIAN_NO_SWAP (0 << 18)
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# define ZB_DEPTHPITCH_DEPTHENDIAN_WORD_SWAP (1 << 18)
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# define ZB_DEPTHPITCH_DEPTHENDIAN_DWORD_SWAP (2 << 18)
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# define ZB_DEPTHPITCH_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
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/* Z Buffer Clear Value */
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/* Z Buffer Clear Value */
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#define ZB_DEPTHCLEARVALUE 0x4f28
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#define ZB_DEPTHCLEARVALUE 0x4f28
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@ -1774,12 +1792,44 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
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/* Hierarchical Z Read Index */
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/* Hierarchical Z Read Index */
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#define ZB_HIZ_RDINDEX 0x4f48
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#define ZB_HIZ_RDINDEX 0x4f48
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/* Hierarchical Z Data */
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#define ZB_HIZ_DWORD 0x4f4c
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/* Hierarchical Z Write Index */
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/* Hierarchical Z Write Index */
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#define ZB_HIZ_WRINDEX 0x4f50
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#define ZB_HIZ_WRINDEX 0x4f50
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/* Hierarchical Z Pitch */
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/* Hierarchical Z Pitch */
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#define ZB_HIZ_PITCH 0x4f54
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#define ZB_HIZ_PITCH 0x4f54
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/* Z Buffer Z Pass Counter Data */
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#define ZB_ZPASS_DATA 0x4f58
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/* Z Buffer Z Pass Counter Address */
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#define ZB_ZPASS_ADDR 0x4f5c
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/* Depth buffer X and Y coordinate offset */
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#define ZB_DEPTHXY_OFFSET 0x4f60
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# define ZB_DEPTHX_OFFSET_SHIFT 1
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# define ZB_DEPTHX_OFFSET_MASK 0x000007FE
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# define ZB_DEPTHY_OFFSET_SHIFT 17
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# define ZB_DEPTHY_OFFSET_MASK 0x07FE0000
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/* Sets the fifo sizes */
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#define ZB_FIFO_SIZE 0x4fd0
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# define ZB_FIFO_SIZE_OP_FIFO_SIZE_FULL (0 << 0)
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# define ZB_FIFO_SIZE_OP_FIFO_SIZE_HALF (1 << 0)
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# define ZB_FIFO_SIZE_OP_FIFO_SIZE_QUATER (2 << 0)
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# define ZB_FIFO_SIZE_OP_FIFO_SIZE_EIGTHS (4 << 0)
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/* Stencil Reference Value and Mask for backfacing quads */
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#define ZB_STENCILREFMASK_BF 0x4fd4
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# define ZB_STENCILREFMASK_BF_STENCILREF_SHIFT 0
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# define ZB_STENCILREFMASK_BF_STENCILREF_MASK 0x000000ff
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# define ZB_STENCILREFMASK_BF_STENCILMASK_SHIFT 8
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# define ZB_STENCILREFMASK_BF_STENCILMASK_MASK 0x0000ff00
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# define ZB_STENCILREFMASK_BF_STENCILWRITEMASK_SHIFT 16
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# define ZB_STENCILREFMASK_BF_STENCILWRITEMASK_MASK 0xffff0000
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/* BEGIN: Vertex program instruction set */
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/* BEGIN: Vertex program instruction set */
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/* Every instruction is four dwords long:
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/* Every instruction is four dwords long:
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@ -363,18 +363,16 @@ static void r300SetEarlyZState(GLcontext * ctx)
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R300_STATECHANGE(r300, zstencil_format);
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R300_STATECHANGE(r300, zstencil_format);
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switch (ctx->Visual.depthBits) {
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switch (ctx->Visual.depthBits) {
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case 16:
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case 16:
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r300->hw.zstencil_format.cmd[1] = R300_DEPTH_FORMAT_16BIT_INT_Z;
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r300->hw.zstencil_format.cmd[1] = ZB_FORMAR_DEPTHFORMAT_16BIT_INT_Z;
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break;
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break;
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case 24:
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case 24:
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r300->hw.zstencil_format.cmd[1] = R300_DEPTH_FORMAT_24BIT_INT_Z;
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r300->hw.zstencil_format.cmd[1] = ZB_FORMAR_DEPTHFORMAT_24BIT_INT_Z;
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break;
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break;
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default:
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default:
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fprintf(stderr, "Error: Unsupported depth %d... exiting\n", ctx->Visual.depthBits);
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fprintf(stderr, "Error: Unsupported depth %d... exiting\n", ctx->Visual.depthBits);
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_mesa_exit(-1);
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_mesa_exit(-1);
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}
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}
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// r300->hw.zstencil_format.cmd[1] |= R300_DEPTH_FORMAT_UNK32;
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if (ctx->Color.AlphaEnabled && ctx->Color.AlphaFunc != GL_ALWAYS)
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if (ctx->Color.AlphaEnabled && ctx->Color.AlphaFunc != GL_ALWAYS)
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/* disable early Z */
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/* disable early Z */
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r300->hw.zstencil_format.cmd[2] = R300_EARLY_Z_DISABLE;
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r300->hw.zstencil_format.cmd[2] = R300_EARLY_Z_DISABLE;
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@ -822,13 +820,13 @@ static void r300StencilFuncSeparate(GLcontext * ctx, GLenum face,
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r300ContextPtr rmesa = R300_CONTEXT(ctx);
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r300ContextPtr rmesa = R300_CONTEXT(ctx);
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GLuint refmask =
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GLuint refmask =
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(((ctx->Stencil.
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(((ctx->Stencil.
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Ref[0] & 0xff) << R300_RB3D_ZS2_STENCIL_REF_SHIFT) | ((ctx->
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Ref[0] & 0xff) << ZB_STENCILREFMASK_STENCILREF_SHIFT) | ((ctx->
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Stencil.
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Stencil.
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ValueMask
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ValueMask
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[0] &
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[0] &
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0xff)
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0xff)
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<<
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<<
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R300_RB3D_ZS2_STENCIL_MASK_SHIFT));
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ZB_STENCILREFMASK_STENCILMASK_SHIFT));
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GLuint flag;
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GLuint flag;
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@ -840,9 +838,8 @@ static void r300StencilFuncSeparate(GLcontext * ctx, GLenum face,
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R300_RB3D_ZS1_BACK_FUNC_SHIFT));
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R300_RB3D_ZS1_BACK_FUNC_SHIFT));
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rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
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rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
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~((R300_RB3D_ZS2_STENCIL_MASK <<
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~((ZB_STENCILREFMASK_STENCILREF_MASK << ZB_STENCILREFMASK_STENCILREF_SHIFT) |
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R300_RB3D_ZS2_STENCIL_REF_SHIFT) |
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(ZB_STENCILREFMASK_STENCILMASK_MASK << ZB_STENCILREFMASK_STENCILMASK_SHIFT));
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(R300_RB3D_ZS2_STENCIL_MASK << R300_RB3D_ZS2_STENCIL_MASK_SHIFT));
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flag = translate_func(ctx->Stencil.Function[0]);
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flag = translate_func(ctx->Stencil.Function[0]);
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rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
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rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
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@ -862,11 +859,11 @@ static void r300StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask)
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R300_STATECHANGE(rmesa, zs);
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R300_STATECHANGE(rmesa, zs);
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rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
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rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
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~(R300_RB3D_ZS2_STENCIL_MASK <<
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~(ZB_STENCILREFMASK_STENCILMASK_MASK <<
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R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT);
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ZB_STENCILREFMASK_STENCILWRITEMASK_SHIFT);
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rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |=
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rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |=
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(ctx->Stencil.
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(ctx->Stencil.
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WriteMask[0] & 0xff) << R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT;
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WriteMask[0] & 0xff) << ZB_STENCILREFMASK_STENCILWRITEMASK_SHIFT;
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}
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}
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static void r300StencilOpSeparate(GLcontext * ctx, GLenum face,
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static void r300StencilOpSeparate(GLcontext * ctx, GLenum face,
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@ -914,10 +911,10 @@ static void r300ClearStencil(GLcontext * ctx, GLint s)
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rmesa->state.stencil.clear =
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rmesa->state.stencil.clear =
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((GLuint) (ctx->Stencil.Clear & 0xff) |
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((GLuint) (ctx->Stencil.Clear & 0xff) |
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(R300_RB3D_ZS2_STENCIL_MASK <<
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(ZB_STENCILREFMASK_STENCILMASK_MASK <<
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R300_RB3D_ZS2_STENCIL_MASK_SHIFT) | ((ctx->Stencil.
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ZB_STENCILREFMASK_STENCILMASK_SHIFT) | ((ctx->Stencil.
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WriteMask[0] & 0xff) <<
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WriteMask[0] & 0xff) <<
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R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT));
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ZB_STENCILREFMASK_STENCILMASK_SHIFT));
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}
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}
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/* =============================================================
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/* =============================================================
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@ -1990,11 +1987,11 @@ static void r300ResetHwState(r300ContextPtr r300)
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if (r300->radeon.sarea->tiling_enabled) {
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if (r300->radeon.sarea->tiling_enabled) {
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/* XXX: Turn off when clearing buffers ? */
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/* XXX: Turn off when clearing buffers ? */
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r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTH_TILE_ENABLE;
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r300->hw.zb.cmd[R300_ZB_PITCH] |= ZB_DEPTHPITCH_DEPTHMACROTILE_ENABLE;
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if (ctx->Visual.depthBits == 24)
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if (ctx->Visual.depthBits == 24)
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r300->hw.zb.cmd[R300_ZB_PITCH] |=
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r300->hw.zb.cmd[R300_ZB_PITCH] |=
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R300_DEPTH_MICROTILE_ENABLE;
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ZB_DEPTHPITCH_DEPTHMICROTILE_TILED;
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}
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}
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r300->hw.zb_depthclearvalue.cmd[1] = 0;
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r300->hw.zb_depthclearvalue.cmd[1] = 0;
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@ -2182,12 +2179,12 @@ void r300InitState(r300ContextPtr r300)
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switch (ctx->Visual.depthBits) {
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switch (ctx->Visual.depthBits) {
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case 16:
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case 16:
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r300->state.depth.scale = 1.0 / (GLfloat) 0xffff;
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r300->state.depth.scale = 1.0 / (GLfloat) 0xffff;
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depth_fmt = R300_DEPTH_FORMAT_16BIT_INT_Z;
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depth_fmt = ZB_FORMAR_DEPTHFORMAT_16BIT_INT_Z;
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r300->state.stencil.clear = 0x00000000;
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r300->state.stencil.clear = 0x00000000;
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break;
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break;
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case 24:
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case 24:
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r300->state.depth.scale = 1.0 / (GLfloat) 0xffffff;
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r300->state.depth.scale = 1.0 / (GLfloat) 0xffffff;
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depth_fmt = R300_DEPTH_FORMAT_24BIT_INT_Z;
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depth_fmt = ZB_FORMAR_DEPTHFORMAT_24BIT_INT_Z;
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r300->state.stencil.clear = 0x00ff0000;
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r300->state.stencil.clear = 0x00ff0000;
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break;
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break;
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default:
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default:
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