mesa: update or remove out of date references to ir_to_mesa
Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14066>
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@ -128,5 +128,5 @@ Basic formatting guidelines
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prefer the use of ``bool``, ``true``, and ``false`` over
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prefer the use of ``bool``, ``true``, and ``false`` over
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``GLboolean``, ``GL_TRUE``, and ``GL_FALSE``. In C code, this may
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``GLboolean``, ``GL_TRUE``, and ``GL_FALSE``. In C code, this may
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mean that ``#include <stdbool.h>`` needs to be added. The
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mean that ``#include <stdbool.h>`` needs to be added. The
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``try_emit_*`` methods in ``src/mesa/program/ir_to_mesa.cpp`` and
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``try_emit_*`` method ``src/mesa/state_tracker/st_glsl_to_tgsi.cpp``
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``src/mesa/state_tracker/st_glsl_to_tgsi.cpp`` can serve as examples.
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can serve as an example.
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@ -155,9 +155,8 @@ for the 965 fragment shader backend when that is developed.
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Q: How should I expand instructions that take multiple backend instructions?
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Q: How should I expand instructions that take multiple backend instructions?
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Sometimes you'll have to do the expansion in your code generation --
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Sometimes you'll have to do the expansion in your code generation.
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see, for example, ir_to_mesa.cpp's handling of ir_unop_sqrt. However,
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However, in many cases you'll want to do a pass over the IR to convert
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in many cases you'll want to do a pass over the IR to convert
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non-native instructions to a series of native instructions. For
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non-native instructions to a series of native instructions. For
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example, for the Mesa backend we have ir_div_to_mul_rcp.cpp because
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example, for the Mesa backend we have ir_div_to_mul_rcp.cpp because
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Mesa IR (and many hardware backends) only have a reciprocal
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Mesa IR (and many hardware backends) only have a reciprocal
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@ -941,9 +941,6 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
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neg(op_expr[0]->operands[0]));
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neg(op_expr[0]->operands[0]));
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}
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}
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/* While ir_to_mesa.cpp will lower sqrt(x) to rcp(rsq(x)), it does so at
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* its IR level, so we can always apply this transformation.
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*/
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if (op_expr[0] && op_expr[0]->operation == ir_unop_rsq)
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if (op_expr[0] && op_expr[0]->operation == ir_unop_rsq)
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return sqrt(op_expr[0]->operands[0]);
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return sqrt(op_expr[0]->operands[0]);
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@ -218,9 +218,6 @@ st_nir_assign_uniform_locations(struct gl_context *ctx,
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}
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}
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} else if (uniform->state_slots) {
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} else if (uniform->state_slots) {
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const gl_state_index16 *const stateTokens = uniform->state_slots[0].tokens;
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const gl_state_index16 *const stateTokens = uniform->state_slots[0].tokens;
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/* This state reference has already been setup by ir_to_mesa, but we'll
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* get the same index back here.
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*/
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unsigned comps;
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unsigned comps;
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if (glsl_type_is_struct_or_ifc(type)) {
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if (glsl_type_is_struct_or_ifc(type)) {
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@ -5078,7 +5078,7 @@ get_src_arg_mask(st_dst_reg dst, st_src_reg src)
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* instruction is the first instruction to write to register T0. There are
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* instruction is the first instruction to write to register T0. There are
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* several lowering passes done in GLSL IR (e.g. branches and
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* several lowering passes done in GLSL IR (e.g. branches and
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* relative addressing) that create a large number of conditional assignments
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* relative addressing) that create a large number of conditional assignments
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* that ir_to_mesa converts to CMP instructions like the one mentioned above.
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* that glsl_to_tgsi converts to CMP instructions like the one mentioned above.
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*
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*
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* Here is why this conversion is safe:
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* Here is why this conversion is safe:
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* CMP T0, T1 T2 T0 can be expanded to:
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* CMP T0, T1 T2 T0 can be expanded to:
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