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i965/fs: Fix the FS inputs setup when some SF outputs aren't used in the FS. 

If there was an edge flag or a two-side-color pair present, we'd end up
mismatched and read values from earlier in the VUE for later FS inputs.

v2: Fix regression in gles2conform shaders generating point size. (change by
    anholt)

Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
NOTE: This is a candidate for the 8.0 branch.
This commit is contained in:
Olivier Galibert 2012-07-19 22:00:16 +02:00 committed by Eric Anholt
parent 3466538171
commit 7426d9d769
2 changed files with 25 additions and 2 deletions
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13
src/mesa/drivers/dri/i965/brw_fs.cpp
View File

@ -954,11 +954,22 @@ fs_visitor::calculate_urb_setup()
} else {
/* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
for (unsigned int i = 0; i < VERT_RESULT_MAX; i++) {
/* Point size is packed into the header, not as a general attribute */
if (i == VERT_RESULT_PSIZ)
continue;
if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
int fp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i);
/* The back color slot is skipped when the front color is
* also written to. In addition, some slots can be
* written in the vertex shader and not read in the
* fragment shader. So the register number must always be
* incremented, mapped or not.
*/
if (fp_index >= 0)
urb_setup[fp_index] = urb_next++;
urb_setup[fp_index] = urb_next;
urb_next++;
}
}

14
src/mesa/drivers/dri/i965/brw_wm_pass2.c
View File

@ -93,12 +93,24 @@ static void init_registers( struct brw_wm_compile *c )
}
} else {
for (j = 0; j < VERT_RESULT_MAX; j++) {
/* Point size is packed into the header, not as a general attribute */
if (j == VERT_RESULT_PSIZ)
continue;
if (c->key.vp_outputs_written & BITFIELD64_BIT(j)) {
int fp_index = _mesa_vert_result_to_frag_attrib(j);
nr_interp_regs++;
/* The back color slot is skipped when the front color is
* also written to. In addition, some slots can be
* written in the vertex shader and not read in the
* fragment shader. So the register number must always be
* incremented, mapped or not.
*/
if (fp_index >= 0)
prealloc_reg(c, &c->payload.input_interp[fp_index], i++);
prealloc_reg(c, &c->payload.input_interp[fp_index], i);
i++;
}
}
assert(nr_interp_regs >= 1);