i965: Enumerate Observability Architecture counters on Gen5+.
In addition to listing the counter names, we include several "remap" tables. Confusingly, counters are documented with names like "A23", are written to some buffer offset other than 23, and exposed by core Mesa under a counter ID that is different still. The first is inevitable; MI_REPORT_PERF_COUNT writes certain counters to fixed locations in the buffer. The latter could be avoided, but core Mesa uses the "Counters" array index as the ID for a counter. We could do remapping there, but it would just complicate the core Mesa code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke
parent
9f41585eb5
commit
7329f8dd10
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@ -1402,6 +1402,15 @@ struct brw_context
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struct {
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/** A map from pipeline statistics counter IDs to MMIO addresses. */
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const int *statistics_registers;
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/**
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* Mapping from a uint32_t offset within an OA snapshot to the ID of
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* the counter which MI_REPORT_PERF_COUNT stores there.
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*/
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const int *oa_snapshot_layout;
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/** Number of 32-bit entries in a hardware counter snapshot. */
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int entries_per_oa_snapshot;
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} perfmon;
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int num_atoms;
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@ -25,6 +25,21 @@
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* \file brw_performance_monitor.c
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*
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* Implementation of the GL_AMD_performance_monitor extension.
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*
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* On Gen5+ hardware, we have two sources of performance counter data:
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* the Observability Architecture counters (MI_REPORT_PERF_COUNT), and
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* the Pipeline Statistics Registers. We expose both sets of raw data,
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* as well as some useful processed values.
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*
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* The Observability Architecture (OA) counters for Gen6+ are documented
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* in a separate document from the rest of the PRMs. It is available at:
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* https://01.org/linuxgraphics/documentation/driver-documentation-prms
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* => 2013 Intel Core Processor Family => Observability Performance Counters
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* (This one volume covers Sandybridge, Ivybridge, Baytrail, and Haswell.)
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*
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* On Ironlake, the OA counters were called "CHAPS" counters. Sadly, no public
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* documentation exists; our implementation is based on the source code for the
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* intel_perf_counters utility (which is available as part of intel-gpu-tools).
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*/
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#include <limits.h>
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@ -100,14 +115,88 @@ brw_perf_monitor(struct gl_perf_monitor_object *m)
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/** Performance Monitor Group IDs */
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enum brw_counter_groups {
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OA_COUNTERS, /* Observability Architecture (MI_REPORT_PERF_COUNT) Counters */
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PIPELINE_STATS_COUNTERS, /* Pipeline Statistics Register Counters */
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};
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/**
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* Ironlake:
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* @{
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*
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* The list of CHAPS counters unfortunately does not appear in any public
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* documentation, but is available by reading the source code for the
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* intel_perf_counters utility (shipped as part of intel-gpu-tools).
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*/
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const static struct gl_perf_monitor_counter gen5_raw_chaps_counters[] = {
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COUNTER("cycles the CS unit is starved"),
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COUNTER("cycles the CS unit is stalled"),
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COUNTER("cycles the VF unit is starved"),
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COUNTER("cycles the VF unit is stalled"),
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COUNTER("cycles the VS unit is starved"),
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COUNTER("cycles the VS unit is stalled"),
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COUNTER("cycles the GS unit is starved"),
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COUNTER("cycles the GS unit is stalled"),
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COUNTER("cycles the CL unit is starved"),
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COUNTER("cycles the CL unit is stalled"),
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COUNTER("cycles the SF unit is starved"),
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COUNTER("cycles the SF unit is stalled"),
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COUNTER("cycles the WZ unit is starved"),
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COUNTER("cycles the WZ unit is stalled"),
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COUNTER("Z buffer read/write"),
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COUNTER("cycles each EU was active"),
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COUNTER("cycles each EU was suspended"),
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COUNTER("cycles threads loaded all EUs"),
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COUNTER("cycles filtering active"),
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COUNTER("cycles PS threads executed"),
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COUNTER("subspans written to RC"),
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COUNTER("bytes read for texture reads"),
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COUNTER("texels returned from sampler"),
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COUNTER("polygons not culled"),
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COUNTER("clocks MASF has valid message"),
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COUNTER("64b writes/reads from RC"),
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COUNTER("reads on dataport"),
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COUNTER("clocks MASF has valid msg not consumed by sampler"),
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COUNTER("cycles any EU is stalled for math"),
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};
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const static int gen5_oa_snapshot_layout[] =
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{
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-1, /* Report ID */
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-1, /* TIMESTAMP (64-bit) */
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-1, /* ...second half... */
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0, /* cycles the CS unit is starved */
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1, /* cycles the CS unit is stalled */
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2, /* cycles the VF unit is starved */
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3, /* cycles the VF unit is stalled */
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4, /* cycles the VS unit is starved */
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5, /* cycles the VS unit is stalled */
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6, /* cycles the GS unit is starved */
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7, /* cycles the GS unit is stalled */
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8, /* cycles the CL unit is starved */
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9, /* cycles the CL unit is stalled */
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10, /* cycles the SF unit is starved */
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11, /* cycles the SF unit is stalled */
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12, /* cycles the WZ unit is starved */
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13, /* cycles the WZ unit is stalled */
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14, /* Z buffer read/write */
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15, /* cycles each EU was active */
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16, /* cycles each EU was suspended */
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17, /* cycles threads loaded all EUs */
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18, /* cycles filtering active */
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19, /* cycles PS threads executed */
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20, /* subspans written to RC */
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21, /* bytes read for texture reads */
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22, /* texels returned from sampler */
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23, /* polygons not culled */
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24, /* clocks MASF has valid message */
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25, /* 64b writes/reads from RC */
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26, /* reads on dataport */
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27, /* clocks MASF has valid msg not consumed by sampler */
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28, /* cycles any EU is stalled for math */
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};
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const static struct gl_perf_monitor_group gen5_groups[] = {
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[OA_COUNTERS] = GROUP("CHAPS Counters", INT_MAX, gen5_raw_chaps_counters),
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/* Our pipeline statistics counter handling requires hardware contexts. */
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};
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/** @} */
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@ -115,7 +204,93 @@ const static struct gl_perf_monitor_group gen5_groups[] = {
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/**
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* Sandybridge:
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* @{
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*
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* A few of the counters here (A17-A20) are not included in the latest
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* documentation, but are described in the Ironlake PRM (which strangely
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* documents Sandybridge's performance counter system, not Ironlake's).
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* It's unclear whether they work or not; empirically, they appear to.
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*/
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/**
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* Aggregating counters A0-A28:
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*/
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const static struct gl_perf_monitor_counter gen6_raw_oa_counters[] = {
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/* A0: 0 */ COUNTER("Aggregated Core Array Active"),
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/* A1: 1 */ COUNTER("Aggregated Core Array Stalled"),
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/* A2: 2 */ COUNTER("Vertex Shader Active Time"),
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/* A3: Not actually hooked up on Sandybridge. */
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/* A4: 3 */ COUNTER("Vertex Shader Stall Time - Core Stall"),
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/* A5: 4 */ COUNTER("# VS threads loaded"),
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/* A6: 5 */ COUNTER("Vertex Shader Ready but not running Time"),
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/* A7: 6 */ COUNTER("Geometry Shader Active Time"),
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/* A8: Not actually hooked up on Sandybridge. */
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/* A9: 7 */ COUNTER("Geometry Shader Stall Time - Core Stall"),
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/* A10: 8 */ COUNTER("# GS threads loaded"),
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/* A11: 9 */ COUNTER("Geometry Shader Ready but not running Time"),
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/* A12: 10 */ COUNTER("Pixel Shader Active Time"),
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/* A13: Not actually hooked up on Sandybridge. */
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/* A14: 11 */ COUNTER("Pixel Shader Stall Time - Core Stall"),
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/* A15: 12 */ COUNTER("# PS threads loaded"),
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/* A16: 13 */ COUNTER("Pixel Shader Ready but not running Time"),
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/* A17: 14 */ COUNTER("Early Z Test Pixels Passing"),
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/* A18: 15 */ COUNTER("Early Z Test Pixels Failing"),
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/* A19: 16 */ COUNTER("Early Stencil Test Pixels Passing"),
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/* A20: 17 */ COUNTER("Early Stencil Test Pixels Failing"),
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/* A21: 18 */ COUNTER("Pixel Kill Count"),
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/* A22: 19 */ COUNTER("Alpha Test Pixels Failed"),
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/* A23: 20 */ COUNTER("Post PS Stencil Pixels Failed"),
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/* A24: 21 */ COUNTER("Post PS Z buffer Pixels Failed"),
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/* A25: 22 */ COUNTER("Pixels/samples Written in the frame buffer"),
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/* A26: 23 */ COUNTER("GPU Busy"),
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/* A27: 24 */ COUNTER("CL active and not stalled"),
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/* A28: 25 */ COUNTER("SF active and stalled"),
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};
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/**
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* Sandybridge: Counter Select = 001
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* A0 A1 A2 A3 A4 TIMESTAMP RPT_ID
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* A5 A6 A7 A8 A9 A10 A11 A12
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* A13 A14 A15 A16 A17 A18 A19 A20
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* A21 A22 A23 A24 A25 A26 A27 A28
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*
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* (Yes, this is a strange order.) We also have to remap for missing counters.
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*/
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const static int gen6_oa_snapshot_layout[] =
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{
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-1, /* Report ID */
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-1, /* TIMESTAMP (64-bit) */
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-1, /* ...second half... */
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3, /* A4: Vertex Shader Stall Time - Core Stall */
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-1, /* A3: (not available) */
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2, /* A2: Vertex Shader Active Time */
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1, /* A1: Aggregated Core Array Stalled */
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0, /* A0: Aggregated Core Array Active */
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10, /* A12: Pixel Shader Active Time */
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9, /* A11: Geometry Shader ready but not running Time */
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8, /* A10: # GS threads loaded */
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7, /* A9: Geometry Shader Stall Time - Core Stall */
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-1, /* A8: (not available) */
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6, /* A7: Geometry Shader Active Time */
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5, /* A6: Vertex Shader ready but not running Time */
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4, /* A5: # VS Threads Loaded */
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17, /* A20: Early Stencil Test Pixels Failing */
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16, /* A19: Early Stencil Test Pixels Passing */
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15, /* A18: Early Z Test Pixels Failing */
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14, /* A17: Early Z Test Pixels Passing */
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13, /* A16: Pixel Shader ready but not running Time */
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12, /* A15: # PS threads loaded */
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11, /* A14: Pixel Shader Stall Time - Core Stall */
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-1, /* A13: (not available) */
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25, /* A28: SF active and stalled */
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24, /* A27: CL active and not stalled */
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23, /* A26: GPU Busy */
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22, /* A25: Pixels/samples Written in the frame buffer */
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21, /* A24: Post PS Z buffer Pixels Failed */
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20, /* A23: Post PS Stencil Pixels Failed */
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19, /* A22: Alpha Test Pixels Failed */
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18, /* A21: Pixel Kill Count */
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};
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const static struct gl_perf_monitor_counter gen6_statistics_counters[] = {
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COUNTER64("IA_VERTICES_COUNT"),
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COUNTER64("IA_PRIMITIVES_COUNT"),
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@ -146,6 +321,7 @@ const static int gen6_statistics_register_addresses[] = {
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};
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const static struct gl_perf_monitor_group gen6_groups[] = {
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GROUP("Observability Architecture Counters", INT_MAX, gen6_raw_oa_counters),
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GROUP("Pipeline Statistics Registers", INT_MAX, gen6_statistics_counters),
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};
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/** @} */
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@ -154,6 +330,120 @@ const static struct gl_perf_monitor_group gen6_groups[] = {
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* Ivybridge/Baytrail/Haswell:
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* @{
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*/
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const static struct gl_perf_monitor_counter gen7_raw_oa_counters[] = {
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COUNTER("Aggregated Core Array Active"),
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COUNTER("Aggregated Core Array Stalled"),
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COUNTER("Vertex Shader Active Time"),
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COUNTER("Vertex Shader Stall Time - Core Stall"),
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COUNTER("# VS threads loaded"),
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COUNTER("Hull Shader Active Time"),
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COUNTER("Hull Shader Stall Time - Core Stall"),
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COUNTER("# HS threads loaded"),
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COUNTER("Domain Shader Active Time"),
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COUNTER("Domain Shader Stall Time - Core Stall"),
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COUNTER("# DS threads loaded"),
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COUNTER("Compute Shader Active Time"),
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COUNTER("Compute Shader Stall Time - Core Stall"),
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COUNTER("# CS threads loaded"),
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COUNTER("Geometry Shader Active Time"),
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COUNTER("Geometry Shader Stall Time - Core Stall"),
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COUNTER("# GS threads loaded"),
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COUNTER("Pixel Shader Active Time"),
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COUNTER("Pixel Shader Stall Time - Core Stall"),
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COUNTER("# PS threads loaded"),
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COUNTER("HiZ Fast Z Test Pixels Passing"),
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COUNTER("HiZ Fast Z Test Pixels Failing"),
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COUNTER("Slow Z Test Pixels Passing"),
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COUNTER("Slow Z Test Pixels Failing"),
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COUNTER("Pixel Kill Count"),
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COUNTER("Alpha Test Pixels Failed"),
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COUNTER("Post PS Stencil Pixels Failed"),
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COUNTER("Post PS Z buffer Pixels Failed"),
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COUNTER("3D/GPGPU Render Target Writes"),
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COUNTER("Render Engine Busy"),
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COUNTER("VS bottleneck"),
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COUNTER("GS bottleneck"),
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};
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/**
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* Ivybridge/Baytrail/Haswell: Counter Select = 101
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* A4 A3 A2 A1 A0 TIMESTAMP ReportID
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* A12 A11 A10 A9 A8 A7 A6 A5
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* A20 A19 A18 A17 A16 A15 A14 A13
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* A28 A27 A26 A25 A24 A23 A22 A21
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* A36 A35 A34 A33 A32 A31 A30 A29
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* A44 A43 A42 A41 A40 A39 A38 A37
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* B7 B6 B5 B4 B3 B2 B1 B0
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* Rsv Rsv Rsv Rsv Rsv Rsv Rsv Rsv
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*/
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const static int gen7_oa_snapshot_layout[] =
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{
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-1, /* Report ID */
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-1, /* TIMESTAMP (64-bit) */
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-1, /* ...second half... */
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0, /* A0: Aggregated Core Array Active */
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1, /* A1: Aggregated Core Array Stalled */
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2, /* A2: Vertex Shader Active Time */
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-1, /* A3: Reserved */
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3, /* A4: Vertex Shader Stall Time - Core Stall */
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4, /* A5: # VS threads loaded */
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-1, /* A6: Reserved */
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5, /* A7: Hull Shader Active Time */
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-1, /* A8: Reserved */
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6, /* A9: Hull Shader Stall Time - Core Stall */
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7, /* A10: # HS threads loaded */
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-1, /* A11: Reserved */
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8, /* A12: Domain Shader Active Time */
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-1, /* A13: Reserved */
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9, /* A14: Domain Shader Stall Time - Core Stall */
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10, /* A15: # DS threads loaded */
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-1, /* A16: Reserved */
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11, /* A17: Compute Shader Active Time */
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-1, /* A18: Reserved */
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12, /* A19: Compute Shader Stall Time - Core Stall */
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13, /* A20: # CS threads loaded */
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-1, /* A21: Reserved */
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14, /* A22: Geometry Shader Active Time */
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-1, /* A23: Reserved */
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15, /* A24: Geometry Shader Stall Time - Core Stall */
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16, /* A25: # GS threads loaded */
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-1, /* A26: Reserved */
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17, /* A27: Pixel Shader Active Time */
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-1, /* A28: Reserved */
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18, /* A29: Pixel Shader Stall Time - Core Stall */
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19, /* A30: # PS threads loaded */
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-1, /* A31: Reserved */
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20, /* A32: HiZ Fast Z Test Pixels Passing */
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21, /* A33: HiZ Fast Z Test Pixels Failing */
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22, /* A34: Slow Z Test Pixels Passing */
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23, /* A35: Slow Z Test Pixels Failing */
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24, /* A36: Pixel Kill Count */
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25, /* A37: Alpha Test Pixels Failed */
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26, /* A38: Post PS Stencil Pixels Failed */
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27, /* A39: Post PS Z buffer Pixels Failed */
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28, /* A40: 3D/GPGPU Render Target Writes */
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29, /* A41: Render Engine Busy */
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30, /* A42: VS bottleneck */
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31, /* A43: GS bottleneck */
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-1, /* A44: Reserved */
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-1, /* B0 */
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-1, /* B1 */
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-1, /* B2 */
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-1, /* B3 */
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-1, /* B4 */
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-1, /* B5 */
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-1, /* B6 */
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-1, /* B7 */
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-1, /* Reserved */
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-1, /* Reserved */
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-1, /* Reserved */
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-1, /* Reserved */
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-1, /* Reserved */
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-1, /* Reserved */
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-1, /* Reserved */
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-1, /* Reserved */
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};
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const static struct gl_perf_monitor_counter gen7_statistics_counters[] = {
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COUNTER64("IA_VERTICES_COUNT"),
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COUNTER64("IA_PRIMITIVES_COUNT"),
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@ -200,6 +490,7 @@ const static int gen7_statistics_register_addresses[] = {
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};
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const static struct gl_perf_monitor_group gen7_groups[] = {
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GROUP("Observability Architecture Counters", INT_MAX, gen7_raw_oa_counters),
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GROUP("Pipeline Statistics Registers", INT_MAX, gen7_statistics_counters),
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};
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/** @} */
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@ -481,13 +772,19 @@ brw_init_performance_monitors(struct brw_context *brw)
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if (brw->gen == 5) {
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ctx->PerfMonitor.Groups = gen5_groups;
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ctx->PerfMonitor.NumGroups = ARRAY_SIZE(gen5_groups);
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brw->perfmon.oa_snapshot_layout = gen5_oa_snapshot_layout;
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brw->perfmon.entries_per_oa_snapshot = ARRAY_SIZE(gen5_oa_snapshot_layout);
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} else if (brw->gen == 6) {
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ctx->PerfMonitor.Groups = gen6_groups;
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ctx->PerfMonitor.NumGroups = ARRAY_SIZE(gen6_groups);
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brw->perfmon.oa_snapshot_layout = gen6_oa_snapshot_layout;
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brw->perfmon.entries_per_oa_snapshot = ARRAY_SIZE(gen6_oa_snapshot_layout);
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brw->perfmon.statistics_registers = gen6_statistics_register_addresses;
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} else if (brw->gen == 7) {
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ctx->PerfMonitor.Groups = gen7_groups;
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ctx->PerfMonitor.NumGroups = ARRAY_SIZE(gen7_groups);
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brw->perfmon.oa_snapshot_layout = gen7_oa_snapshot_layout;
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brw->perfmon.entries_per_oa_snapshot = ARRAY_SIZE(gen7_oa_snapshot_layout);
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brw->perfmon.statistics_registers = gen7_statistics_register_addresses;
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}
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}
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