intel/compiler: Add unit tests for new EU validation checks
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
This commit is contained in:
Matt Turner
Marge Bot
parent
5f4eacaeda
commit
72cf63cfc6
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@ -23,6 +23,8 @@
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#include <gtest/gtest.h>
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#include "brw_eu.h"
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#include "brw_eu_defines.h"
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#include "util/bitset.h"
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#include "util/ralloc.h"
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static const struct gen_info {
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@ -188,6 +190,400 @@ TEST_P(validation_test, opcode46)
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}
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}
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TEST_P(validation_test, invalid_exec_size_encoding)
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{
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const struct {
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enum brw_execution_size exec_size;
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bool expected_result;
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} test_case[] = {
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{ BRW_EXECUTE_1, true },
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{ BRW_EXECUTE_2, true },
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{ BRW_EXECUTE_4, true },
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{ BRW_EXECUTE_8, true },
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{ BRW_EXECUTE_16, true },
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{ BRW_EXECUTE_32, true },
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{ (enum brw_execution_size)((int)BRW_EXECUTE_32 + 1), false },
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{ (enum brw_execution_size)((int)BRW_EXECUTE_32 + 2), false },
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};
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for (unsigned i = 0; i < ARRAY_SIZE(test_case); i++) {
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brw_MOV(p, g0, g0);
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brw_inst_set_exec_size(&devinfo, last_inst, test_case[i].exec_size);
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brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
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brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W);
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if (test_case[i].exec_size == BRW_EXECUTE_1) {
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brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
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brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1);
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brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
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} else {
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brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_2);
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brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_2);
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brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
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}
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EXPECT_EQ(test_case[i].expected_result, validate(p));
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clear_instructions(p);
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}
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}
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TEST_P(validation_test, invalid_file_encoding)
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{
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/* Register file on Gen12 is only one bit */
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if (devinfo.gen >= 12)
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return;
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brw_MOV(p, g0, g0);
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brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_MESSAGE_REGISTER_FILE, BRW_REGISTER_TYPE_F);
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if (devinfo.gen > 6) {
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EXPECT_FALSE(validate(p));
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} else {
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EXPECT_TRUE(validate(p));
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}
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clear_instructions(p);
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if (devinfo.gen < 6) {
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gen4_math(p, g0, BRW_MATH_FUNCTION_SIN, 0, g0, BRW_MATH_PRECISION_FULL);
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} else {
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gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null);
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}
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brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_MESSAGE_REGISTER_FILE, BRW_REGISTER_TYPE_F);
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if (devinfo.gen > 6) {
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EXPECT_FALSE(validate(p));
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} else {
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EXPECT_TRUE(validate(p));
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}
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}
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TEST_P(validation_test, invalid_type_encoding)
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{
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enum brw_reg_file files[2] = {
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BRW_GENERAL_REGISTER_FILE,
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BRW_IMMEDIATE_VALUE,
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};
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for (unsigned i = 0; i < ARRAY_SIZE(files); i++) {
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const enum brw_reg_file file = files[i];
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const int num_bits = devinfo.gen >= 8 ? 4 : 3;
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const int num_encodings = 1 << num_bits;
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/* The data types are encoded into <num_bits> bits to be used in hardware
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* instructions, so keep a record in a bitset the invalid patterns so
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* they can be verified to be invalid when used.
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*/
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BITSET_DECLARE(invalid_encodings, num_encodings);
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const struct {
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enum brw_reg_type type;
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bool expected_result;
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} test_case[] = {
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{ BRW_REGISTER_TYPE_NF, devinfo.gen == 11 && file != IMM },
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{ BRW_REGISTER_TYPE_DF, devinfo.has_64bit_float && (devinfo.gen >= 8 || file != IMM) },
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{ BRW_REGISTER_TYPE_F, true },
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{ BRW_REGISTER_TYPE_HF, devinfo.gen >= 8 },
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{ BRW_REGISTER_TYPE_VF, file == IMM },
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{ BRW_REGISTER_TYPE_Q, devinfo.has_64bit_int },
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{ BRW_REGISTER_TYPE_UQ, devinfo.has_64bit_int },
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{ BRW_REGISTER_TYPE_D, true },
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{ BRW_REGISTER_TYPE_UD, true },
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{ BRW_REGISTER_TYPE_W, true },
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{ BRW_REGISTER_TYPE_UW, true },
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{ BRW_REGISTER_TYPE_B, file == FIXED_GRF },
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{ BRW_REGISTER_TYPE_UB, file == FIXED_GRF },
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{ BRW_REGISTER_TYPE_V, file == IMM },
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{ BRW_REGISTER_TYPE_UV, devinfo.gen >= 6 && file == IMM },
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};
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/* Initially assume all hardware encodings are invalid */
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BITSET_ONES(invalid_encodings);
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brw_set_default_exec_size(p, BRW_EXECUTE_4);
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for (unsigned i = 0; i < ARRAY_SIZE(test_case); i++) {
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if (test_case[i].expected_result) {
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unsigned hw_type = brw_reg_type_to_hw_type(&devinfo, file, test_case[i].type);
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if (hw_type != INVALID_REG_TYPE) {
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/* ... and remove valid encodings from the set */
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assert(BITSET_TEST(invalid_encodings, hw_type));
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BITSET_CLEAR(invalid_encodings, hw_type);
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}
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if (file == FIXED_GRF) {
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struct brw_reg g = retype(g0, test_case[i].type);
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brw_MOV(p, g, g);
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brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
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brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
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brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
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} else {
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enum brw_reg_type t;
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switch (test_case[i].type) {
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case BRW_REGISTER_TYPE_V:
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t = BRW_REGISTER_TYPE_W;
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break;
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case BRW_REGISTER_TYPE_UV:
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t = BRW_REGISTER_TYPE_UW;
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break;
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case BRW_REGISTER_TYPE_VF:
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t = BRW_REGISTER_TYPE_F;
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break;
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default:
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t = test_case[i].type;
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break;
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}
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struct brw_reg g = retype(g0, t);
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brw_MOV(p, g, retype(brw_imm_w(0), test_case[i].type));
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}
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EXPECT_TRUE(validate(p));
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clear_instructions(p);
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}
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}
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/* The remaining encodings in invalid_encodings do not have a mapping
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* from BRW_REGISTER_TYPE_* and must be invalid. Verify that invalid
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* encodings are rejected by the validator.
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*/
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int e;
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BITSET_WORD tmp;
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BITSET_FOREACH_SET(e, tmp, invalid_encodings, num_encodings) {
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if (file == FIXED_GRF) {
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brw_MOV(p, g0, g0);
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brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
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brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
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brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
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} else {
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brw_MOV(p, g0, brw_imm_w(0));
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}
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brw_inst_set_dst_reg_hw_type(&devinfo, last_inst, e);
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brw_inst_set_src0_reg_hw_type(&devinfo, last_inst, e);
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EXPECT_FALSE(validate(p));
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clear_instructions(p);
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}
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}
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}
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TEST_P(validation_test, invalid_type_encoding_3src_a16)
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{
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/* 3-src instructions in align16 mode only supported on Gen6-10 */
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if (devinfo.gen < 6 || devinfo.gen > 10)
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return;
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const int num_bits = devinfo.gen >= 8 ? 3 : 2;
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const int num_encodings = 1 << num_bits;
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/* The data types are encoded into <num_bits> bits to be used in hardware
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* instructions, so keep a record in a bitset the invalid patterns so
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* they can be verified to be invalid when used.
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*/
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BITSET_DECLARE(invalid_encodings, num_encodings);
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const struct {
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enum brw_reg_type type;
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bool expected_result;
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} test_case[] = {
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{ BRW_REGISTER_TYPE_DF, devinfo.gen >= 7 },
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{ BRW_REGISTER_TYPE_F, true },
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{ BRW_REGISTER_TYPE_HF, devinfo.gen >= 8 },
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{ BRW_REGISTER_TYPE_D, devinfo.gen >= 7 },
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{ BRW_REGISTER_TYPE_UD, devinfo.gen >= 7 },
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};
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/* Initially assume all hardware encodings are invalid */
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BITSET_ONES(invalid_encodings);
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brw_set_default_access_mode(p, BRW_ALIGN_16);
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brw_set_default_exec_size(p, BRW_EXECUTE_4);
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for (unsigned i = 0; i < ARRAY_SIZE(test_case); i++) {
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if (test_case[i].expected_result) {
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unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(&devinfo, test_case[i].type);
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if (hw_type != INVALID_HW_REG_TYPE) {
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/* ... and remove valid encodings from the set */
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assert(BITSET_TEST(invalid_encodings, hw_type));
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BITSET_CLEAR(invalid_encodings, hw_type);
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}
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struct brw_reg g = retype(g0, test_case[i].type);
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if (!brw_reg_type_is_integer(test_case[i].type)) {
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brw_MAD(p, g, g, g, g);
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} else {
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brw_BFE(p, g, g, g, g);
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}
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EXPECT_TRUE(validate(p));
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clear_instructions(p);
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}
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}
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/* The remaining encodings in invalid_encodings do not have a mapping
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* from BRW_REGISTER_TYPE_* and must be invalid. Verify that invalid
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* encodings are rejected by the validator.
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*/
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int e;
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BITSET_WORD tmp;
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BITSET_FOREACH_SET(e, tmp, invalid_encodings, num_encodings) {
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for (unsigned i = 0; i < 2; i++) {
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if (i == 0) {
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brw_MAD(p, g0, g0, g0, g0);
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} else {
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brw_BFE(p, g0, g0, g0, g0);
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}
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brw_inst_set_3src_a16_dst_hw_type(&devinfo, last_inst, e);
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brw_inst_set_3src_a16_src_hw_type(&devinfo, last_inst, e);
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EXPECT_FALSE(validate(p));
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clear_instructions(p);
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if (devinfo.gen == 6)
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break;
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}
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}
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}
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TEST_P(validation_test, invalid_type_encoding_3src_a1)
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{
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/* 3-src instructions in align1 mode only supported on Gen10+ */
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if (devinfo.gen < 10)
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return;
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const int num_bits = 3 + 1 /* for exec_type */;
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const int num_encodings = 1 << num_bits;
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/* The data types are encoded into <num_bits> bits to be used in hardware
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* instructions, so keep a record in a bitset the invalid patterns so
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* they can be verified to be invalid when used.
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*/
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BITSET_DECLARE(invalid_encodings, num_encodings);
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const struct {
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enum brw_reg_type type;
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unsigned exec_type;
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bool expected_result;
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} test_case[] = {
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#define E(x) ((unsigned)BRW_ALIGN1_3SRC_EXEC_TYPE_##x)
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{ BRW_REGISTER_TYPE_NF, E(FLOAT), devinfo.gen == 11 },
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{ BRW_REGISTER_TYPE_DF, E(FLOAT), devinfo.has_64bit_float },
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{ BRW_REGISTER_TYPE_F, E(FLOAT), true },
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{ BRW_REGISTER_TYPE_HF, E(FLOAT), true },
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{ BRW_REGISTER_TYPE_D, E(INT), true },
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{ BRW_REGISTER_TYPE_UD, E(INT), true },
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{ BRW_REGISTER_TYPE_W, E(INT), true },
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{ BRW_REGISTER_TYPE_UW, E(INT), true },
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/* There are no ternary instructions that can operate on B-type sources
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* on Gen11-12. Src1/Src2 cannot be B-typed either.
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*/
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{ BRW_REGISTER_TYPE_B, E(INT), devinfo.gen == 10 },
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{ BRW_REGISTER_TYPE_UB, E(INT), devinfo.gen == 10 },
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};
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/* Initially assume all hardware encodings are invalid */
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BITSET_ONES(invalid_encodings);
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brw_set_default_access_mode(p, BRW_ALIGN_1);
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brw_set_default_exec_size(p, BRW_EXECUTE_4);
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for (unsigned i = 0; i < ARRAY_SIZE(test_case); i++) {
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if (test_case[i].expected_result) {
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unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(&devinfo, test_case[i].type);
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unsigned hw_exec_type = hw_type | (test_case[i].exec_type << 3);
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if (hw_type != INVALID_HW_REG_TYPE) {
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/* ... and remove valid encodings from the set */
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assert(BITSET_TEST(invalid_encodings, hw_exec_type));
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BITSET_CLEAR(invalid_encodings, hw_exec_type);
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}
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struct brw_reg g = retype(g0, test_case[i].type);
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if (!brw_reg_type_is_integer(test_case[i].type)) {
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brw_MAD(p, g, g, g, g);
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} else {
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brw_BFE(p, g, g, g, g);
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}
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EXPECT_TRUE(validate(p));
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clear_instructions(p);
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}
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}
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/* The remaining encodings in invalid_encodings do not have a mapping
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* from BRW_REGISTER_TYPE_* and must be invalid. Verify that invalid
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* encodings are rejected by the validator.
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*/
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int e;
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BITSET_WORD tmp;
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BITSET_FOREACH_SET(e, tmp, invalid_encodings, num_encodings) {
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const unsigned hw_type = e & 0x7;
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const unsigned exec_type = e >> 3;
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for (unsigned i = 0; i < 2; i++) {
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if (i == 0) {
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brw_MAD(p, g0, g0, g0, g0);
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brw_inst_set_3src_a1_exec_type(&devinfo, last_inst, BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT);
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} else {
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brw_CSEL(p, g0, g0, g0, g0);
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brw_inst_set_3src_cond_modifier(&devinfo, last_inst, BRW_CONDITIONAL_NZ);
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brw_inst_set_3src_a1_exec_type(&devinfo, last_inst, BRW_ALIGN1_3SRC_EXEC_TYPE_INT);
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}
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brw_inst_set_3src_a1_exec_type(&devinfo, last_inst, exec_type);
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brw_inst_set_3src_a1_dst_hw_type (&devinfo, last_inst, hw_type);
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brw_inst_set_3src_a1_src0_hw_type(&devinfo, last_inst, hw_type);
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brw_inst_set_3src_a1_src1_hw_type(&devinfo, last_inst, hw_type);
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brw_inst_set_3src_a1_src2_hw_type(&devinfo, last_inst, hw_type);
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EXPECT_FALSE(validate(p));
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clear_instructions(p);
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}
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}
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}
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TEST_P(validation_test, 3src_inst_access_mode)
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{
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/* 3-src instructions only supported on Gen6+ */
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if (devinfo.gen < 6)
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return;
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/* No access mode bit on Gen12+ */
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if (devinfo.gen >= 12)
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return;
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const struct {
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unsigned mode;
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bool expected_result;
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} test_case[] = {
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{ BRW_ALIGN_1, devinfo.gen >= 10 },
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{ BRW_ALIGN_16, devinfo.gen <= 10 },
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};
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for (unsigned i = 0; i < ARRAY_SIZE(test_case); i++) {
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if (devinfo.gen < 10)
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brw_set_default_access_mode(p, BRW_ALIGN_16);
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brw_MAD(p, g0, g0, g0, g0);
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brw_inst_set_access_mode(&devinfo, last_inst, test_case[i].mode);
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EXPECT_EQ(test_case[i].expected_result, validate(p));
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clear_instructions(p);
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}
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}
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/* When the Execution Data Type is wider than the destination data type, the
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* destination must [...] specify a HorzStride equal to the ratio in sizes of
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* the two data types.
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