nvfx: implement fp SSG properly
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parent
527a4f11a7
commit
72648ca51f
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@ -757,12 +757,25 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
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nvfx_fp_emit(fpc, arith(sat, SNE, dst, mask, src[0], src[1], none));
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break;
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case TGSI_OPCODE_SSG:
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tmp = nvfx_src(temp(fpc));
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tmp2 = nvfx_src(temp(fpc));
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nvfx_fp_emit(fpc, arith(0, SGT, tmp.reg, mask, src[0], nvfx_src(nvfx_reg(NVFXSR_CONST, 0)), none));
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nvfx_fp_emit(fpc, arith(0, SLT, tmp.reg, mask, src[0], nvfx_src(nvfx_reg(NVFXSR_CONST, 0)), none));
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nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, tmp, neg(tmp2), none));
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{
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float minonesv[4] = {-1.0, -1.0, -1.0, -1.0};
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struct nvfx_src minones = swz(nvfx_src(constant(fpc, -1, minonesv)), X, X, X, X);
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insn = arith(sat, MOV, dst, mask, src[0], none, none);
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insn.cc_update = 1;
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nvfx_fp_emit(fpc, insn);
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insn = arith(0, STR, dst, mask, none, none, none);
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insn.cc_test = NVFX_COND_GT;
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nvfx_fp_emit(fpc, insn);
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if(!sat) {
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insn = arith(0, MOV, dst, mask, minones, none, none);
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insn.cc_test = NVFX_COND_LT;
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nvfx_fp_emit(fpc, insn);
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}
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break;
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}
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case TGSI_OPCODE_STR:
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nvfx_fp_emit(fpc, arith(sat, STR, dst, mask, src[0], src[1], none));
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break;
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