radv: don't reset vertex state params on pipeline bind if reg layout matches
this is unnecessary since the locations will match Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8788>
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@ -4428,6 +4428,12 @@ void radv_CmdBindPipeline(
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return;
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radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
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bool vtx_emit_count_changed = !pipeline ||
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!cmd_buffer->state.pipeline ||
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cmd_buffer->state.pipeline->graphics.vtx_emit_num !=
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pipeline->graphics.vtx_emit_num ||
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cmd_buffer->state.pipeline->graphics.vtx_base_sgpr !=
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pipeline->graphics.vtx_base_sgpr;
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cmd_buffer->state.pipeline = pipeline;
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if (!pipeline)
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break;
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@ -4436,9 +4442,11 @@ void radv_CmdBindPipeline(
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cmd_buffer->push_constant_stages |= pipeline->active_stages;
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/* the new vertex shader might not have the same user regs */
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cmd_buffer->state.last_first_instance = -1;
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cmd_buffer->state.last_vertex_offset = -1;
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cmd_buffer->state.last_drawid = -1;
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if (vtx_emit_count_changed) {
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cmd_buffer->state.last_first_instance = -1;
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cmd_buffer->state.last_vertex_offset = -1;
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cmd_buffer->state.last_drawid = -1;
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}
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/* Prefetch all pipeline shaders at first draw time. */
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cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
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