radeonsi: use r600_common_context less pt1
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
This commit is contained in:
parent
0606190059
commit
71d9028b7a
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@ -46,6 +46,7 @@ void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
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struct r600_resource *resource,
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unsigned usage)
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{
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struct si_context *sctx = (struct si_context*)ctx;
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enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
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bool busy = false;
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@ -75,10 +76,10 @@ void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
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ctx->ws->cs_is_buffer_referenced(ctx->dma_cs,
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resource->buf, rusage)) {
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if (usage & PIPE_TRANSFER_DONTBLOCK) {
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si_flush_dma_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
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si_flush_dma_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
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return NULL;
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} else {
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si_flush_dma_cs(ctx, 0, NULL);
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si_flush_dma_cs(sctx, 0, NULL);
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busy = true;
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}
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}
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@ -79,7 +79,7 @@ static bool r600_resource_commit(struct pipe_context *pctx,
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unsigned level, struct pipe_box *box,
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bool commit)
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{
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struct r600_common_context *ctx = (struct r600_common_context *)pctx;
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struct si_context *ctx = (struct si_context *)pctx;
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struct r600_resource *res = r600_resource(resource);
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/*
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@ -89,23 +89,23 @@ static bool r600_resource_commit(struct pipe_context *pctx,
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* (b) wait for threaded submit to finish, including those that were
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* triggered by some other, earlier operation.
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*/
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if (radeon_emitted(ctx->gfx_cs, ctx->initial_gfx_cs_size) &&
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ctx->ws->cs_is_buffer_referenced(ctx->gfx_cs,
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res->buf, RADEON_USAGE_READWRITE)) {
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if (radeon_emitted(ctx->b.gfx_cs, ctx->b.initial_gfx_cs_size) &&
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ctx->b.ws->cs_is_buffer_referenced(ctx->b.gfx_cs,
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res->buf, RADEON_USAGE_READWRITE)) {
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si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
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}
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if (radeon_emitted(ctx->dma_cs, 0) &&
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ctx->ws->cs_is_buffer_referenced(ctx->dma_cs,
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res->buf, RADEON_USAGE_READWRITE)) {
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if (radeon_emitted(ctx->b.dma_cs, 0) &&
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ctx->b.ws->cs_is_buffer_referenced(ctx->b.dma_cs,
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res->buf, RADEON_USAGE_READWRITE)) {
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si_flush_dma_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
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}
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ctx->ws->cs_sync_flush(ctx->dma_cs);
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ctx->ws->cs_sync_flush(ctx->gfx_cs);
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ctx->b.ws->cs_sync_flush(ctx->b.dma_cs);
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ctx->b.ws->cs_sync_flush(ctx->b.gfx_cs);
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assert(resource->target == PIPE_BUFFER);
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return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
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return ctx->b.ws->buffer_commit(res->buf, box->x, box->width, commit);
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}
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bool si_common_context_init(struct r600_common_context *rctx,
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@ -175,7 +175,7 @@ bool si_common_context_init(struct r600_common_context *rctx,
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if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
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rctx->dma_cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
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si_flush_dma_cs,
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(void*)si_flush_dma_cs,
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rctx);
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}
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@ -47,7 +47,7 @@ static void cik_sdma_copy_buffer(struct si_context *ctx,
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src_offset += rsrc->gpu_address;
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ncopy = DIV_ROUND_UP(size, CIK_SDMA_COPY_MAX_SIZE);
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si_need_dma_space(&ctx->b, ncopy * 7, rdst, rsrc);
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si_need_dma_space(ctx, ncopy * 7, rdst, rsrc);
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for (i = 0; i < ncopy; i++) {
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csize = MIN2(size, CIK_SDMA_COPY_MAX_SIZE);
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@ -92,7 +92,7 @@ static void cik_sdma_clear_buffer(struct pipe_context *ctx,
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/* the same maximum size as for copying */
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ncopy = DIV_ROUND_UP(size, CIK_SDMA_COPY_MAX_SIZE);
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si_need_dma_space(&sctx->b, ncopy * 5, rdst, NULL);
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si_need_dma_space(sctx, ncopy * 5, rdst, NULL);
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for (i = 0; i < ncopy; i++) {
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csize = MIN2(size, CIK_SDMA_COPY_MAX_SIZE);
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@ -232,7 +232,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
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srcy + copy_height != (1 << 14)))) {
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struct radeon_winsys_cs *cs = sctx->b.dma_cs;
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si_need_dma_space(&sctx->b, 13, &rdst->resource, &rsrc->resource);
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si_need_dma_space(sctx, 13, &rdst->resource, &rsrc->resource);
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radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
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CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
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@ -395,7 +395,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
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struct radeon_winsys_cs *cs = sctx->b.dma_cs;
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uint32_t direction = linear == rdst ? 1u << 31 : 0;
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si_need_dma_space(&sctx->b, 14, &rdst->resource, &rsrc->resource);
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si_need_dma_space(sctx, 14, &rdst->resource, &rsrc->resource);
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radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
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CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
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@ -489,7 +489,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
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dstx + copy_width != (1 << 14)))) {
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struct radeon_winsys_cs *cs = sctx->b.dma_cs;
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si_need_dma_space(&sctx->b, 15, &rdst->resource, &rsrc->resource);
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si_need_dma_space(sctx, 15, &rdst->resource, &rsrc->resource);
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radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
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CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0));
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@ -1108,10 +1108,9 @@ static void si_dump_dma(struct si_context *sctx,
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fprintf(f, "SDMA Dump Done.\n");
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}
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void si_check_vm_faults(struct r600_common_context *ctx,
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void si_check_vm_faults(struct si_context *sctx,
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struct radeon_saved_cs *saved, enum ring_type ring)
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct pipe_screen *screen = sctx->b.b.screen;
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FILE *f;
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uint64_t addr;
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@ -59,7 +59,7 @@ static void si_dma_copy_buffer(struct si_context *ctx,
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}
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ncopy = DIV_ROUND_UP(size, max_size);
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si_need_dma_space(&ctx->b, ncopy * 5, rdst, rsrc);
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si_need_dma_space(ctx, ncopy * 5, rdst, rsrc);
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for (i = 0; i < ncopy; i++) {
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count = MIN2(size, max_size);
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@ -101,7 +101,7 @@ static void si_dma_clear_buffer(struct pipe_context *ctx,
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/* the same maximum size as for copying */
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ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
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si_need_dma_space(&sctx->b, ncopy * 4, rdst, NULL);
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si_need_dma_space(sctx, ncopy * 4, rdst, NULL);
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for (i = 0; i < ncopy; i++) {
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csize = MIN2(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
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@ -190,7 +190,7 @@ static void si_dma_copy_tile(struct si_context *ctx,
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mt = G_009910_MICRO_TILE_MODE(tile_mode);
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size = copy_height * pitch;
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ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
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si_need_dma_space(&ctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
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si_need_dma_space(ctx, ncopy * 9, &rdst->resource, &rsrc->resource);
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for (i = 0; i < ncopy; i++) {
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cheight = copy_height;
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@ -24,22 +24,22 @@
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#include "si_pipe.h"
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#include "radeon/r600_cs.h"
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static void si_dma_emit_wait_idle(struct r600_common_context *rctx)
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static void si_dma_emit_wait_idle(struct si_context *sctx)
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{
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struct radeon_winsys_cs *cs = rctx->dma_cs;
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struct radeon_winsys_cs *cs = sctx->b.dma_cs;
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/* NOP waits for idle on Evergreen and later. */
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if (rctx->chip_class >= CIK)
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if (sctx->b.chip_class >= CIK)
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radeon_emit(cs, 0x00000000); /* NOP */
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else
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radeon_emit(cs, 0xf0000000); /* NOP */
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}
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void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
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void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
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struct r600_resource *dst, struct r600_resource *src)
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{
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uint64_t vram = ctx->dma_cs->used_vram;
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uint64_t gtt = ctx->dma_cs->used_gart;
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uint64_t vram = ctx->b.dma_cs->used_vram;
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uint64_t gtt = ctx->b.dma_cs->used_gart;
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if (dst) {
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vram += dst->vram_usage;
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@ -51,13 +51,13 @@ void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
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}
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/* Flush the GFX IB if DMA depends on it. */
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if (radeon_emitted(ctx->gfx_cs, ctx->initial_gfx_cs_size) &&
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if (radeon_emitted(ctx->b.gfx_cs, ctx->b.initial_gfx_cs_size) &&
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((dst &&
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ctx->ws->cs_is_buffer_referenced(ctx->gfx_cs, dst->buf,
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RADEON_USAGE_READWRITE)) ||
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ctx->b.ws->cs_is_buffer_referenced(ctx->b.gfx_cs, dst->buf,
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RADEON_USAGE_READWRITE)) ||
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(src &&
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ctx->ws->cs_is_buffer_referenced(ctx->gfx_cs, src->buf,
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RADEON_USAGE_WRITE))))
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ctx->b.ws->cs_is_buffer_referenced(ctx->b.gfx_cs, src->buf,
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RADEON_USAGE_WRITE))))
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si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
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/* Flush if there's not enough space, or if the memory usage per IB
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@ -73,66 +73,66 @@ void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
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* engine busy while uploads are being submitted.
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*/
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num_dw++; /* for emit_wait_idle below */
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if (!ctx->ws->cs_check_space(ctx->dma_cs, num_dw) ||
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ctx->dma_cs->used_vram + ctx->dma_cs->used_gart > 64 * 1024 * 1024 ||
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!radeon_cs_memory_below_limit(ctx->screen, ctx->dma_cs, vram, gtt)) {
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if (!ctx->b.ws->cs_check_space(ctx->b.dma_cs, num_dw) ||
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ctx->b.dma_cs->used_vram + ctx->b.dma_cs->used_gart > 64 * 1024 * 1024 ||
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!radeon_cs_memory_below_limit(ctx->screen, ctx->b.dma_cs, vram, gtt)) {
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si_flush_dma_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
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assert((num_dw + ctx->dma_cs->current.cdw) <= ctx->dma_cs->current.max_dw);
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assert((num_dw + ctx->b.dma_cs->current.cdw) <= ctx->b.dma_cs->current.max_dw);
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}
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/* Wait for idle if either buffer has been used in the IB before to
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* prevent read-after-write hazards.
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*/
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if ((dst &&
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ctx->ws->cs_is_buffer_referenced(ctx->dma_cs, dst->buf,
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RADEON_USAGE_READWRITE)) ||
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ctx->b.ws->cs_is_buffer_referenced(ctx->b.dma_cs, dst->buf,
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RADEON_USAGE_READWRITE)) ||
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(src &&
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ctx->ws->cs_is_buffer_referenced(ctx->dma_cs, src->buf,
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RADEON_USAGE_WRITE)))
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ctx->b.ws->cs_is_buffer_referenced(ctx->b.dma_cs, src->buf,
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RADEON_USAGE_WRITE)))
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si_dma_emit_wait_idle(ctx);
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if (dst) {
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radeon_add_to_buffer_list(ctx, ctx->dma_cs, dst,
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radeon_add_to_buffer_list(&ctx->b, ctx->b.dma_cs, dst,
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RADEON_USAGE_WRITE,
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RADEON_PRIO_SDMA_BUFFER);
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}
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if (src) {
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radeon_add_to_buffer_list(ctx, ctx->dma_cs, src,
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radeon_add_to_buffer_list(&ctx->b, ctx->b.dma_cs, src,
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RADEON_USAGE_READ,
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RADEON_PRIO_SDMA_BUFFER);
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}
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/* this function is called before all DMA calls, so increment this. */
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ctx->num_dma_calls++;
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ctx->b.num_dma_calls++;
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}
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void si_flush_dma_cs(void *ctx, unsigned flags, struct pipe_fence_handle **fence)
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void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
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struct pipe_fence_handle **fence)
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{
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struct r600_common_context *rctx = (struct r600_common_context *)ctx;
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struct radeon_winsys_cs *cs = rctx->dma_cs;
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struct radeon_winsys_cs *cs = ctx->b.dma_cs;
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struct radeon_saved_cs saved;
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bool check_vm = (rctx->screen->debug_flags & DBG(CHECK_VM));
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bool check_vm = (ctx->screen->debug_flags & DBG(CHECK_VM)) != 0;
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if (!radeon_emitted(cs, 0)) {
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if (fence)
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rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
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ctx->b.ws->fence_reference(fence, ctx->b.last_sdma_fence);
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return;
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}
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if (check_vm)
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si_save_cs(rctx->ws, cs, &saved, true);
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si_save_cs(ctx->b.ws, cs, &saved, true);
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rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
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ctx->b.ws->cs_flush(cs, flags, &ctx->b.last_sdma_fence);
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if (fence)
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rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
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ctx->b.ws->fence_reference(fence, ctx->b.last_sdma_fence);
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if (check_vm) {
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/* Use conservative timeout 800ms, after which we won't wait any
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* longer and assume the GPU is hung.
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*/
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rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
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ctx->b.ws->fence_wait(ctx->b.ws, ctx->b.last_sdma_fence, 800*1000*1000);
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si_check_vm_faults(rctx, &saved, RING_DMA);
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si_check_vm_faults(ctx, &saved, RING_DMA);
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si_clear_saved_cs(&saved);
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}
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}
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@ -140,10 +140,10 @@ void si_flush_dma_cs(void *ctx, unsigned flags, struct pipe_fence_handle **fence
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void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
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uint64_t offset, uint64_t size, unsigned value)
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{
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struct r600_common_context *rctx = (struct r600_common_context*)sscreen->aux_context;
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struct si_context *ctx = (struct si_context*)sscreen->aux_context;
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mtx_lock(&sscreen->aux_context_lock);
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rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
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ctx->b.dma_clear_buffer(&ctx->b.b, dst, offset, size, value);
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sscreen->aux_context->flush(sscreen->aux_context, NULL, 0);
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mtx_unlock(&sscreen->aux_context_lock);
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}
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@ -46,7 +46,7 @@ struct si_multi_fence {
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/* If the context wasn't flushed at fence creation, this is non-NULL. */
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struct {
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struct r600_common_context *ctx;
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struct si_context *ctx;
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unsigned ib_index;
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} gfx_unflushed;
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@ -174,14 +174,14 @@ void si_gfx_wait_fence(struct r600_common_context *ctx,
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radeon_emit(cs, 4); /* poll interval */
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}
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static void si_add_fence_dependency(struct r600_common_context *rctx,
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static void si_add_fence_dependency(struct si_context *sctx,
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struct pipe_fence_handle *fence)
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{
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struct radeon_winsys *ws = rctx->ws;
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struct radeon_winsys *ws = sctx->b.ws;
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if (rctx->dma_cs)
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ws->cs_add_fence_dependency(rctx->dma_cs, fence);
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ws->cs_add_fence_dependency(rctx->gfx_cs, fence);
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if (sctx->b.dma_cs)
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ws->cs_add_fence_dependency(sctx->b.dma_cs, fence);
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ws->cs_add_fence_dependency(sctx->b.gfx_cs, fence);
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}
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static void si_add_syncobj_signal(struct r600_common_context *rctx,
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@ -351,7 +351,7 @@ static boolean si_fence_finish(struct pipe_screen *screen,
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struct si_context *sctx;
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sctx = (struct si_context *)threaded_context_unwrap_unsync(ctx);
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if (rfence->gfx_unflushed.ctx == &sctx->b &&
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if (rfence->gfx_unflushed.ctx == sctx &&
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rfence->gfx_unflushed.ib_index == sctx->b.num_gfx_cs_flushes) {
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/* Section 4.1.2 (Signaling) of the OpenGL 4.6 (Core profile)
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* spec says:
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@ -496,8 +496,8 @@ static void si_flush_from_st(struct pipe_context *ctx,
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unsigned flags)
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{
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struct pipe_screen *screen = ctx->screen;
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struct r600_common_context *rctx = (struct r600_common_context *)ctx;
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struct radeon_winsys *ws = rctx->ws;
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struct si_context *sctx = (struct si_context *)ctx;
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struct radeon_winsys *ws = sctx->b.ws;
|
||||
struct pipe_fence_handle *gfx_fence = NULL;
|
||||
struct pipe_fence_handle *sdma_fence = NULL;
|
||||
bool deferred_fence = false;
|
||||
|
@ -511,18 +511,18 @@ static void si_flush_from_st(struct pipe_context *ctx,
|
|||
assert(flags & PIPE_FLUSH_DEFERRED);
|
||||
assert(fence);
|
||||
|
||||
si_fine_fence_set((struct si_context *)rctx, &fine, flags);
|
||||
si_fine_fence_set(sctx, &fine, flags);
|
||||
}
|
||||
|
||||
/* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
|
||||
if (rctx->dma_cs)
|
||||
si_flush_dma_cs(rctx, rflags, fence ? &sdma_fence : NULL);
|
||||
if (sctx->b.dma_cs)
|
||||
si_flush_dma_cs(sctx, rflags, fence ? &sdma_fence : NULL);
|
||||
|
||||
if (!radeon_emitted(rctx->gfx_cs, rctx->initial_gfx_cs_size)) {
|
||||
if (!radeon_emitted(sctx->b.gfx_cs, sctx->b.initial_gfx_cs_size)) {
|
||||
if (fence)
|
||||
ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
|
||||
ws->fence_reference(&gfx_fence, sctx->b.last_gfx_fence);
|
||||
if (!(flags & PIPE_FLUSH_DEFERRED))
|
||||
ws->cs_sync_flush(rctx->gfx_cs);
|
||||
ws->cs_sync_flush(sctx->b.gfx_cs);
|
||||
} else {
|
||||
/* Instead of flushing, create a deferred fence. Constraints:
|
||||
* - The state tracker must allow a deferred flush.
|
||||
|
@ -533,10 +533,10 @@ static void si_flush_from_st(struct pipe_context *ctx,
|
|||
if (flags & PIPE_FLUSH_DEFERRED &&
|
||||
!(flags & PIPE_FLUSH_FENCE_FD) &&
|
||||
fence) {
|
||||
gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx_cs);
|
||||
gfx_fence = sctx->b.ws->cs_get_next_fence(sctx->b.gfx_cs);
|
||||
deferred_fence = true;
|
||||
} else {
|
||||
si_flush_gfx_cs(rctx, rflags, fence ? &gfx_fence : NULL);
|
||||
si_flush_gfx_cs(sctx, rflags, fence ? &gfx_fence : NULL);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -564,8 +564,8 @@ static void si_flush_from_st(struct pipe_context *ctx,
|
|||
multi_fence->sdma = sdma_fence;
|
||||
|
||||
if (deferred_fence) {
|
||||
multi_fence->gfx_unflushed.ctx = rctx;
|
||||
multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
|
||||
multi_fence->gfx_unflushed.ctx = sctx;
|
||||
multi_fence->gfx_unflushed.ib_index = sctx->b.num_gfx_cs_flushes;
|
||||
}
|
||||
|
||||
multi_fence->fine = fine;
|
||||
|
@ -579,9 +579,9 @@ static void si_flush_from_st(struct pipe_context *ctx,
|
|||
assert(!fine.buf);
|
||||
finish:
|
||||
if (!(flags & PIPE_FLUSH_DEFERRED)) {
|
||||
if (rctx->dma_cs)
|
||||
ws->cs_sync_flush(rctx->dma_cs);
|
||||
ws->cs_sync_flush(rctx->gfx_cs);
|
||||
if (sctx->b.dma_cs)
|
||||
ws->cs_sync_flush(sctx->b.dma_cs);
|
||||
ws->cs_sync_flush(sctx->b.gfx_cs);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -615,14 +615,14 @@ static void si_fence_server_signal(struct pipe_context *ctx,
|
|||
static void si_fence_server_sync(struct pipe_context *ctx,
|
||||
struct pipe_fence_handle *fence)
|
||||
{
|
||||
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
|
||||
struct si_context *sctx = (struct si_context *)ctx;
|
||||
struct si_multi_fence *rfence = (struct si_multi_fence *)fence;
|
||||
|
||||
util_queue_fence_wait(&rfence->ready);
|
||||
|
||||
/* Unflushed fences from the same context are no-ops. */
|
||||
if (rfence->gfx_unflushed.ctx &&
|
||||
rfence->gfx_unflushed.ctx == rctx)
|
||||
rfence->gfx_unflushed.ctx == sctx)
|
||||
return;
|
||||
|
||||
/* All unflushed commands will not start execution before
|
||||
|
@ -633,9 +633,9 @@ static void si_fence_server_sync(struct pipe_context *ctx,
|
|||
si_flush_from_st(ctx, NULL, PIPE_FLUSH_ASYNC);
|
||||
|
||||
if (rfence->sdma)
|
||||
si_add_fence_dependency(rctx, rfence->sdma);
|
||||
si_add_fence_dependency(sctx, rfence->sdma);
|
||||
if (rfence->gfx)
|
||||
si_add_fence_dependency(rctx, rfence->gfx);
|
||||
si_add_fence_dependency(sctx, rfence->gfx);
|
||||
}
|
||||
|
||||
void si_init_fence_functions(struct si_context *ctx)
|
||||
|
|
|
@ -139,7 +139,7 @@ void si_flush_gfx_cs(void *context, unsigned flags,
|
|||
*/
|
||||
ctx->b.ws->fence_wait(ctx->b.ws, ctx->b.last_gfx_fence, 800*1000*1000);
|
||||
|
||||
si_check_vm_faults(&ctx->b, &ctx->current_saved_cs->gfx, RING_GFX);
|
||||
si_check_vm_faults(ctx, &ctx->current_saved_cs->gfx, RING_GFX);
|
||||
}
|
||||
|
||||
if (ctx->current_saved_cs)
|
||||
|
|
|
@ -714,7 +714,7 @@ void si_log_hw_flush(struct si_context *sctx);
|
|||
void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
|
||||
void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
|
||||
void si_init_debug_functions(struct si_context *sctx);
|
||||
void si_check_vm_faults(struct r600_common_context *ctx,
|
||||
void si_check_vm_faults(struct si_context *sctx,
|
||||
struct radeon_saved_cs *saved, enum ring_type ring);
|
||||
bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
|
||||
|
||||
|
@ -722,9 +722,10 @@ bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
|
|||
void si_init_dma_functions(struct si_context *sctx);
|
||||
|
||||
/* si_dma_cs.c */
|
||||
void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
|
||||
void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
|
||||
struct r600_resource *dst, struct r600_resource *src);
|
||||
void si_flush_dma_cs(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
|
||||
void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
|
||||
struct pipe_fence_handle **fence);
|
||||
void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
|
||||
uint64_t offset, uint64_t size, unsigned value);
|
||||
|
||||
|
|
Loading…
Reference in New Issue