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radeon: switch to 3-spaces style 

For clang-format config see the previous commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
This commit is contained in:
Pierre-Eric Pelloux-Prayer 2020-03-27 20:42:29 +01:00 committed by Marge Bot
parent d7008fe46a
commit 716a065ac0
21 changed files with 8125 additions and 8441 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/gallium/drivers/radeon/.editorconfig
View File

@ -1,2 +0,0 @@
[*.{c,h}]
indent_style = tab

192
src/gallium/drivers/radeon/radeon_uvd.c
View File

@ -25,23 +25,21 @@
*
**************************************************************************/
#include <sys/types.h>
#include <assert.h>
#include <errno.h>
#include <unistd.h>
#include <stdio.h>
#include "radeon_uvd.h"
#include "pipe/p_video_codec.h"
#include "radeon_video.h"
#include "radeonsi/si_pipe.h"
#include "util/u_memory.h"
#include "util/u_video.h"
#include "vl/vl_defines.h"
#include "vl/vl_mpeg12_decoder.h"
#include <sys/types.h>
#include "radeonsi/si_pipe.h"
#include "radeon_video.h"
#include "radeon_uvd.h"
#include <assert.h>
#include <errno.h>
#include <stdio.h>
#include <unistd.h>
#define NUM_BUFFERS 4
@ -109,14 +107,12 @@ static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val)
}
/* send a command to the VCPU through the GPCOM registers */
static void send_cmd(struct ruvd_decoder *dec, unsigned cmd,
struct pb_buffer* buf, uint32_t off,
static void send_cmd(struct ruvd_decoder *dec, unsigned cmd, struct pb_buffer *buf, uint32_t off,
enum radeon_bo_usage usage, enum radeon_bo_domain domain)
{
int reloc_idx;
reloc_idx = dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
domain, 0);
reloc_idx = dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
if (!dec->use_legacy) {
uint64_t addr;
addr = dec->ws->buffer_get_virtual_address(buf);
@ -134,8 +130,7 @@ static void send_cmd(struct ruvd_decoder *dec, unsigned cmd,
/* do the codec needs an IT buffer ?*/
static bool have_it(struct ruvd_decoder *dec)
{
return dec->stream_type == RUVD_CODEC_H264_PERF ||
dec->stream_type == RUVD_CODEC_H265;
return dec->stream_type == RUVD_CODEC_H264_PERF || dec->stream_type == RUVD_CODEC_H265;
}
/* map the next available message/feedback/itscaling buffer */
@ -148,8 +143,8 @@ static void map_msg_fb_it_buf(struct ruvd_decoder *dec)
buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
/* and map it for CPU access */
ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
ptr =
dec->ws->buffer_map(buf->res->buf, dec->cs, PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
/* calc buffer offsets */
dec->msg = (struct ruvd_msg *)ptr;
@ -178,15 +173,12 @@ static void send_msg_buf(struct ruvd_decoder *dec)
dec->fb = NULL;
dec->it = NULL;
if (dec->sessionctx.res)
send_cmd(dec, RUVD_CMD_SESSION_CONTEXT_BUFFER,
dec->sessionctx.res->buf, 0, RADEON_USAGE_READWRITE,
RADEON_DOMAIN_VRAM);
send_cmd(dec, RUVD_CMD_SESSION_CONTEXT_BUFFER, dec->sessionctx.res->buf, 0,
RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
/* and send it to the hardware */
send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->res->buf, 0,
RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
}
/* cycle to the next set of buffers */
@ -201,8 +193,7 @@ static uint32_t profile2stream_type(struct ruvd_decoder *dec, unsigned family)
{
switch (u_reduce_video_profile(dec->base.profile)) {
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
return (family >= CHIP_TONGA) ?
RUVD_CODEC_H264_PERF : RUVD_CODEC_H264;
return (family >= CHIP_TONGA) ? RUVD_CODEC_H264_PERF : RUVD_CODEC_H264;
case PIPE_VIDEO_FORMAT_VC1:
return RUVD_CODEC_VC1;
@ -296,7 +287,8 @@ static unsigned calc_ctx_size_h265_main(struct ruvd_decoder *dec)
return ((width + 255) / 16) * ((height + 255) / 16) * 16 * max_references + 52 * 1024;
}
static unsigned calc_ctx_size_h265_main10(struct ruvd_decoder *dec, struct pipe_h265_picture_desc *pic)
static unsigned calc_ctx_size_h265_main10(struct ruvd_decoder *dec,
struct pipe_h265_picture_desc *pic)
{
unsigned log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
@ -304,7 +296,8 @@ static unsigned calc_ctx_size_h265_main10(struct ruvd_decoder *dec, struct pipe_
unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
unsigned coeff_10bit = (pic->pps->sps->bit_depth_luma_minus8 || pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
unsigned coeff_10bit =
(pic->pps->sps->bit_depth_luma_minus8 || pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
unsigned max_references = dec->base.max_references + 1;
@ -425,9 +418,11 @@ static unsigned calc_dpb_size(struct ruvd_decoder *dec)
width = align(width, 16);
height = align(height, 16);
if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
dpb_size = align((align(width, get_db_pitch_alignment(dec)) * height * 9) / 4, 256) * max_references;
dpb_size = align((align(width, get_db_pitch_alignment(dec)) * height * 9) / 4, 256) *
max_references;
else
dpb_size = align((align(width, get_db_pitch_alignment(dec)) * height * 3) / 2, 256) * max_references;
dpb_size = align((align(width, get_db_pitch_alignment(dec)) * height * 3) / 2, 256) *
max_references;
break;
case PIPE_VIDEO_FORMAT_VC1:
@ -616,16 +611,22 @@ static struct ruvd_h265 get_h265_msg(struct ruvd_decoder *dec, struct pipe_video
result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
result.sps_max_dec_pic_buffering_minus1 = pic->pps->sps->sps_max_dec_pic_buffering_minus1;
result.log2_min_luma_coding_block_size_minus3 = pic->pps->sps->log2_min_luma_coding_block_size_minus3;
result.log2_diff_max_min_luma_coding_block_size = pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
result.log2_min_transform_block_size_minus2 = pic->pps->sps->log2_min_transform_block_size_minus2;
result.log2_diff_max_min_transform_block_size = pic->pps->sps->log2_diff_max_min_transform_block_size;
result.log2_min_luma_coding_block_size_minus3 =
pic->pps->sps->log2_min_luma_coding_block_size_minus3;
result.log2_diff_max_min_luma_coding_block_size =
pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
result.log2_min_transform_block_size_minus2 =
pic->pps->sps->log2_min_transform_block_size_minus2;
result.log2_diff_max_min_transform_block_size =
pic->pps->sps->log2_diff_max_min_transform_block_size;
result.max_transform_hierarchy_depth_inter = pic->pps->sps->max_transform_hierarchy_depth_inter;
result.max_transform_hierarchy_depth_intra = pic->pps->sps->max_transform_hierarchy_depth_intra;
result.pcm_sample_bit_depth_luma_minus1 = pic->pps->sps->pcm_sample_bit_depth_luma_minus1;
result.pcm_sample_bit_depth_chroma_minus1 = pic->pps->sps->pcm_sample_bit_depth_chroma_minus1;
result.log2_min_pcm_luma_coding_block_size_minus3 = pic->pps->sps->log2_min_pcm_luma_coding_block_size_minus3;
result.log2_diff_max_min_pcm_luma_coding_block_size = pic->pps->sps->log2_diff_max_min_pcm_luma_coding_block_size;
result.log2_min_pcm_luma_coding_block_size_minus3 =
pic->pps->sps->log2_min_pcm_luma_coding_block_size_minus3;
result.log2_diff_max_min_pcm_luma_coding_block_size =
pic->pps->sps->log2_diff_max_min_pcm_luma_coding_block_size;
result.num_short_term_ref_pic_sets = pic->pps->sps->num_short_term_ref_pic_sets;
result.pps_info_flags = 0;
@ -692,8 +693,7 @@ static struct ruvd_h265 get_h265_msg(struct ruvd_decoder *dec, struct pipe_video
}
}
vl_video_buffer_set_associated_data(target, &dec->base,
(void *)(uintptr_t)result.curr_idx,
vl_video_buffer_set_associated_data(target, &dec->base, (void *)(uintptr_t)result.curr_idx,
&ruvd_destroy_associated_data);
for (i = 0; i < 16; ++i) {
@ -741,8 +741,7 @@ static struct ruvd_h265 get_h265_msg(struct ruvd_decoder *dec, struct pipe_video
}
if (pic->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
if (target->buffer_format == PIPE_FORMAT_P010 ||
target->buffer_format == PIPE_FORMAT_P016) {
if (target->buffer_format == PIPE_FORMAT_P010 || target->buffer_format == PIPE_FORMAT_P016) {
result.p010_mode = 1;
result.msb_mode = 1;
} else {
@ -1001,8 +1000,7 @@ static void ruvd_destroy(struct pipe_video_codec *decoder)
/**
* start decoding of a new frame
*/
static void ruvd_begin_frame(struct pipe_video_codec *decoder,
struct pipe_video_buffer *target,
static void ruvd_begin_frame(struct pipe_video_codec *decoder, struct pipe_video_buffer *target,
struct pipe_picture_desc *picture)
{
struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
@ -1015,9 +1013,8 @@ static void ruvd_begin_frame(struct pipe_video_codec *decoder,
&ruvd_destroy_associated_data);
dec->bs_size = 0;
dec->bs_ptr = dec->ws->buffer_map(
dec->bs_buffers[dec->cur_buffer].res->buf,
dec->cs, PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
dec->bs_ptr = dec->ws->buffer_map(dec->bs_buffers[dec->cur_buffer].res->buf, dec->cs,
PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
}
/**
@ -1038,10 +1035,8 @@ static void ruvd_decode_macroblock(struct pipe_video_codec *decoder,
*/
static void ruvd_decode_bitstream(struct pipe_video_codec *decoder,
struct pipe_video_buffer *target,
struct pipe_picture_desc *picture,
unsigned num_buffers,
const void * const *buffers,
const unsigned *sizes)
struct pipe_picture_desc *picture, unsigned num_buffers,
const void *const *buffers, const unsigned *sizes)
{
struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
unsigned i;
@ -1062,8 +1057,7 @@ static void ruvd_decode_bitstream(struct pipe_video_codec *decoder,
return;
}
dec->bs_ptr = dec->ws->buffer_map(
buf->res->buf, dec->cs,
dec->bs_ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
if (!dec->bs_ptr)
return;
@ -1080,8 +1074,7 @@ static void ruvd_decode_bitstream(struct pipe_video_codec *decoder,
/**
* end decoding of the current frame
*/
static void ruvd_end_frame(struct pipe_video_codec *decoder,
struct pipe_video_buffer *target,
static void ruvd_end_frame(struct pipe_video_codec *decoder, struct pipe_video_buffer *target,
struct pipe_picture_desc *picture)
{
struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
@ -1114,8 +1107,10 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
if ((picture->profile == PIPE_VIDEO_PROFILE_VC1_SIMPLE) ||
(picture->profile == PIPE_VIDEO_PROFILE_VC1_MAIN)) {
dec->msg->body.decode.width_in_samples = align(dec->msg->body.decode.width_in_samples, 16) / 16;
dec->msg->body.decode.height_in_samples = align(dec->msg->body.decode.height_in_samples, 16) / 16;
dec->msg->body.decode.width_in_samples =
align(dec->msg->body.decode.width_in_samples, 16) / 16;
dec->msg->body.decode.height_in_samples =
align(dec->msg->body.decode.height_in_samples, 16) / 16;
}
if (dec->dpb.res)
@ -1133,11 +1128,13 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
switch (u_reduce_video_profile(picture->profile)) {
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
dec->msg->body.decode.codec.h264 = get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
dec->msg->body.decode.codec.h264 =
get_h264_msg(dec, (struct pipe_h264_picture_desc *)picture);
break;
case PIPE_VIDEO_FORMAT_HEVC:
dec->msg->body.decode.codec.h265 = get_h265_msg(dec, target, (struct pipe_h265_picture_desc*)picture);
dec->msg->body.decode.codec.h265 =
get_h265_msg(dec, target, (struct pipe_h265_picture_desc *)picture);
if (dec->ctx.res == NULL) {
unsigned ctx_size;
if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
@ -1159,11 +1156,13 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
break;
case PIPE_VIDEO_FORMAT_MPEG12:
dec->msg->body.decode.codec.mpeg2 = get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc*)picture);
dec->msg->body.decode.codec.mpeg2 =
get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc *)picture);
break;
case PIPE_VIDEO_FORMAT_MPEG4:
dec->msg->body.decode.codec.mpeg4 = get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc*)picture);
dec->msg->body.decode.codec.mpeg4 =
get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc *)picture);
break;
case PIPE_VIDEO_FORMAT_JPEG:
@ -1183,18 +1182,17 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
send_msg_buf(dec);
if (dec->dpb.res)
send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->buf, 0, RADEON_USAGE_READWRITE,
RADEON_DOMAIN_VRAM);
if (dec->ctx.res)
send_cmd(dec, RUVD_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0,
RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
send_cmd(dec, RUVD_CMD_BITSTREAM_BUFFER, bs_buf->res->buf,
0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0,
RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_it_buf->res->buf,
FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
send_cmd(dec, RUVD_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0, RADEON_USAGE_READWRITE,
RADEON_DOMAIN_VRAM);
send_cmd(dec, RUVD_CMD_BITSTREAM_BUFFER, bs_buf->res->buf, 0, RADEON_USAGE_READ,
RADEON_DOMAIN_GTT);
send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_it_buf->res->buf, FB_BUFFER_OFFSET,
RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
if (have_it(dec))
send_cmd(dec, RUVD_CMD_ITSCALING_TABLE_BUFFER, msg_fb_it_buf->res->buf,
FB_BUFFER_OFFSET + dec->fb_size, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
@ -1245,7 +1243,6 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
break;
}
dec = CALLOC_STRUCT(ruvd_decoder);
if (!dec)
@ -1279,22 +1276,21 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
for (i = 0; i < 16; i++)
dec->render_pic_list[i] = NULL;
dec->fb_size = (sctx->family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA :
FB_BUFFER_SIZE;
dec->fb_size = (sctx->family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA : FB_BUFFER_SIZE;
bs_buf_size = width * height * (512 / (16 * 16));
for (i = 0; i < NUM_BUFFERS; ++i) {
unsigned msg_fb_it_size = FB_BUFFER_OFFSET + dec->fb_size;
STATIC_ASSERT(sizeof(struct ruvd_msg) <= FB_BUFFER_OFFSET);
if (have_it(dec))
msg_fb_it_size += IT_SCALING_TABLE_SIZE;
if (!si_vid_create_buffer(dec->screen, &dec->msg_fb_it_buffers[i],
msg_fb_it_size, PIPE_USAGE_STAGING)) {
if (!si_vid_create_buffer(dec->screen, &dec->msg_fb_it_buffers[i], msg_fb_it_size,
PIPE_USAGE_STAGING)) {
RVID_ERR("Can't allocated message buffers.\n");
goto error;
}
if (!si_vid_create_buffer(dec->screen, &dec->bs_buffers[i],
bs_buf_size, PIPE_USAGE_STAGING)) {
if (!si_vid_create_buffer(dec->screen, &dec->bs_buffers[i], bs_buf_size,
PIPE_USAGE_STAGING)) {
RVID_ERR("Can't allocated bitstream buffers.\n");
goto error;
}
@ -1322,8 +1318,7 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
}
if (sctx->family >= CHIP_POLARIS10 && sctx->screen->info.drm_minor >= 3) {
if (!si_vid_create_buffer(dec->screen, &dec->sessionctx,
UVD_SESSION_CONTEXT_SIZE,
if (!si_vid_create_buffer(dec->screen, &dec->sessionctx, UVD_SESSION_CONTEXT_SIZE,
PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't allocated session ctx.\n");
goto error;
@ -1361,7 +1356,8 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
return &dec->base;
error:
if (dec->cs) dec->ws->cs_destroy(dec->cs);
if (dec->cs)
dec->ws->cs_destroy(dec->cs);
for (i = 0; i < NUM_BUFFERS; ++i) {
si_vid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
@ -1388,8 +1384,7 @@ static unsigned texture_offset(struct radeon_surf *surface, unsigned layer,
layer * (uint64_t)surface->u.legacy.level[0].slice_size_dw * 4;
break;
case RUVD_SURFACE_TYPE_GFX9:
return surface->u.gfx9.surf_offset +
layer * surface->u.gfx9.surf_slice_size;
return surface->u.gfx9.surf_offset + layer * surface->u.gfx9.surf_slice_size;
break;
}
}
@ -1399,10 +1394,18 @@ static unsigned macro_tile_aspect(unsigned macro_tile_aspect)
{
switch (macro_tile_aspect) {
default:
case 1: macro_tile_aspect = 0; break;
case 2: macro_tile_aspect = 1; break;
case 4: macro_tile_aspect = 2; break;
case 8: macro_tile_aspect = 3; break;
case 1:
macro_tile_aspect = 0;
break;
case 2:
macro_tile_aspect = 1;
break;
case 4:
macro_tile_aspect = 2;
break;
case 8:
macro_tile_aspect = 3;
break;
}
return macro_tile_aspect;
}
@ -1412,10 +1415,18 @@ static unsigned bank_wh(unsigned bankwh)
{
switch (bankwh) {
default:
case 1: bankwh = 0; break;
case 2: bankwh = 1; break;
case 4: bankwh = 2; break;
case 8: bankwh = 3; break;
case 1:
bankwh = 0;
break;
case 2:
bankwh = 1;
break;
case 4:
bankwh = 2;
break;
case 8:
bankwh = 3;
break;
}
return bankwh;
}
@ -1468,7 +1479,8 @@ void si_uvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->u.legacy.bankw));
msg->body.decode.dt_surf_tile_config |= RUVD_BANK_HEIGHT(bank_wh(luma->u.legacy.bankh));
msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
msg->body.decode.dt_surf_tile_config |=
RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
break;
case RUVD_SURFACE_TYPE_GFX9:
msg->body.decode.dt_pitch = luma->u.gfx9.surf_pitch * luma->blk_w;

12
src/gallium/drivers/radeon/radeon_uvd.h
View File

@ -41,7 +41,8 @@
#define RUVD_PKT0_BASE_INDEX_S(x) (((unsigned)(x)&0xFFFF) << 0)
#define RUVD_PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF)
#define RUVD_PKT0_BASE_INDEX_C 0xFFFF0000
#define RUVD_PKT0(index, count) (RUVD_PKT_TYPE_S(0) | RUVD_PKT0_BASE_INDEX_S(index) | RUVD_PKT_COUNT_S(count))
#define RUVD_PKT0(index, count) \
(RUVD_PKT_TYPE_S(0) | RUVD_PKT0_BASE_INDEX_S(index) | RUVD_PKT_COUNT_S(count))
#define RUVD_PKT2() (RUVD_PKT_TYPE_S(2))
/* registers involved with UVD */
@ -111,7 +112,8 @@
#define RUVD_VC1_PROFILE_MAIN 0x00000001
#define RUVD_VC1_PROFILE_ADVANCED 0x00000002
enum ruvd_surface_type {
enum ruvd_surface_type
{
RUVD_SURFACE_TYPE_LEGACY = 0,
RUVD_SURFACE_TYPE_GFX9
};
@ -287,8 +289,7 @@ struct ruvd_mpeg2 {
uint8_t alternate_scan;
};
struct ruvd_mpeg4
{
struct ruvd_mpeg4 {
uint32_t decoded_pic_idx;
uint32_t ref_pic_idx[2];
@ -427,8 +428,7 @@ struct ruvd_msg {
};
/* driver dependent callback */
typedef struct pb_buffer* (*ruvd_set_dtb)
(struct ruvd_msg* msg, struct vl_video_buffer *vb);
typedef struct pb_buffer *(*ruvd_set_dtb)(struct ruvd_msg *msg, struct vl_video_buffer *vb);
/* create an UVD decode */
struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *context,

115
src/gallium/drivers/radeon/radeon_uvd_enc.c
View File

@ -25,18 +25,16 @@
*
**************************************************************************/
#include <stdio.h>
#include "radeon_uvd_enc.h"
#include "pipe/p_video_codec.h"
#include "util/u_video.h"
#include "radeon_video.h"
#include "radeonsi/si_pipe.h"
#include "util/u_memory.h"
#include "util/u_video.h"
#include "vl/vl_video_buffer.h"
#include "radeonsi/si_pipe.h"
#include "radeon_video.h"
#include "radeon_uvd_enc.h"
#include <stdio.h>
#define UVD_HEVC_LEVEL_1 30
#define UVD_HEVC_LEVEL_2 60
@ -52,8 +50,7 @@
#define UVD_HEVC_LEVEL_6_1 183
#define UVD_HEVC_LEVEL_6_2 186
static void
radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
struct pipe_h265_enc_picture_desc *pic)
{
enc->enc_pic.picture_type = pic->picture_type;
@ -61,73 +58,57 @@ radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
enc->enc_pic.not_referenced = pic->not_referenced;
enc->enc_pic.is_iframe =
(pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR)
|| (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
enc->enc_pic.is_iframe = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
(pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
enc->enc_pic.crop_left = 0;
enc->enc_pic.crop_right =
(align(enc->base.width, 16) - enc->base.width) / 2;
enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
enc->enc_pic.crop_top = 0;
enc->enc_pic.crop_bottom =
(align(enc->base.height, 16) - enc->base.height) / 2;
enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
enc->enc_pic.max_poc =
MAX2(16, util_next_power_of_two(pic->seq.intra_period));
enc->enc_pic.max_poc = MAX2(16, util_next_power_of_two(pic->seq.intra_period));
enc->enc_pic.log2_max_poc = 0;
for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
i = (i >> 1);
enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
enc->enc_pic.pic_width_in_luma_samples =
pic->seq.pic_width_in_luma_samples;
enc->enc_pic.pic_height_in_luma_samples =
pic->seq.pic_height_in_luma_samples;
enc->enc_pic.pic_width_in_luma_samples = pic->seq.pic_width_in_luma_samples;
enc->enc_pic.pic_height_in_luma_samples = pic->seq.pic_height_in_luma_samples;
enc->enc_pic.log2_diff_max_min_luma_coding_block_size =
pic->seq.log2_diff_max_min_luma_coding_block_size;
enc->enc_pic.log2_min_transform_block_size_minus2 =
pic->seq.log2_min_transform_block_size_minus2;
enc->enc_pic.log2_diff_max_min_transform_block_size =
pic->seq.log2_diff_max_min_transform_block_size;
enc->enc_pic.max_transform_hierarchy_depth_inter =
pic->seq.max_transform_hierarchy_depth_inter;
enc->enc_pic.max_transform_hierarchy_depth_intra =
pic->seq.max_transform_hierarchy_depth_intra;
enc->enc_pic.log2_parallel_merge_level_minus2 =
pic->pic.log2_parallel_merge_level_minus2;
enc->enc_pic.max_transform_hierarchy_depth_inter = pic->seq.max_transform_hierarchy_depth_inter;
enc->enc_pic.max_transform_hierarchy_depth_intra = pic->seq.max_transform_hierarchy_depth_intra;
enc->enc_pic.log2_parallel_merge_level_minus2 = pic->pic.log2_parallel_merge_level_minus2;
enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
enc->enc_pic.sample_adaptive_offset_enabled_flag =
pic->seq.sample_adaptive_offset_enabled_flag;
enc->enc_pic.sample_adaptive_offset_enabled_flag = pic->seq.sample_adaptive_offset_enabled_flag;
enc->enc_pic.pcm_enabled_flag = 0; /*HW not support PCM */
enc->enc_pic.sps_temporal_mvp_enabled_flag =
pic->seq.sps_temporal_mvp_enabled_flag;
enc->enc_pic.sps_temporal_mvp_enabled_flag = pic->seq.sps_temporal_mvp_enabled_flag;
}
static void
flush(struct radeon_uvd_encoder *enc)
static void flush(struct radeon_uvd_encoder *enc)
{
enc->ws->cs_flush(enc->cs, PIPE_FLUSH_ASYNC, NULL);
}
static void
radeon_uvd_enc_flush(struct pipe_video_codec *encoder)
static void radeon_uvd_enc_flush(struct pipe_video_codec *encoder)
{
struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
flush(enc);
}
static void
radeon_uvd_enc_cs_flush(void *ctx, unsigned flags,
struct pipe_fence_handle **fence)
static void radeon_uvd_enc_cs_flush(void *ctx, unsigned flags, struct pipe_fence_handle **fence)
{
// just ignored
}
static unsigned
get_cpb_num(struct radeon_uvd_encoder *enc)
static unsigned get_cpb_num(struct radeon_uvd_encoder *enc)
{
unsigned w = align(enc->base.width, 16) / 16;
unsigned h = align(enc->base.height, 16) / 16;
@ -176,16 +157,14 @@ get_cpb_num(struct radeon_uvd_encoder *enc)
return MIN2(dpb / (w * h), 16);
}
static void
radeon_uvd_enc_begin_frame(struct pipe_video_codec *encoder,
static void radeon_uvd_enc_begin_frame(struct pipe_video_codec *encoder,
struct pipe_video_buffer *source,
struct pipe_picture_desc *picture)
{
struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
radeon_uvd_enc_get_param(enc,
(struct pipe_h265_enc_picture_desc *) picture);
radeon_uvd_enc_get_param(enc, (struct pipe_h265_enc_picture_desc *)picture);
enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
@ -196,8 +175,7 @@ radeon_uvd_enc_begin_frame(struct pipe_video_codec *encoder,
struct rvid_buffer fb;
enc->stream_handle = si_vid_alloc_stream_handle();
enc->si = CALLOC_STRUCT(rvid_buffer);
si_vid_create_buffer(enc->screen, enc->si, 128 * 1024,
PIPE_USAGE_STAGING);
si_vid_create_buffer(enc->screen, enc->si, 128 * 1024, PIPE_USAGE_STAGING);
si_vid_create_buffer(enc->screen, &fb, 4096, PIPE_USAGE_STAGING);
enc->fb = &fb;
enc->begin(enc, picture);
@ -206,8 +184,7 @@ radeon_uvd_enc_begin_frame(struct pipe_video_codec *encoder,
}
}
static void
radeon_uvd_enc_encode_bitstream(struct pipe_video_codec *encoder,
static void radeon_uvd_enc_encode_bitstream(struct pipe_video_codec *encoder,
struct pipe_video_buffer *source,
struct pipe_resource *destination, void **fb)
{
@ -226,8 +203,7 @@ radeon_uvd_enc_encode_bitstream(struct pipe_video_codec *encoder,
enc->encode(enc);
}
static void
radeon_uvd_enc_end_frame(struct pipe_video_codec *encoder,
static void radeon_uvd_enc_end_frame(struct pipe_video_codec *encoder,
struct pipe_video_buffer *source,
struct pipe_picture_desc *picture)
{
@ -235,8 +211,7 @@ radeon_uvd_enc_end_frame(struct pipe_video_codec *encoder,
flush(enc);
}
static void
radeon_uvd_enc_destroy(struct pipe_video_codec *encoder)
static void radeon_uvd_enc_destroy(struct pipe_video_codec *encoder)
{
struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
@ -255,18 +230,15 @@ radeon_uvd_enc_destroy(struct pipe_video_codec *encoder)
FREE(enc);
}
static void
radeon_uvd_enc_get_feedback(struct pipe_video_codec *encoder,
void *feedback, unsigned *size)
static void radeon_uvd_enc_get_feedback(struct pipe_video_codec *encoder, void *feedback,
unsigned *size)
{
struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
struct rvid_buffer *fb = feedback;
if (NULL != size) {
radeon_uvd_enc_feedback_t *fb_data =
(radeon_uvd_enc_feedback_t *) enc->ws->buffer_map(
fb->res->buf, enc->cs,
PIPE_TRANSFER_READ_WRITE | RADEON_TRANSFER_TEMPORARY);
radeon_uvd_enc_feedback_t *fb_data = (radeon_uvd_enc_feedback_t *)enc->ws->buffer_map(
fb->res->buf, enc->cs, PIPE_TRANSFER_READ_WRITE | RADEON_TRANSFER_TEMPORARY);
if (!fb_data->status)
*size = fb_data->bitstream_size;
@ -279,8 +251,7 @@ radeon_uvd_enc_get_feedback(struct pipe_video_codec *encoder,
FREE(fb);
}
struct pipe_video_codec *
radeon_uvd_create_encoder(struct pipe_context *context,
struct pipe_video_codec *radeon_uvd_create_encoder(struct pipe_context *context,
const struct pipe_video_codec *templ,
struct radeon_winsys *ws,
radeon_uvd_enc_get_buffer get_buffer)
@ -314,8 +285,7 @@ radeon_uvd_create_encoder(struct pipe_context *context,
enc->bits_in_shifter = 0;
enc->screen = context->screen;
enc->ws = ws;
enc->cs =
ws->cs_create(sctx->ctx, RING_UVD_ENC, radeon_uvd_enc_cs_flush, enc, false);
enc->cs = ws->cs_create(sctx->ctx, RING_UVD_ENC, radeon_uvd_enc_cs_flush, enc, false);
if (!enc->cs) {
RVID_ERR("Can't get command submission context.\n");
@ -341,21 +311,19 @@ radeon_uvd_create_encoder(struct pipe_context *context,
if (!enc->cpb_num)
goto error;
get_buffer(((struct vl_video_buffer *) tmp_buf)->resources[0], NULL,
&tmp_surf);
get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
cpb_size = (sscreen->info.chip_class < GFX9) ?
align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
align(tmp_surf->u.legacy.level[0].nblk_y, 32) :
align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
cpb_size = (sscreen->info.chip_class < GFX9)
? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
align(tmp_surf->u.legacy.level[0].nblk_y, 32)
: align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
align(tmp_surf->u.gfx9.surf_height, 32);
cpb_size = cpb_size * 3 / 2;
cpb_size = cpb_size * enc->cpb_num;
tmp_buf->destroy(tmp_buf);
if (!si_vid_create_buffer
(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't create CPB buffer.\n");
goto error;
}
@ -374,8 +342,7 @@ radeon_uvd_create_encoder(struct pipe_context *context,
return NULL;
}
bool
si_radeon_uvd_enc_supported(struct si_screen * sscreen)
bool si_radeon_uvd_enc_supported(struct si_screen *sscreen)
{
return (sscreen->info.uvd_enc_supported);
}

118
src/gallium/drivers/radeon/radeon_uvd_enc.h
View File

@ -128,8 +128,7 @@
#define RENC_UVD_FEEDBACK_STATUS_OK 0x00000000
#define RENC_UVD_FEEDBACK_STATUS_NOT_ENCODED 0x10000001
typedef struct radeon_uvd_enc_feedback_s
{
typedef struct radeon_uvd_enc_feedback_s {
uint32_t task_id;
uint32_t first_in_task;
uint32_t last_in_task;
@ -142,23 +141,20 @@ typedef struct radeon_uvd_enc_feedback_s
uint32_t extra_bytes;
} radeon_uvd_enc_feedback_t;
typedef struct ruvd_enc_session_info_s
{
typedef struct ruvd_enc_session_info_s {
uint32_t reserved;
uint32_t interface_version;
uint32_t sw_context_address_hi;
uint32_t sw_context_address_lo;
} ruvd_enc_session_info_t;
typedef struct ruvd_enc_task_info_s
{
typedef struct ruvd_enc_task_info_s {
uint32_t total_size_of_all_packages;
uint32_t task_id;
uint32_t allowed_max_num_feedbacks;
} ruvd_enc_task_info_t;
typedef struct ruvd_enc_session_init_s
{
typedef struct ruvd_enc_session_init_s {
uint32_t aligned_picture_width;
uint32_t aligned_picture_height;
uint32_t padding_width;
@ -167,38 +163,31 @@ typedef struct ruvd_enc_session_init_s
uint32_t pre_encode_chroma_enabled;
} ruvd_enc_session_init_t;
typedef struct ruvd_enc_layer_control_s
{
typedef struct ruvd_enc_layer_control_s {
uint32_t max_num_temporal_layers;
uint32_t num_temporal_layers;
} ruvd_enc_layer_control_t;
typedef struct ruvd_enc_layer_select_s
{
typedef struct ruvd_enc_layer_select_s {
uint32_t temporal_layer_index;
} ruvd_enc_layer_select_t;
typedef struct ruvd_enc_hevc_slice_control_s
{
typedef struct ruvd_enc_hevc_slice_control_s {
uint32_t slice_control_mode;
union
{
struct
{
union {
struct {
uint32_t num_ctbs_per_slice;
uint32_t num_ctbs_per_slice_segment;
} fixed_ctbs_per_slice;
struct
{
struct {
uint32_t num_bits_per_slice;
uint32_t num_bits_per_slice_segment;
} fixed_bits_per_slice;
};
} ruvd_enc_hevc_slice_control_t;
typedef struct ruvd_enc_hevc_spec_misc_s
{
typedef struct ruvd_enc_hevc_spec_misc_s {
uint32_t log2_min_luma_coding_block_size_minus3;
uint32_t amp_disabled;
uint32_t strong_intra_smoothing_enabled;
@ -208,14 +197,12 @@ typedef struct ruvd_enc_hevc_spec_misc_s
uint32_t quarter_pel_enabled;
} ruvd_enc_hevc_spec_misc_t;
typedef struct ruvd_enc_rate_ctl_session_init_s
{
typedef struct ruvd_enc_rate_ctl_session_init_s {
uint32_t rate_control_method;
uint32_t vbv_buffer_level;
} ruvd_enc_rate_ctl_session_init_t;
typedef struct ruvd_enc_rate_ctl_layer_init_s
{
typedef struct ruvd_enc_rate_ctl_layer_init_s {
uint32_t target_bit_rate;
uint32_t peak_bit_rate;
uint32_t frame_rate_num;
@ -226,8 +213,7 @@ typedef struct ruvd_enc_rate_ctl_layer_init_s
uint32_t peak_bits_per_picture_fractional;
} ruvd_enc_rate_ctl_layer_init_t;
typedef struct ruvd_enc_rate_ctl_per_picture_s
{
typedef struct ruvd_enc_rate_ctl_per_picture_s {
uint32_t qp;
uint32_t min_qp_app;
uint32_t max_qp_app;
@ -237,34 +223,27 @@ typedef struct ruvd_enc_rate_ctl_per_picture_s
uint32_t enforce_hrd;
} ruvd_enc_rate_ctl_per_picture_t;
typedef struct ruvd_enc_quality_params_s
{
typedef struct ruvd_enc_quality_params_s {
uint32_t vbaq_mode;
uint32_t scene_change_sensitivity;
uint32_t scene_change_min_idr_interval;
} ruvd_enc_quality_params_t;
typedef struct ruvd_enc_direct_output_nalu_s
{
typedef struct ruvd_enc_direct_output_nalu_s {
uint32_t type;
uint32_t size;
uint32_t data[1];
} ruvd_enc_direct_output_nalu_t;
typedef struct ruvd_enc_slice_header_s
{
uint32_t
bitstream_template
[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS];
struct
{
typedef struct ruvd_enc_slice_header_s {
uint32_t bitstream_template[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS];
struct {
uint32_t instruction;
uint32_t num_bits;
} instructions[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS];
} ruvd_enc_slice_header_t;
typedef struct ruvd_enc_encode_params_s
{
typedef struct ruvd_enc_encode_params_s {
uint32_t pic_type;
uint32_t allowed_max_bitstream_size;
uint32_t input_picture_luma_address_hi;
@ -273,13 +252,11 @@ typedef struct ruvd_enc_encode_params_s
uint32_t input_picture_chroma_address_lo;
uint32_t input_pic_luma_pitch;
uint32_t input_pic_chroma_pitch;
union
{
union {
uint32_t input_pic_addr_mode;
uint32_t reserved;
};
union
{
union {
uint32_t input_pic_array_mode;
uint32_t input_pic_swizzle_mode;
};
@ -287,8 +264,7 @@ typedef struct ruvd_enc_encode_params_s
uint32_t reconstructed_picture_index;
} ruvd_enc_encode_params_t;
typedef struct ruvd_enc_hevc_deblocking_filter_s
{
typedef struct ruvd_enc_hevc_deblocking_filter_s {
uint32_t loop_filter_across_slices_enabled;
int32_t deblocking_filter_disabled;
int32_t beta_offset_div2;
@ -297,48 +273,40 @@ typedef struct ruvd_enc_hevc_deblocking_filter_s
int32_t cr_qp_offset;
} ruvd_enc_hevc_deblocking_filter_t;
typedef struct ruvd_enc_intra_refresh_s
{
typedef struct ruvd_enc_intra_refresh_s {
uint32_t intra_refresh_mode;
uint32_t offset;
uint32_t region_size;
} ruvd_enc_intra_refresh_t;
typedef struct ruvd_enc_reconstructed_picture_s
{
typedef struct ruvd_enc_reconstructed_picture_s {
uint32_t luma_offset;
uint32_t chroma_offset;
} ruvd_enc_reconstructed_picture_t;
typedef struct ruvd_enc_encode_context_buffer_s
{
typedef struct ruvd_enc_encode_context_buffer_s {
uint32_t encode_context_address_hi;
uint32_t encode_context_address_lo;
union
{
union {
uint32_t addr_mode;
uint32_t reserved;
};
union
{
union {
uint32_t array_mode;
uint32_t swizzle_mode;
};
uint32_t rec_luma_pitch;
uint32_t rec_chroma_pitch;
uint32_t num_reconstructed_pictures;
ruvd_enc_reconstructed_picture_t
reconstructed_pictures[RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES];
ruvd_enc_reconstructed_picture_t reconstructed_pictures[RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES];
uint32_t pre_encode_picture_luma_pitch;
uint32_t pre_encode_picture_chroma_pitch;
ruvd_enc_reconstructed_picture_t
pre_encode_reconstructed_pictures
[RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES];
pre_encode_reconstructed_pictures[RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES];
ruvd_enc_reconstructed_picture_t pre_encode_input_picture;
} ruvd_enc_encode_context_buffer_t;
typedef struct ruvd_enc_video_bitstream_buffer_s
{
typedef struct ruvd_enc_video_bitstream_buffer_s {
uint32_t mode;
uint32_t video_bitstream_buffer_address_hi;
uint32_t video_bitstream_buffer_address_lo;
@ -346,8 +314,7 @@ typedef struct ruvd_enc_video_bitstream_buffer_s
uint32_t video_bitstream_data_offset;
} ruvd_enc_video_bitstream_buffer_t;
typedef struct ruvd_enc_feedback_buffer_s
{
typedef struct ruvd_enc_feedback_buffer_s {
uint32_t mode;
uint32_t feedback_buffer_address_hi;
uint32_t feedback_buffer_address_lo;
@ -355,20 +322,15 @@ typedef struct ruvd_enc_feedback_buffer_s
uint32_t feedback_data_size;
} ruvd_enc_feedback_buffer_t;
typedef void (*radeon_uvd_enc_get_buffer) (struct pipe_resource * resource,
struct pb_buffer ** handle,
typedef void (*radeon_uvd_enc_get_buffer)(struct pipe_resource *resource, struct pb_buffer **handle,
struct radeon_surf **surface);
struct pipe_video_codec *radeon_uvd_create_encoder(struct pipe_context
*context,
const struct
pipe_video_codec *templat,
struct pipe_video_codec *radeon_uvd_create_encoder(struct pipe_context *context,
const struct pipe_video_codec *templat,
struct radeon_winsys *ws,
radeon_uvd_enc_get_buffer
get_buffer);
radeon_uvd_enc_get_buffer get_buffer);
struct radeon_uvd_enc_pic
{
struct radeon_uvd_enc_pic {
enum pipe_h265_enc_picture_type picture_type;
unsigned frame_num;
@ -422,12 +384,10 @@ struct radeon_uvd_enc_pic
ruvd_enc_encode_params_t enc_params;
};
struct radeon_uvd_encoder
{
struct radeon_uvd_encoder {
struct pipe_video_codec base;
void (*begin) (struct radeon_uvd_encoder * enc,
struct pipe_picture_desc * pic);
void (*begin)(struct radeon_uvd_encoder *enc, struct pipe_picture_desc *pic);
void (*encode)(struct radeon_uvd_encoder *enc);
void (*destroy)(struct radeon_uvd_encoder *enc);

408
src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
View File

@ -25,37 +25,39 @@
*
**************************************************************************/
#include "pipe/p_video_codec.h"
#include "radeon_uvd_enc.h"
#include "radeon_video.h"
#include "radeonsi/si_pipe.h"
#include "util/u_memory.h"
#include "util/u_video.h"
#include "vl/vl_video_buffer.h"
#include <stdio.h>
#include "pipe/p_video_codec.h"
#include "util/u_video.h"
#include "util/u_memory.h"
#include "vl/vl_video_buffer.h"
#include "radeonsi/si_pipe.h"
#include "radeon_video.h"
#include "radeon_uvd_enc.h"
#define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
#define RADEON_ENC_BEGIN(cmd) { \
#define RADEON_ENC_BEGIN(cmd) \
{ \
uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
RADEON_ENC_CS(cmd)
#define RADEON_ENC_READ(buf, domain, off) radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
#define RADEON_ENC_WRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
#define RADEON_ENC_READWRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
#define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
enc->total_task_size += *begin;}
#define RADEON_ENC_READ(buf, domain, off) \
radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
#define RADEON_ENC_WRITE(buf, domain, off) \
radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
#define RADEON_ENC_READWRITE(buf, domain, off) \
radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
#define RADEON_ENC_END() \
*begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
enc->total_task_size += *begin; \
}
static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
static void
radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc,
struct pb_buffer *buf, enum radeon_bo_usage usage,
enum radeon_bo_domain domain, signed offset)
static void radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc, struct pb_buffer *buf,
enum radeon_bo_usage usage, enum radeon_bo_domain domain,
signed offset)
{
enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
domain, 0);
enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
uint64_t addr;
addr = enc->ws->buffer_get_virtual_address(buf);
addr = addr + offset;
@ -63,9 +65,7 @@ radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc,
RADEON_ENC_CS(addr);
}
static void
radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder *enc,
bool set)
static void radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder *enc, bool set)
{
if (set != enc->emulation_prevention) {
enc->emulation_prevention = set;
@ -73,9 +73,7 @@ radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder *enc,
}
}
static void
radeon_uvd_enc_output_one_byte(struct radeon_uvd_encoder *enc,
unsigned char byte)
static void radeon_uvd_enc_output_one_byte(struct radeon_uvd_encoder *enc, unsigned char byte)
{
if (enc->byte_index == 0)
enc->cs->current.buf[enc->cs->current.cdw] = 0;
@ -89,14 +87,11 @@ radeon_uvd_enc_output_one_byte(struct radeon_uvd_encoder *enc,
}
}
static void
radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder *enc,
unsigned char byte)
static void radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder *enc, unsigned char byte)
{
if (enc->emulation_prevention) {
if ((enc->num_zeros >= 2)
&& ((byte == 0x00) || (byte == 0x01)
|| (byte == 0x02) || (byte == 0x03))) {
if ((enc->num_zeros >= 2) &&
((byte == 0x00) || (byte == 0x01) || (byte == 0x02) || (byte == 0x03))) {
radeon_uvd_enc_output_one_byte(enc, 0x03);
enc->bits_output += 8;
enc->num_zeros = 0;
@ -105,23 +100,20 @@ radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder *enc,
}
}
static void
radeon_uvd_enc_code_fixed_bits(struct radeon_uvd_encoder *enc,
unsigned int value, unsigned int num_bits)
static void radeon_uvd_enc_code_fixed_bits(struct radeon_uvd_encoder *enc, unsigned int value,
unsigned int num_bits)
{
unsigned int bits_to_pack = 0;
while (num_bits > 0) {
unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
bits_to_pack =
num_bits >
(32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
if (bits_to_pack < num_bits)
value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
enc->shifter |=
value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
num_bits -= bits_to_pack;
enc->bits_in_shifter += bits_to_pack;
@ -136,8 +128,7 @@ radeon_uvd_enc_code_fixed_bits(struct radeon_uvd_encoder *enc,
}
}
static void
radeon_uvd_enc_reset(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_reset(struct radeon_uvd_encoder *enc)
{
enc->emulation_prevention = false;
enc->shifter = 0;
@ -147,8 +138,7 @@ radeon_uvd_enc_reset(struct radeon_uvd_encoder *enc)
enc->byte_index = 0;
}
static void
radeon_uvd_enc_byte_align(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_byte_align(struct radeon_uvd_encoder *enc)
{
unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
@ -156,8 +146,7 @@ radeon_uvd_enc_byte_align(struct radeon_uvd_encoder *enc)
radeon_uvd_enc_code_fixed_bits(enc, 0, num_padding_zeros);
}
static void
radeon_uvd_enc_flush_headers(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_flush_headers(struct radeon_uvd_encoder *enc)
{
if (enc->bits_in_shifter != 0) {
unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
@ -175,8 +164,7 @@ radeon_uvd_enc_flush_headers(struct radeon_uvd_encoder *enc)
}
}
static void
radeon_uvd_enc_code_ue(struct radeon_uvd_encoder *enc, unsigned int value)
static void radeon_uvd_enc_code_ue(struct radeon_uvd_encoder *enc, unsigned int value)
{
int x = -1;
unsigned int ue_code = value + 1;
@ -191,26 +179,21 @@ radeon_uvd_enc_code_ue(struct radeon_uvd_encoder *enc, unsigned int value)
radeon_uvd_enc_code_fixed_bits(enc, ue_code, ue_length);
}
static void
radeon_uvd_enc_code_se(struct radeon_uvd_encoder *enc, int value)
static void radeon_uvd_enc_code_se(struct radeon_uvd_encoder *enc, int value)
{
unsigned int v = 0;
if (value != 0)
v = (value < 0 ? ((unsigned int) (0 - value) << 1)
: (((unsigned int) (value) << 1) - 1));
v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
radeon_uvd_enc_code_ue(enc, v);
}
static void
radeon_uvd_enc_session_info(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_session_info(struct radeon_uvd_encoder *enc)
{
unsigned int interface_version =
((RENC_UVD_FW_INTERFACE_MAJOR_VERSION <<
RENC_UVD_IF_MAJOR_VERSION_SHIFT) |
(RENC_UVD_FW_INTERFACE_MINOR_VERSION <<
RENC_UVD_IF_MINOR_VERSION_SHIFT));
((RENC_UVD_FW_INTERFACE_MAJOR_VERSION << RENC_UVD_IF_MAJOR_VERSION_SHIFT) |
(RENC_UVD_FW_INTERFACE_MINOR_VERSION << RENC_UVD_IF_MINOR_VERSION_SHIFT));
RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INFO);
RADEON_ENC_CS(0x00000000); // reserved
RADEON_ENC_CS(interface_version);
@ -218,8 +201,7 @@ radeon_uvd_enc_session_info(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_task_info(struct radeon_uvd_encoder *enc, bool need_feedback)
static void radeon_uvd_enc_task_info(struct radeon_uvd_encoder *enc, bool need_feedback)
{
enc->enc_pic.task_info.task_id++;
@ -235,13 +217,10 @@ radeon_uvd_enc_task_info(struct radeon_uvd_encoder *enc, bool need_feedback)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_session_init_hevc(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_session_init_hevc(struct radeon_uvd_encoder *enc)
{
enc->enc_pic.session_init.aligned_picture_width =
align(enc->base.width, 64);
enc->enc_pic.session_init.aligned_picture_height =
align(enc->base.height, 16);
enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
enc->enc_pic.session_init.padding_width =
enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
enc->enc_pic.session_init.padding_height =
@ -259,8 +238,7 @@ radeon_uvd_enc_session_init_hevc(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_layer_control(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_layer_control(struct radeon_uvd_encoder *enc)
{
enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
@ -271,8 +249,7 @@ radeon_uvd_enc_layer_control(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_layer_select(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_layer_select(struct radeon_uvd_encoder *enc)
{
enc->enc_pic.layer_sel.temporal_layer_index = 0;
@ -281,46 +258,37 @@ radeon_uvd_enc_layer_select(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_slice_control_hevc(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_slice_control_hevc(struct radeon_uvd_encoder *enc)
{
enc->enc_pic.hevc_slice_ctrl.slice_control_mode =
RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS;
enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS;
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice =
align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
enc->enc_pic.hevc_slice_ctrl.
fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SLICE_CONTROL);
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.
fixed_ctbs_per_slice.num_ctbs_per_slice);
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.
fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
RADEON_ENC_END();
}
static void
radeon_uvd_enc_spec_misc_hevc(struct radeon_uvd_encoder *enc,
static void radeon_uvd_enc_spec_misc_hevc(struct radeon_uvd_encoder *enc,
struct pipe_picture_desc *picture)
{
struct pipe_h265_enc_picture_desc *pic =
(struct pipe_h265_enc_picture_desc *) picture;
struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 =
pic->seq.log2_min_luma_coding_block_size_minus3;
enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled =
pic->seq.strong_intra_smoothing_enabled_flag;
enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag =
pic->pic.constrained_intra_pred_flag;
enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = pic->pic.constrained_intra_pred_flag;
enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SPEC_MISC);
RADEON_ENC_CS(enc->enc_pic.
hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
@ -330,22 +298,18 @@ radeon_uvd_enc_spec_misc_hevc(struct radeon_uvd_encoder *enc,
RADEON_ENC_END();
}
static void
radeon_uvd_enc_rc_session_init(struct radeon_uvd_encoder *enc,
static void radeon_uvd_enc_rc_session_init(struct radeon_uvd_encoder *enc,
struct pipe_picture_desc *picture)
{
struct pipe_h265_enc_picture_desc *pic =
(struct pipe_h265_enc_picture_desc *) picture;
struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc.vbv_buf_lv;
switch (pic->rc.rate_ctrl_method) {
case PIPE_H265_ENC_RATE_CONTROL_METHOD_DISABLE:
enc->enc_pic.rc_session_init.rate_control_method =
RENC_UVD_RATE_CONTROL_METHOD_NONE;
enc->enc_pic.rc_session_init.rate_control_method = RENC_UVD_RATE_CONTROL_METHOD_NONE;
break;
case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT:
enc->enc_pic.rc_session_init.rate_control_method =
RENC_UVD_RATE_CONTROL_METHOD_CBR;
enc->enc_pic.rc_session_init.rate_control_method = RENC_UVD_RATE_CONTROL_METHOD_CBR;
break;
case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE:
@ -353,8 +317,7 @@ radeon_uvd_enc_rc_session_init(struct radeon_uvd_encoder *enc,
RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
break;
default:
enc->enc_pic.rc_session_init.rate_control_method =
RENC_UVD_RATE_CONTROL_METHOD_NONE;
enc->enc_pic.rc_session_init.rate_control_method = RENC_UVD_RATE_CONTROL_METHOD_NONE;
}
RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT);
@ -363,23 +326,18 @@ radeon_uvd_enc_rc_session_init(struct radeon_uvd_encoder *enc,
RADEON_ENC_END();
}
static void
radeon_uvd_enc_rc_layer_init(struct radeon_uvd_encoder *enc,
static void radeon_uvd_enc_rc_layer_init(struct radeon_uvd_encoder *enc,
struct pipe_picture_desc *picture)
{
struct pipe_h265_enc_picture_desc *pic =
(struct pipe_h265_enc_picture_desc *) picture;
struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
enc->enc_pic.rc_layer_init.target_bit_rate = pic->rc.target_bitrate;
enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rc.peak_bitrate;
enc->enc_pic.rc_layer_init.frame_rate_num = pic->rc.frame_rate_num;
enc->enc_pic.rc_layer_init.frame_rate_den = pic->rc.frame_rate_den;
enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rc.vbv_buffer_size;
enc->enc_pic.rc_layer_init.avg_target_bits_per_picture =
pic->rc.target_bits_picture;
enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer =
pic->rc.peak_bits_picture_integer;
enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional =
pic->rc.peak_bits_picture_fraction;
enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rc.target_bits_picture;
enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rc.peak_bits_picture_integer;
enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rc.peak_bits_picture_fraction;
RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT);
RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate);
@ -393,18 +351,15 @@ radeon_uvd_enc_rc_layer_init(struct radeon_uvd_encoder *enc,
RADEON_ENC_END();
}
static void
radeon_uvd_enc_deblocking_filter_hevc(struct radeon_uvd_encoder *enc,
static void radeon_uvd_enc_deblocking_filter_hevc(struct radeon_uvd_encoder *enc,
struct pipe_picture_desc *picture)
{
struct pipe_h265_enc_picture_desc *pic =
(struct pipe_h265_enc_picture_desc *) picture;
struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled =
pic->slice.slice_loop_filter_across_slices_enabled_flag;
enc->enc_pic.hevc_deblock.deblocking_filter_disabled =
pic->slice.slice_deblocking_filter_disabled_flag;
enc->enc_pic.hevc_deblock.beta_offset_div2 =
pic->slice.slice_beta_offset_div2;
enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
@ -419,8 +374,7 @@ radeon_uvd_enc_deblocking_filter_hevc(struct radeon_uvd_encoder *enc,
RADEON_ENC_END();
}
static void
radeon_uvd_enc_quality_params(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_quality_params(struct radeon_uvd_encoder *enc)
{
enc->enc_pic.quality_params.vbaq_mode = 0;
enc->enc_pic.quality_params.scene_change_sensitivity = 0;
@ -433,8 +387,7 @@ radeon_uvd_enc_quality_params(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
{
RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
RADEON_ENC_CS(RENC_UVD_NALU_TYPE_SPS);
@ -448,9 +401,7 @@ radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
radeon_uvd_enc_byte_align(enc);
radeon_uvd_enc_set_emulation_prevention(enc, true);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 4);
radeon_uvd_enc_code_fixed_bits(enc,
enc->enc_pic.
layer_ctrl.max_num_temporal_layers - 1, 3);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
@ -470,16 +421,13 @@ radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
radeon_uvd_enc_code_ue(enc, 0x0);
radeon_uvd_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
radeon_uvd_enc_code_ue(enc,
enc->enc_pic.session_init.aligned_picture_width);
radeon_uvd_enc_code_ue(enc,
enc->enc_pic.session_init.aligned_picture_height);
radeon_uvd_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
radeon_uvd_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
int conformance_window_flag =
(enc->enc_pic.crop_top > 0) ||
(enc->enc_pic.crop_bottom > 0) ||
(enc->enc_pic.crop_left > 0) ||
(enc->enc_pic.crop_right > 0) ? 0x1 : 0x0;
int conformance_window_flag = (enc->enc_pic.crop_top > 0) || (enc->enc_pic.crop_bottom > 0) ||
(enc->enc_pic.crop_left > 0) || (enc->enc_pic.crop_right > 0)
? 0x1
: 0x0;
radeon_uvd_enc_code_fixed_bits(enc, conformance_window_flag, 1);
if (conformance_window_flag == 1) {
radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_left);
@ -495,31 +443,18 @@ radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
radeon_uvd_enc_code_ue(enc, 1);
radeon_uvd_enc_code_ue(enc, 0x0);
radeon_uvd_enc_code_ue(enc, 0x0);
radeon_uvd_enc_code_ue(enc,
enc->enc_pic.hevc_spec_misc.
log2_min_luma_coding_block_size_minus3);
radeon_uvd_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
/* Only support CTBSize 64 */
radeon_uvd_enc_code_ue(enc,
6 -
(enc->enc_pic.hevc_spec_misc.
log2_min_luma_coding_block_size_minus3 + 3));
radeon_uvd_enc_code_ue(enc,
enc->enc_pic.log2_min_transform_block_size_minus2);
radeon_uvd_enc_code_ue(enc,
enc->enc_pic.
log2_diff_max_min_transform_block_size);
radeon_uvd_enc_code_ue(enc,
enc->enc_pic.max_transform_hierarchy_depth_inter);
radeon_uvd_enc_code_ue(enc,
enc->enc_pic.max_transform_hierarchy_depth_intra);
radeon_uvd_enc_code_ue(
enc, 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
radeon_uvd_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
radeon_uvd_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
radeon_uvd_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
radeon_uvd_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
radeon_uvd_enc_code_fixed_bits(enc,
!enc->enc_pic.hevc_spec_misc.amp_disabled,
1);
radeon_uvd_enc_code_fixed_bits(enc,
enc->enc_pic.
sample_adaptive_offset_enabled_flag, 1);
radeon_uvd_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
radeon_uvd_enc_code_ue(enc, 1);
@ -531,9 +466,8 @@ radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0, 1);
radeon_uvd_enc_code_fixed_bits(enc,
enc->enc_pic.hevc_spec_misc.
strong_intra_smoothing_enabled, 1);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled,
1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
@ -547,8 +481,7 @@ radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder *enc)
{
RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
RADEON_ENC_CS(RENC_UVD_NALU_TYPE_PPS);
@ -569,12 +502,9 @@ radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder *enc)
radeon_uvd_enc_code_ue(enc, 0x0);
radeon_uvd_enc_code_ue(enc, 0x0);
radeon_uvd_enc_code_se(enc, 0x0);
radeon_uvd_enc_code_fixed_bits(enc,
enc->enc_pic.hevc_spec_misc.
constrained_intra_pred_flag, 1);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
if (enc->enc_pic.rc_session_init.rate_control_method ==
RENC_UVD_RATE_CONTROL_METHOD_NONE)
if (enc->enc_pic.rc_session_init.rate_control_method == RENC_UVD_RATE_CONTROL_METHOD_NONE)
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
else {
radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
@ -587,14 +517,11 @@ radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder *enc)
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
radeon_uvd_enc_code_fixed_bits(enc,
enc->enc_pic.hevc_deblock.
loop_filter_across_slices_enabled, 1);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled,
1);
radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
radeon_uvd_enc_code_fixed_bits(enc,
enc->enc_pic.hevc_deblock.
deblocking_filter_disabled, 1);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
@ -614,8 +541,7 @@ radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_nalu_vps_hevc(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_nalu_vps_hevc(struct radeon_uvd_encoder *enc)
{
RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
RADEON_ENC_CS(RENC_UVD_NALU_TYPE_VPS);
@ -632,9 +558,7 @@ radeon_uvd_enc_nalu_vps_hevc(struct radeon_uvd_encoder *enc)
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 4);
radeon_uvd_enc_code_fixed_bits(enc, 0x3, 2);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 6);
radeon_uvd_enc_code_fixed_bits(enc,
enc->enc_pic.layer_ctrl.
max_num_temporal_layers - 1, 3);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0xffff, 16);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
@ -671,8 +595,7 @@ radeon_uvd_enc_nalu_vps_hevc(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_nalu_aud_hevc(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_nalu_aud_hevc(struct radeon_uvd_encoder *enc)
{
RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
RADEON_ENC_CS(RENC_UVD_NALU_TYPE_AUD);
@ -709,8 +632,7 @@ radeon_uvd_enc_nalu_aud_hevc(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
{
uint32_t instruction[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
uint32_t num_bits[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
@ -736,8 +658,7 @@ radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_FIRST_SLICE;
inst_index++;
if ((enc->enc_pic.nal_unit_type >= 16)
&& (enc->enc_pic.nal_unit_type <= 23))
if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
radeon_uvd_enc_code_ue(enc, 0x0);
@ -771,11 +692,8 @@ radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
radeon_uvd_enc_code_ue(enc, 0x1);
}
if ((enc->enc_pic.nal_unit_type != 19)
&& (enc->enc_pic.nal_unit_type != 20)) {
radeon_uvd_enc_code_fixed_bits(enc,
enc->enc_pic.pic_order_cnt,
enc->enc_pic.log2_max_poc);
if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
if (enc->enc_pic.picture_type == PIPE_H265_ENC_PICTURE_TYPE_P)
radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
else {
@ -792,9 +710,7 @@ radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
if ((enc->enc_pic.picture_type == PIPE_H265_ENC_PICTURE_TYPE_P) ||
(enc->enc_pic.picture_type == PIPE_H265_ENC_PICTURE_TYPE_B)) {
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
radeon_uvd_enc_code_fixed_bits(enc,
enc->enc_pic.hevc_spec_misc.
cabac_init_flag, 1);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
radeon_uvd_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
}
@ -810,9 +726,8 @@ radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
(!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) {
radeon_uvd_enc_code_fixed_bits(enc,
enc->enc_pic.hevc_deblock.
loop_filter_across_slices_enabled, 1);
radeon_uvd_enc_code_fixed_bits(
enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
radeon_uvd_enc_flush_headers(enc);
bit_index++;
@ -824,12 +739,10 @@ radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_END;
for (int i = bit_index;
i < RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
for (int i = bit_index; i < RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
RADEON_ENC_CS(0x00000000);
for (int j = 0; j < RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS;
j++) {
for (int j = 0; j < RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
RADEON_ENC_CS(instruction[j]);
RADEON_ENC_CS(num_bits[j]);
}
@ -837,23 +750,18 @@ radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_ctx(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_ctx(struct radeon_uvd_encoder *enc)
{
struct si_screen *sscreen = (struct si_screen *)enc->screen;
enc->enc_pic.ctx_buf.swizzle_mode = 0;
if (sscreen->info.chip_class < GFX9) {
enc->enc_pic.ctx_buf.rec_luma_pitch =
(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
enc->enc_pic.ctx_buf.rec_luma_pitch = (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
enc->enc_pic.ctx_buf.rec_chroma_pitch =
(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
}
else {
enc->enc_pic.ctx_buf.rec_luma_pitch =
enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
enc->enc_pic.ctx_buf.rec_chroma_pitch =
enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
} else {
enc->enc_pic.ctx_buf.rec_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
enc->enc_pic.ctx_buf.rec_chroma_pitch = enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
}
enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
@ -867,14 +775,11 @@ radeon_uvd_enc_ctx(struct radeon_uvd_encoder *enc)
/* reconstructed_picture_1_luma_offset */
RADEON_ENC_CS(0x00000000);
/* reconstructed_picture_1_chroma_offset */
RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch *
align(enc->base.height, 16));
RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch * align(enc->base.height, 16));
/* reconstructed_picture_2_luma_offset */
RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch *
align(enc->base.height, 16) * 3 / 2);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch * align(enc->base.height, 16) * 3 / 2);
/* reconstructed_picture_2_chroma_offset */
RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch *
align(enc->base.height, 16) * 5 / 2);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch * align(enc->base.height, 16) * 5 / 2);
for (int i = 0; i < 136; i++)
RADEON_ENC_CS(0x00000000);
@ -882,8 +787,7 @@ radeon_uvd_enc_ctx(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_bitstream(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_bitstream(struct radeon_uvd_encoder *enc)
{
enc->enc_pic.bit_buf.mode = RENC_UVD_SWIZZLE_MODE_LINEAR;
enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
@ -897,8 +801,7 @@ radeon_uvd_enc_bitstream(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_feedback(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_feedback(struct radeon_uvd_encoder *enc)
{
enc->enc_pic.fb_buf.mode = RENC_UVD_FEEDBACK_BUFFER_MODE_LINEAR;
enc->enc_pic.fb_buf.feedback_buffer_size = 16;
@ -912,11 +815,9 @@ radeon_uvd_enc_feedback(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_intra_refresh(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_intra_refresh(struct radeon_uvd_encoder *enc)
{
enc->enc_pic.intra_ref.intra_refresh_mode =
RENC_UVD_INTRA_REFRESH_MODE_NONE;
enc->enc_pic.intra_ref.intra_refresh_mode = RENC_UVD_INTRA_REFRESH_MODE_NONE;
enc->enc_pic.intra_ref.offset = 0;
enc->enc_pic.intra_ref.region_size = 0;
@ -927,12 +828,10 @@ radeon_uvd_enc_intra_refresh(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_rc_per_pic(struct radeon_uvd_encoder *enc,
static void radeon_uvd_enc_rc_per_pic(struct radeon_uvd_encoder *enc,
struct pipe_picture_desc *picture)
{
struct pipe_h265_enc_picture_desc *pic =
(struct pipe_h265_enc_picture_desc *) picture;
struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
enc->enc_pic.rc_per_pic.qp = pic->rc.quant_i_frames;
enc->enc_pic.rc_per_pic.min_qp_app = 0;
enc->enc_pic.rc_per_pic.max_qp_app = 51;
@ -952,8 +851,7 @@ radeon_uvd_enc_rc_per_pic(struct radeon_uvd_encoder *enc,
RADEON_ENC_END();
}
static void
radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
{
struct si_screen *sscreen = (struct si_screen *)enc->screen;
switch (enc->enc_pic.picture_type) {
@ -980,40 +878,30 @@ radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
enc->enc_pic.enc_params.input_pic_chroma_pitch =
(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
}
else {
enc->enc_pic.enc_params.input_pic_luma_pitch =
enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
} else {
enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
enc->enc_pic.enc_params.input_pic_chroma_pitch =
enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
}
enc->enc_pic.enc_params.input_pic_swizzle_mode =
RENC_UVD_SWIZZLE_MODE_LINEAR;
enc->enc_pic.enc_params.input_pic_swizzle_mode = RENC_UVD_SWIZZLE_MODE_LINEAR;
if (enc->enc_pic.enc_params.pic_type == RENC_UVD_PICTURE_TYPE_I)
enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
else
enc->enc_pic.enc_params.reference_picture_index =
(enc->enc_pic.frame_num - 1) % 2;
enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
enc->enc_pic.enc_params.reconstructed_picture_index =
enc->enc_pic.frame_num % 2;
enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_ENCODE_PARAMS);
RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
if (sscreen->info.chip_class < GFX9) {
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->luma->u.legacy.level[0].offset);
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->chroma->u.legacy.level[0].offset);
}
else {
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->luma->u.gfx9.surf_offset);
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->chroma->u.gfx9.surf_offset);
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.legacy.level[0].offset);
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.legacy.level[0].offset);
} else {
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
}
RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
@ -1024,50 +912,43 @@ radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
RADEON_ENC_END();
}
static void
radeon_uvd_enc_op_init(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_op_init(struct radeon_uvd_encoder *enc)
{
RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INITIALIZE);
RADEON_ENC_END();
}
static void
radeon_uvd_enc_op_close(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_op_close(struct radeon_uvd_encoder *enc)
{
RADEON_ENC_BEGIN(RENC_UVD_IB_OP_CLOSE_SESSION);
RADEON_ENC_END();
}
static void
radeon_uvd_enc_op_enc(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_op_enc(struct radeon_uvd_encoder *enc)
{
RADEON_ENC_BEGIN(RENC_UVD_IB_OP_ENCODE);
RADEON_ENC_END();
}
static void
radeon_uvd_enc_op_init_rc(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_op_init_rc(struct radeon_uvd_encoder *enc)
{
RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INIT_RC);
RADEON_ENC_END();
}
static void
radeon_uvd_enc_op_init_rc_vbv(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_op_init_rc_vbv(struct radeon_uvd_encoder *enc)
{
RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
RADEON_ENC_END();
}
static void
radeon_uvd_enc_op_speed(struct radeon_uvd_encoder *enc)
static void radeon_uvd_enc_op_speed(struct radeon_uvd_encoder *enc)
{
RADEON_ENC_BEGIN(RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE);
RADEON_ENC_END();
}
static void
begin(struct radeon_uvd_encoder *enc, struct pipe_picture_desc *pic)
static void begin(struct radeon_uvd_encoder *enc, struct pipe_picture_desc *pic)
{
radeon_uvd_enc_session_info(enc);
enc->total_task_size = 0;
@ -1091,8 +972,7 @@ begin(struct radeon_uvd_encoder *enc, struct pipe_picture_desc *pic)
*enc->p_task_size = (enc->total_task_size);
}
static void
encode(struct radeon_uvd_encoder *enc)
static void encode(struct radeon_uvd_encoder *enc)
{
radeon_uvd_enc_session_info(enc);
enc->total_task_size = 0;
@ -1118,8 +998,7 @@ encode(struct radeon_uvd_encoder *enc)
*enc->p_task_size = (enc->total_task_size);
}
static void
destroy(struct radeon_uvd_encoder *enc)
static void destroy(struct radeon_uvd_encoder *enc)
{
radeon_uvd_enc_session_info(enc);
enc->total_task_size = 0;
@ -1128,8 +1007,7 @@ destroy(struct radeon_uvd_encoder *enc)
*enc->p_task_size = (enc->total_task_size);
}
void
radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder *enc)
void radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder *enc)
{
enc->begin = begin;
enc->encode = encode;

73
src/gallium/drivers/radeon/radeon_vce.c
View File

@ -25,18 +25,16 @@
*
**************************************************************************/
#include <stdio.h>
#include "radeon_vce.h"
#include "pipe/p_video_codec.h"
#include "util/u_video.h"
#include "radeon_video.h"
#include "radeonsi/si_pipe.h"
#include "util/u_memory.h"
#include "util/u_video.h"
#include "vl/vl_video_buffer.h"
#include "radeonsi/si_pipe.h"
#include "radeon_video.h"
#include "radeon_vce.h"
#include <stdio.h>
#define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
#define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8))
@ -119,8 +117,7 @@ static void sort_cpb(struct rvce_encoder *enc)
if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P && l0)
break;
if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B &&
l0 && l1)
if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B && l0 && l1)
break;
}
@ -216,8 +213,8 @@ struct rvce_cpb_slot *si_l1_slot(struct rvce_encoder *enc)
/**
* Calculate the offsets into the CPB
*/
void si_vce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
signed *luma_offset, signed *chroma_offset)
void si_vce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot, signed *luma_offset,
signed *chroma_offset)
{
struct si_screen *sscreen = (struct si_screen *)enc->screen;
unsigned pitch, vpitch, fsize;
@ -256,8 +253,7 @@ static void rvce_destroy(struct pipe_video_codec *encoder)
FREE(enc);
}
static void rvce_begin_frame(struct pipe_video_codec *encoder,
struct pipe_video_buffer *source,
static void rvce_begin_frame(struct pipe_video_codec *encoder, struct pipe_video_buffer *source,
struct pipe_picture_desc *picture)
{
struct rvce_encoder *enc = (struct rvce_encoder *)encoder;
@ -307,8 +303,7 @@ static void rvce_begin_frame(struct pipe_video_codec *encoder,
static void rvce_encode_bitstream(struct pipe_video_codec *encoder,
struct pipe_video_buffer *source,
struct pipe_resource *destination,
void **fb)
struct pipe_resource *destination, void **fb)
{
struct rvce_encoder *enc = (struct rvce_encoder *)encoder;
enc->get_buffer(destination, &enc->bs_handle, NULL);
@ -325,13 +320,11 @@ static void rvce_encode_bitstream(struct pipe_video_codec *encoder,
enc->feedback(enc);
}
static void rvce_end_frame(struct pipe_video_codec *encoder,
struct pipe_video_buffer *source,
static void rvce_end_frame(struct pipe_video_codec *encoder, struct pipe_video_buffer *source,
struct pipe_picture_desc *picture)
{
struct rvce_encoder *enc = (struct rvce_encoder *)encoder;
struct rvce_cpb_slot *slot = LIST_ENTRY(
struct rvce_cpb_slot, enc->cpb_slots.prev, list);
struct rvce_cpb_slot *slot = LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.prev, list);
if (!enc->dual_inst || enc->bs_idx > 1)
flush(enc);
@ -346,15 +339,13 @@ static void rvce_end_frame(struct pipe_video_codec *encoder,
}
}
static void rvce_get_feedback(struct pipe_video_codec *encoder,
void *feedback, unsigned *size)
static void rvce_get_feedback(struct pipe_video_codec *encoder, void *feedback, unsigned *size)
{
struct rvce_encoder *enc = (struct rvce_encoder *)encoder;
struct rvid_buffer *fb = feedback;
if (size) {
uint32_t *ptr = enc->ws->buffer_map(
fb->res->buf, enc->cs,
uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs,
PIPE_TRANSFER_READ_WRITE | RADEON_TRANSFER_TEMPORARY);
if (ptr[1]) {
@ -380,16 +371,14 @@ static void rvce_flush(struct pipe_video_codec *encoder)
flush(enc);
}
static void rvce_cs_flush(void *ctx, unsigned flags,
struct pipe_fence_handle **fence)
static void rvce_cs_flush(void *ctx, unsigned flags, struct pipe_fence_handle **fence)
{
// just ignored
}
struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
const struct pipe_video_codec *templ,
struct radeon_winsys* ws,
rvce_get_buffer get_buffer)
struct radeon_winsys *ws, rvce_get_buffer get_buffer)
{
struct si_screen *sscreen = (struct si_screen *)context->screen;
struct si_context *sctx = (struct si_context *)context;
@ -413,18 +402,14 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
if (sscreen->info.is_amdgpu)
enc->use_vm = true;
if ((!sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 42) ||
sscreen->info.is_amdgpu)
if ((!sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 42) || sscreen->info.is_amdgpu)
enc->use_vui = true;
if (sscreen->info.family >= CHIP_TONGA &&
sscreen->info.family != CHIP_STONEY &&
sscreen->info.family != CHIP_POLARIS11 &&
sscreen->info.family != CHIP_POLARIS12 &&
if (sscreen->info.family >= CHIP_TONGA && sscreen->info.family != CHIP_STONEY &&
sscreen->info.family != CHIP_POLARIS11 && sscreen->info.family != CHIP_POLARIS12 &&
sscreen->info.family != CHIP_VEGAM)
enc->dual_pipe = true;
/* TODO enable B frame with dual instance */
if ((sscreen->info.family >= CHIP_TONGA) &&
(templ->max_references == 1) &&
if ((sscreen->info.family >= CHIP_TONGA) && (templ->max_references == 1) &&
(sscreen->info.vce_harvest_config == 0))
enc->dual_inst = true;
@ -462,9 +447,10 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
cpb_size = (sscreen->info.chip_class < GFX9) ?
align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
align(tmp_surf->u.legacy.level[0].nblk_y, 32) :
cpb_size = (sscreen->info.chip_class < GFX9)
? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
align(tmp_surf->u.legacy.level[0].nblk_y, 32)
:
align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
align(tmp_surf->u.gfx9.surf_height, 32);
@ -472,8 +458,7 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
cpb_size = cpb_size * 3 / 2;
cpb_size = cpb_size * enc->cpb_num;
if (enc->dual_pipe)
cpb_size += RVCE_MAX_AUX_BUFFER_NUM *
RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
cpb_size += RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
tmp_buf->destroy(tmp_buf);
if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't create CPB buffer.\n");
@ -550,14 +535,12 @@ bool si_vce_is_fw_version_supported(struct si_screen *sscreen)
/**
* Add the buffer as relocation to the current command submission
*/
void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
enum radeon_bo_usage usage, enum radeon_bo_domain domain,
signed offset)
void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf, enum radeon_bo_usage usage,
enum radeon_bo_domain domain, signed offset)
{
int reloc_idx;
reloc_idx = enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
domain, 0);
reloc_idx = enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
if (enc->use_vm) {
uint64_t addr;
addr = enc->ws->buffer_get_virtual_address(buf);

51
src/gallium/drivers/radeon/radeon_vce.h
View File

@ -28,17 +28,23 @@
#ifndef RADEON_VCE_H
#define RADEON_VCE_H
#include "util/list.h"
#include "radeon_video.h"
#include "util/list.h"
#define RVCE_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
#define RVCE_BEGIN(cmd) { \
#define RVCE_BEGIN(cmd) \
{ \
uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
RVCE_CS(cmd)
#define RVCE_READ(buf, domain, off) si_vce_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
#define RVCE_WRITE(buf, domain, off) si_vce_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
#define RVCE_READWRITE(buf, domain, off) si_vce_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
#define RVCE_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; }
#define RVCE_READ(buf, domain, off) \
si_vce_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
#define RVCE_WRITE(buf, domain, off) \
si_vce_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
#define RVCE_READWRITE(buf, domain, off) \
si_vce_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
#define RVCE_END() \
*begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
}
#define RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE (4096 * 16 * 2.5)
#define RVCE_MAX_AUX_BUFFER_NUM 4
@ -46,8 +52,7 @@
struct si_screen;
/* driver dependent callback */
typedef void (*rvce_get_buffer)(struct pipe_resource *resource,
struct pb_buffer **handle,
typedef void (*rvce_get_buffer)(struct pipe_resource *resource, struct pb_buffer **handle,
struct radeon_surf **surface);
/* Coded picture buffer slot */
@ -239,7 +244,8 @@ struct rvce_enc_operation {
uint32_t input_picture_chroma_address_lo;
uint32_t enc_input_frame_y_pitch;
uint32_t enc_input_pic_luma_pitch;
uint32_t enc_input_pic_chroma_pitch;;
uint32_t enc_input_pic_chroma_pitch;
;
uint32_t enc_input_pic_addr_array;
uint32_t enc_input_pic_addr_array_disable2pipe_disablemboffload;
uint32_t enc_input_pic_tile_config;
@ -272,7 +278,8 @@ struct rvce_enc_operation {
uint32_t l1_luma_offset;
uint32_t l1_chroma_offset;
uint32_t enc_reconstructed_luma_offset;
uint32_t enc_reconstructed_chroma_offset;;
uint32_t enc_reconstructed_chroma_offset;
;
uint32_t enc_coloc_buffer_offset;
uint32_t enc_reconstructed_ref_base_picture_luma_offset;
uint32_t enc_reconstructed_ref_base_picture_chroma_offset;
@ -374,11 +381,9 @@ struct rvce_encoder {
void (*config)(struct rvce_encoder *enc);
void (*encode)(struct rvce_encoder *enc);
void (*destroy)(struct rvce_encoder *enc);
void (*task_info)(struct rvce_encoder *enc, uint32_t op,
uint32_t dep, uint32_t fb_idx,
void (*task_info)(struct rvce_encoder *enc, uint32_t op, uint32_t dep, uint32_t fb_idx,
uint32_t ring_idx);
void (*si_get_pic_param)(struct rvce_encoder *enc,
struct pipe_h264_enc_picture_desc *pic);
void (*si_get_pic_param)(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic);
unsigned stream_handle;
@ -417,8 +422,8 @@ struct rvce_encoder {
struct rvce_cpb_slot *si_current_slot(struct rvce_encoder *enc);
struct rvce_cpb_slot *si_l0_slot(struct rvce_encoder *enc);
struct rvce_cpb_slot *si_l1_slot(struct rvce_encoder *enc);
void si_vce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
signed *luma_offset, signed *chroma_offset);
void si_vce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot, signed *luma_offset,
signed *chroma_offset);
struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
const struct pipe_video_codec *templat,
@ -427,9 +432,8 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
bool si_vce_is_fw_version_supported(struct si_screen *sscreen);
void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
enum radeon_bo_usage usage, enum radeon_bo_domain domain,
signed offset);
void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf, enum radeon_bo_usage usage,
enum radeon_bo_domain domain, signed offset);
/* init vce fw 40.2.2 specific callbacks */
void si_vce_40_2_2_init(struct rvce_encoder *enc);
@ -441,15 +445,12 @@ void si_vce_50_init(struct rvce_encoder *enc);
void si_vce_52_init(struct rvce_encoder *enc);
/* get parameters for vce 40.2.2 */
void si_vce_40_2_2_get_param(struct rvce_encoder *enc,
struct pipe_h264_enc_picture_desc *pic);
void si_vce_40_2_2_get_param(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic);
/* get parameters for vce 50 */
void si_vce_50_get_param(struct rvce_encoder *enc,
struct pipe_h264_enc_picture_desc *pic);
void si_vce_50_get_param(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic);
/* get parameters for vce 52 */
void si_vce_52_get_param(struct rvce_encoder *enc,
struct pipe_h264_enc_picture_desc *pic);
void si_vce_52_get_param(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic);
#endif

17
src/gallium/drivers/radeon/radeon_vce_40_2_2.c
View File

@ -25,18 +25,15 @@
*
**************************************************************************/
#include <stdio.h>
#include "pipe/p_video_codec.h"
#include "util/u_video.h"
#include "radeon_vce.h"
#include "radeon_video.h"
#include "si_pipe.h"
#include "util/u_memory.h"
#include "util/u_video.h"
#include "vl/vl_video_buffer.h"
#include "si_pipe.h"
#include "radeon_video.h"
#include "radeon_vce.h"
#include <stdio.h>
static void session(struct rvce_encoder *enc)
{
@ -45,8 +42,8 @@ static void session(struct rvce_encoder *enc)
RVCE_END();
}
static void task_info(struct rvce_encoder *enc, uint32_t op,
uint32_t dep, uint32_t fb_idx, uint32_t ring_idx)
static void task_info(struct rvce_encoder *enc, uint32_t op, uint32_t dep, uint32_t fb_idx,
uint32_t ring_idx)
{
RVCE_BEGIN(0x00000002); // task info
if (op == 0x3) {

17
src/gallium/drivers/radeon/radeon_vce_50.c
View File

@ -25,18 +25,15 @@
*
**************************************************************************/
#include <stdio.h>
#include "pipe/p_video_codec.h"
#include "util/u_video.h"
#include "radeon_vce.h"
#include "radeon_video.h"
#include "si_pipe.h"
#include "util/u_memory.h"
#include "util/u_video.h"
#include "vl/vl_video_buffer.h"
#include "si_pipe.h"
#include "radeon_video.h"
#include "radeon_vce.h"
#include <stdio.h>
static void rate_control(struct rvce_encoder *enc)
{
@ -100,8 +97,8 @@ static void encode(struct rvce_encoder *enc)
RVCE_END();
if (enc->dual_pipe) {
unsigned aux_offset = enc->cpb.res->buf->size -
RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
unsigned aux_offset =
enc->cpb.res->buf->size - RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
RVCE_BEGIN(0x05000002); // auxiliary buffer
for (i = 0; i < 8; ++i) {
RVCE_CS(aux_offset);

30
src/gallium/drivers/radeon/radeon_vce_52.c
View File

@ -25,18 +25,15 @@
*
**************************************************************************/
#include <stdio.h>
#include "pipe/p_video_codec.h"
#include "util/u_video.h"
#include "radeon_vce.h"
#include "radeon_video.h"
#include "radeonsi/si_pipe.h"
#include "util/u_memory.h"
#include "util/u_video.h"
#include "vl/vl_video_buffer.h"
#include "radeonsi/si_pipe.h"
#include "radeon_video.h"
#include "radeon_vce.h"
#include <stdio.h>
static void get_rate_control_param(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic)
{
@ -59,7 +56,8 @@ static void get_rate_control_param(struct rvce_encoder *enc, struct pipe_h264_en
enc->enc_pic.rc.peak_bits_picture_fraction = pic->rate_ctrl.peak_bits_picture_fraction;
}
static void get_motion_estimation_param(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic)
static void get_motion_estimation_param(struct rvce_encoder *enc,
struct pipe_h264_enc_picture_desc *pic)
{
enc->enc_pic.me.motion_est_quarter_pixel = pic->motion_est.motion_est_quarter_pixel;
enc->enc_pic.me.enc_disable_sub_mode = pic->motion_est.enc_disable_sub_mode;
@ -88,7 +86,8 @@ static void get_pic_control_param(struct rvce_encoder *enc, struct pipe_h264_enc
enc->enc_pic.pc.enc_crop_bottom_offset = pic->pic_ctrl.enc_frame_crop_bottom_offset;
} else {
enc->enc_pic.pc.enc_crop_right_offset = (align(enc->base.width, 16) - enc->base.width) >> 1;
enc->enc_pic.pc.enc_crop_bottom_offset = (align(enc->base.height, 16) - enc->base.height) >> 1;
enc->enc_pic.pc.enc_crop_bottom_offset =
(align(enc->base.height, 16) - enc->base.height) >> 1;
}
enc->enc_pic.pc.enc_num_mbs_per_slice = encNumMBsPerSlice;
enc->enc_pic.pc.enc_b_pic_pattern = MAX2(enc->base.max_references, 1) - 1;
@ -233,8 +232,8 @@ static void encode(struct rvce_encoder *enc)
RVCE_END();
if (enc->dual_pipe) {
unsigned aux_offset = enc->cpb.res->buf->size -
RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
unsigned aux_offset =
enc->cpb.res->buf->size - RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
RVCE_BEGIN(0x05000002); // auxiliary buffer
for (i = 0; i < 8; ++i) {
RVCE_CS(aux_offset);
@ -280,7 +279,8 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(enc->enc_pic.eo.enc_input_pic_tile_config);
RVCE_CS(enc->enc_pic.picture_type); // encPicType
RVCE_CS(enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR); // encIdrFlag
if ((enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR) && (enc->enc_pic.eo.enc_idr_pic_id !=0))
if ((enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR) &&
(enc->enc_pic.eo.enc_idr_pic_id != 0))
enc->enc_pic.eo.enc_idr_pic_id = enc->enc_pic.idr_pic_id - 1;
else
enc->enc_pic.eo.enc_idr_pic_id = 0x00000000;
@ -573,8 +573,8 @@ static void session(struct rvce_encoder *enc)
RVCE_END();
}
static void task_info(struct rvce_encoder *enc, uint32_t op,
uint32_t dep, uint32_t fb_idx, uint32_t ring_idx)
static void task_info(struct rvce_encoder *enc, uint32_t op, uint32_t dep, uint32_t fb_idx,
uint32_t ring_idx)
{
RVCE_BEGIN(0x00000002); // task info
if (op == 0x3) {

240
src/gallium/drivers/radeon/radeon_vcn_dec.c
View File

@ -25,21 +25,19 @@
*
**************************************************************************/
#include <assert.h>
#include <stdio.h>
#include "radeon_vcn_dec.h"
#include "pipe/p_video_codec.h"
#include "radeon_video.h"
#include "radeonsi/si_pipe.h"
#include "util/u_memory.h"
#include "util/u_video.h"
#include "vl/vl_mpeg12_decoder.h"
#include "radeonsi/si_pipe.h"
#include "radeon_video.h"
#include "radeon_vcn_dec.h"
#include "vl/vl_probs_table.h"
#include <assert.h>
#include <stdio.h>
#define FB_BUFFER_OFFSET 0x1000
#define FB_BUFFER_SIZE 2048
#define IT_SCALING_TABLE_SIZE 992
@ -104,8 +102,7 @@ static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
result.log2_max_frame_num_minus4 = pic->pps->sps->log2_max_frame_num_minus4;
result.pic_order_cnt_type = pic->pps->sps->pic_order_cnt_type;
result.log2_max_pic_order_cnt_lsb_minus4 =
pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
switch (dec->base.chroma_format) {
case PIPE_VIDEO_CHROMA_FORMAT_NONE:
@ -204,13 +201,10 @@ static rvcn_dec_message_hevc_t get_h265_msg(struct radeon_decoder *dec,
pic->pps->sps->log2_min_transform_block_size_minus2;
result.log2_diff_max_min_transform_block_size =
pic->pps->sps->log2_diff_max_min_transform_block_size;
result.max_transform_hierarchy_depth_inter =
pic->pps->sps->max_transform_hierarchy_depth_inter;
result.max_transform_hierarchy_depth_intra =
pic->pps->sps->max_transform_hierarchy_depth_intra;
result.max_transform_hierarchy_depth_inter = pic->pps->sps->max_transform_hierarchy_depth_inter;
result.max_transform_hierarchy_depth_intra = pic->pps->sps->max_transform_hierarchy_depth_intra;
result.pcm_sample_bit_depth_luma_minus1 = pic->pps->sps->pcm_sample_bit_depth_luma_minus1;
result.pcm_sample_bit_depth_chroma_minus1 =
pic->pps->sps->pcm_sample_bit_depth_chroma_minus1;
result.pcm_sample_bit_depth_chroma_minus1 = pic->pps->sps->pcm_sample_bit_depth_chroma_minus1;
result.log2_min_pcm_luma_coding_block_size_minus3 =
pic->pps->sps->log2_min_pcm_luma_coding_block_size_minus3;
result.log2_diff_max_min_pcm_luma_coding_block_size =
@ -280,8 +274,7 @@ static rvcn_dec_message_hevc_t get_h265_msg(struct radeon_decoder *dec,
}
}
vl_video_buffer_set_associated_data(target, &dec->base,
(void *)(uintptr_t)result.curr_idx,
vl_video_buffer_set_associated_data(target, &dec->base, (void *)(uintptr_t)result.curr_idx,
&radeon_dec_destroy_associated_data);
for (i = 0; i < 16; ++i) {
@ -329,8 +322,7 @@ static rvcn_dec_message_hevc_t get_h265_msg(struct radeon_decoder *dec,
}
if (pic->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
if (target->buffer_format == PIPE_FORMAT_P010 ||
target->buffer_format == PIPE_FORMAT_P016) {
if (target->buffer_format == PIPE_FORMAT_P010 || target->buffer_format == PIPE_FORMAT_P016) {
result.p010_mode = 1;
result.msb_mode = 1;
} else {
@ -356,7 +348,8 @@ static void fill_probs_table(void *ptr)
memcpy(probs->y_mode_prob, default_if_y_probs, sizeof(default_if_y_probs));
memcpy(probs->uv_mode_prob, default_if_uv_probs, sizeof(default_if_uv_probs));
memcpy(probs->single_ref_prob, default_single_ref_p, sizeof(default_single_ref_p));
memcpy(probs->switchable_interp_prob, default_switchable_interp_prob, sizeof(default_switchable_interp_prob));
memcpy(probs->switchable_interp_prob, default_switchable_interp_prob,
sizeof(default_switchable_interp_prob));
memcpy(probs->partition_prob, default_partition_probs, sizeof(default_partition_probs));
memcpy(probs->inter_mode_probs, default_inter_mode_probs, sizeof(default_inter_mode_probs));
memcpy(probs->mbskip_probs, default_skip_probs, sizeof(default_skip_probs));
@ -406,63 +399,52 @@ static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec,
} else
memset(&prbs->seg, 0, 256);
result.frame_header_flags =
(pic->picture_parameter.pic_fields.frame_type <<
RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_SHIFT) &
result.frame_header_flags = (pic->picture_parameter.pic_fields.frame_type
<< RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_SHIFT) &
RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_MASK;
result.frame_header_flags |=
(pic->picture_parameter.pic_fields.error_resilient_mode <<
RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_SHIFT) &
result.frame_header_flags |= (pic->picture_parameter.pic_fields.error_resilient_mode
<< RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_SHIFT) &
RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_MASK;
result.frame_header_flags |=
(pic->picture_parameter.pic_fields.intra_only <<
RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_SHIFT) &
result.frame_header_flags |= (pic->picture_parameter.pic_fields.intra_only
<< RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_SHIFT) &
RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_MASK;
result.frame_header_flags |=
(pic->picture_parameter.pic_fields.allow_high_precision_mv <<
RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_SHIFT) &
result.frame_header_flags |= (pic->picture_parameter.pic_fields.allow_high_precision_mv
<< RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_SHIFT) &
RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_MASK;
result.frame_header_flags |=
(pic->picture_parameter.pic_fields.frame_parallel_decoding_mode <<
RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_SHIFT) &
result.frame_header_flags |= (pic->picture_parameter.pic_fields.frame_parallel_decoding_mode
<< RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_SHIFT) &
RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_MASK;
result.frame_header_flags |=
(pic->picture_parameter.pic_fields.refresh_frame_context <<
RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_SHIFT) &
result.frame_header_flags |= (pic->picture_parameter.pic_fields.refresh_frame_context
<< RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_SHIFT) &
RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_MASK;
result.frame_header_flags |=
(pic->picture_parameter.pic_fields.segmentation_enabled <<
RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_SHIFT) &
result.frame_header_flags |= (pic->picture_parameter.pic_fields.segmentation_enabled
<< RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_SHIFT) &
RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_MASK;
result.frame_header_flags |=
(pic->picture_parameter.pic_fields.segmentation_update_map <<
RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_SHIFT) &
result.frame_header_flags |= (pic->picture_parameter.pic_fields.segmentation_update_map
<< RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_SHIFT) &
RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_MASK;
result.frame_header_flags |=
(pic->picture_parameter.pic_fields.segmentation_temporal_update <<
RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_SHIFT) &
result.frame_header_flags |= (pic->picture_parameter.pic_fields.segmentation_temporal_update
<< RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_SHIFT) &
RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_MASK;
result.frame_header_flags |=
(pic->picture_parameter.mode_ref_delta_enabled <<
RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_SHIFT) &
result.frame_header_flags |= (pic->picture_parameter.mode_ref_delta_enabled
<< RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_SHIFT) &
RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_MASK;
result.frame_header_flags |=
(pic->picture_parameter.mode_ref_delta_update <<
RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_SHIFT) &
result.frame_header_flags |= (pic->picture_parameter.mode_ref_delta_update
<< RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_SHIFT) &
RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_MASK;
result.frame_header_flags |= ((dec->show_frame &&
!pic->picture_parameter.pic_fields.error_resilient_mode)
result.frame_header_flags |=
((dec->show_frame && !pic->picture_parameter.pic_fields.error_resilient_mode)
<< RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_SHIFT) &
RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_MASK;
dec->show_frame = pic->picture_parameter.pic_fields.show_frame;
@ -493,8 +475,8 @@ static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec,
result.log2_tile_cols = pic->picture_parameter.log2_tile_columns;
result.log2_tile_rows = pic->picture_parameter.log2_tile_rows;
result.chroma_format = 1;
result.bit_depth_luma_minus8 = result.bit_depth_chroma_minus8
= (pic->picture_parameter.bit_depth - 8);
result.bit_depth_luma_minus8 = result.bit_depth_chroma_minus8 =
(pic->picture_parameter.bit_depth - 8);
result.vp9_frame_size = align(dec->bs_size, 128);
result.uncompressed_header_size = pic->picture_parameter.frame_header_length_in_bytes;
@ -504,23 +486,21 @@ static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec,
for (i = 0; i < 16; ++i) {
if (dec->render_pic_list[i] && dec->render_pic_list[i] == target) {
result.curr_pic_idx =
(uintptr_t)vl_video_buffer_get_associated_data(target, &dec->base);
result.curr_pic_idx = (uintptr_t)vl_video_buffer_get_associated_data(target, &dec->base);
break;
} else if (!dec->render_pic_list[i]) {
dec->render_pic_list[i] = target;
result.curr_pic_idx = dec->ref_idx;
vl_video_buffer_set_associated_data(target, &dec->base,
(void *)(uintptr_t)dec->ref_idx++,
vl_video_buffer_set_associated_data(target, &dec->base, (void *)(uintptr_t)dec->ref_idx++,
&radeon_dec_destroy_associated_data);
break;
}
}
for (i = 0; i < 8; i++) {
result.ref_frame_map[i] = (pic->ref[i]) ?
(uintptr_t)vl_video_buffer_get_associated_data(pic->ref[i], &dec->base) :
0x7f;
result.ref_frame_map[i] =
(pic->ref[i]) ? (uintptr_t)vl_video_buffer_get_associated_data(pic->ref[i], &dec->base)
: 0x7f;
}
result.frame_refs[0] = result.ref_frame_map[pic->picture_parameter.pic_fields.last_ref_frame];
@ -531,8 +511,7 @@ static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec,
result.ref_frame_sign_bias[2] = pic->picture_parameter.pic_fields.alt_ref_frame_sign_bias;
if (pic->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2) {
if (target->buffer_format == PIPE_FORMAT_P010 ||
target->buffer_format == PIPE_FORMAT_P016) {
if (target->buffer_format == PIPE_FORMAT_P010 || target->buffer_format == PIPE_FORMAT_P016) {
result.p010_mode = 1;
result.msb_mode = 1;
} else {
@ -562,7 +541,8 @@ static unsigned calc_ctx_size_h265_main(struct radeon_decoder *dec)
return ((width + 255) / 16) * ((height + 255) / 16) * 16 * max_references + 52 * 1024;
}
static unsigned calc_ctx_size_h265_main10(struct radeon_decoder *dec, struct pipe_h265_picture_desc *pic)
static unsigned calc_ctx_size_h265_main10(struct radeon_decoder *dec,
struct pipe_h265_picture_desc *pic)
{
unsigned log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
@ -570,8 +550,8 @@ static unsigned calc_ctx_size_h265_main10(struct radeon_decoder *dec, struct pip
unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
unsigned coeff_10bit = (pic->pps->sps->bit_depth_luma_minus8 ||
pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
unsigned coeff_10bit =
(pic->pps->sps->bit_depth_luma_minus8 || pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
unsigned max_references = dec->base.max_references + 1;
@ -790,10 +770,9 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
struct pipe_video_buffer *target,
struct pipe_picture_desc *picture)
{
struct si_texture *luma = (struct si_texture *)
((struct vl_video_buffer *)target)->resources[0];
struct si_texture *chroma = (struct si_texture *)
((struct vl_video_buffer *)target)->resources[1];
struct si_texture *luma = (struct si_texture *)((struct vl_video_buffer *)target)->resources[0];
struct si_texture *chroma =
(struct si_texture *)((struct vl_video_buffer *)target)->resources[1];
rvcn_dec_message_header_t *header;
rvcn_dec_message_index_t *index;
rvcn_dec_message_decode_t *decode;
@ -834,8 +813,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->bsd_size = align(dec->bs_size, 128);
decode->dpb_size = dec->dpb.res->buf->size;
decode->dt_size =
si_resource(((struct vl_video_buffer *)target)->resources[0])->buf->size +
decode->dt_size = si_resource(((struct vl_video_buffer *)target)->resources[0])->buf->size +
si_resource(((struct vl_video_buffer *)target)->resources[1])->buf->size;
decode->sct_size = 0;
@ -843,9 +821,9 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
decode->db_pitch = (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR &&
dec->base.width > 32 && dec->stream_type == RDECODE_CODEC_VP9) ?
align(dec->base.width, 64) :
align(dec->base.width, 32) ;
dec->base.width > 32 && dec->stream_type == RDECODE_CODEC_VP9)
? align(dec->base.width, 64)
: align(dec->base.width, 32);
decode->db_surf_tile_config = 0;
decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
@ -861,10 +839,10 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->dt_luma_top_offset = luma->surface.u.gfx9.surf_offset;
decode->dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
if (decode->dt_field_mode) {
decode->dt_luma_bottom_offset = luma->surface.u.gfx9.surf_offset +
luma->surface.u.gfx9.surf_slice_size;
decode->dt_chroma_bottom_offset = chroma->surface.u.gfx9.surf_offset +
chroma->surface.u.gfx9.surf_slice_size;
decode->dt_luma_bottom_offset =
luma->surface.u.gfx9.surf_offset + luma->surface.u.gfx9.surf_slice_size;
decode->dt_chroma_bottom_offset =
chroma->surface.u.gfx9.surf_offset + chroma->surface.u.gfx9.surf_slice_size;
} else {
decode->dt_luma_bottom_offset = decode->dt_luma_top_offset;
decode->dt_chroma_bottom_offset = decode->dt_chroma_top_offset;
@ -872,8 +850,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
switch (u_reduce_video_profile(picture->profile)) {
case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
rvcn_dec_message_avc_t avc =
get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
rvcn_dec_message_avc_t avc = get_h264_msg(dec, (struct pipe_h264_picture_desc *)picture);
memcpy(codec, (void *)&avc, sizeof(rvcn_dec_message_avc_t));
index->message_id = RDECODE_MESSAGE_AVC;
break;
@ -887,8 +864,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
if (dec->ctx.res == NULL) {
unsigned ctx_size;
if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
ctx_size = calc_ctx_size_h265_main10(dec,
(struct pipe_h265_picture_desc*)picture);
ctx_size = calc_ctx_size_h265_main10(dec, (struct pipe_h265_picture_desc *)picture);
else
ctx_size = calc_ctx_size_h265_main(dec);
if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT))
@ -908,7 +884,6 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
}
index->message_id = RDECODE_MESSAGE_VC1;
break;
}
case PIPE_VIDEO_FORMAT_MPEG12: {
rvcn_dec_message_mpeg2_vld_t mpeg2 =
@ -961,8 +936,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
si_vid_clear_buffer(dec->base.context, &dec->ctx);
/* ctx needs probs table */
ptr = dec->ws->buffer_map(
dec->ctx.res->buf, dec->cs,
ptr = dec->ws->buffer_map(dec->ctx.res->buf, dec->cs,
PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
fill_probs_table(ptr);
dec->ws->buffer_unmap(dec->ctx.res->buf);
@ -986,8 +960,7 @@ static void rvcn_dec_message_destroy(struct radeon_decoder *dec)
memset(dec->msg, 0, sizeof(rvcn_dec_message_header_t));
header->header_size = sizeof(rvcn_dec_message_header_t);
header->total_size = sizeof(rvcn_dec_message_header_t) -
sizeof(rvcn_dec_message_index_t);
header->total_size = sizeof(rvcn_dec_message_header_t) - sizeof(rvcn_dec_message_index_t);
header->num_buffers = 0;
header->msg_type = RDECODE_MSG_DESTROY;
header->stream_handle = dec->stream_handle;
@ -1017,14 +990,12 @@ static void set_reg(struct radeon_decoder *dec, unsigned reg, uint32_t val)
}
/* send a command to the VCPU through the GPCOM registers */
static void send_cmd(struct radeon_decoder *dec, unsigned cmd,
struct pb_buffer* buf, uint32_t off,
static void send_cmd(struct radeon_decoder *dec, unsigned cmd, struct pb_buffer *buf, uint32_t off,
enum radeon_bo_usage usage, enum radeon_bo_domain domain)
{
uint64_t addr;
dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
domain, 0);
dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
@ -1036,8 +1007,7 @@ static void send_cmd(struct radeon_decoder *dec, unsigned cmd,
/* do the codec needs an IT buffer ?*/
static bool have_it(struct radeon_decoder *dec)
{
return dec->stream_type == RDECODE_CODEC_H264_PERF ||
dec->stream_type == RDECODE_CODEC_H265;
return dec->stream_type == RDECODE_CODEC_H264_PERF || dec->stream_type == RDECODE_CODEC_H265;
}
/* do the codec needs an probs buffer? */
@ -1056,8 +1026,8 @@ static void map_msg_fb_it_probs_buf(struct radeon_decoder *dec)
buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
/* and map it for CPU access */
ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
ptr =
dec->ws->buffer_map(buf->res->buf, dec->cs, PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
/* calc buffer offsets */
dec->msg = ptr;
@ -1089,13 +1059,11 @@ static void send_msg_buf(struct radeon_decoder *dec)
dec->probs = NULL;
if (dec->sessionctx.res)
send_cmd(dec, RDECODE_CMD_SESSION_CONTEXT_BUFFER,
dec->sessionctx.res->buf, 0, RADEON_USAGE_READWRITE,
RADEON_DOMAIN_VRAM);
send_cmd(dec, RDECODE_CMD_SESSION_CONTEXT_BUFFER, dec->sessionctx.res->buf, 0,
RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
/* and send it to the hardware */
send_cmd(dec, RDECODE_CMD_MSG_BUFFER, buf->res->buf, 0,
RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd(dec, RDECODE_CMD_MSG_BUFFER, buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
}
/* cycle to the next set of buffers */
@ -1265,9 +1233,9 @@ static unsigned calc_dpb_size(struct radeon_decoder *dec)
case PIPE_VIDEO_FORMAT_VP9:
max_references = MAX2(max_references, 9);
dpb_size = (((struct si_screen*)dec->screen)->info.family >= CHIP_RENOIR) ?
(8192 * 4320 * 3 / 2) * max_references :
(4096 * 3000 * 3 / 2) * max_references;
dpb_size = (((struct si_screen *)dec->screen)->info.family >= CHIP_RENOIR)
? (8192 * 4320 * 3 / 2) * max_references
: (4096 * 3000 * 3 / 2) * max_references;
if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
dpb_size *= (3 / 2);
@ -1336,9 +1304,8 @@ static void radeon_dec_begin_frame(struct pipe_video_codec *decoder,
&radeon_dec_destroy_associated_data);
dec->bs_size = 0;
dec->bs_ptr = dec->ws->buffer_map(
dec->bs_buffers[dec->cur_buffer].res->buf,
dec->cs, PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
dec->bs_ptr = dec->ws->buffer_map(dec->bs_buffers[dec->cur_buffer].res->buf, dec->cs,
PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
}
/**
@ -1359,10 +1326,8 @@ static void radeon_dec_decode_macroblock(struct pipe_video_codec *decoder,
*/
static void radeon_dec_decode_bitstream(struct pipe_video_codec *decoder,
struct pipe_video_buffer *target,
struct pipe_picture_desc *picture,
unsigned num_buffers,
const void * const *buffers,
const unsigned *sizes)
struct pipe_picture_desc *picture, unsigned num_buffers,
const void *const *buffers, const unsigned *sizes)
{
struct radeon_decoder *dec = (struct radeon_decoder *)decoder;
unsigned i;
@ -1383,8 +1348,7 @@ static void radeon_dec_decode_bitstream(struct pipe_video_codec *decoder,
return;
}
dec->bs_ptr = dec->ws->buffer_map(
buf->res->buf, dec->cs,
dec->bs_ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
if (!dec->bs_ptr)
return;
@ -1401,8 +1365,7 @@ static void radeon_dec_decode_bitstream(struct pipe_video_codec *decoder,
/**
* send cmd for vcn dec
*/
void send_cmd_dec(struct radeon_decoder *dec,
struct pipe_video_buffer *target,
void send_cmd_dec(struct radeon_decoder *dec, struct pipe_video_buffer *target,
struct pipe_picture_desc *picture)
{
struct pb_buffer *dt;
@ -1419,17 +1382,16 @@ void send_cmd_dec(struct radeon_decoder *dec,
rvcn_dec_message_feedback(dec);
send_msg_buf(dec);
send_cmd(dec, RDECODE_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
send_cmd(dec, RDECODE_CMD_DPB_BUFFER, dec->dpb.res->buf, 0, RADEON_USAGE_READWRITE,
RADEON_DOMAIN_VRAM);
if (dec->ctx.res)
send_cmd(dec, RDECODE_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0,
RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
send_cmd(dec, RDECODE_CMD_BITSTREAM_BUFFER, bs_buf->res->buf,
0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd(dec, RDECODE_CMD_DECODING_TARGET_BUFFER, dt, 0,
RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
send_cmd(dec, RDECODE_CMD_FEEDBACK_BUFFER, msg_fb_it_probs_buf->res->buf,
FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
send_cmd(dec, RDECODE_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0, RADEON_USAGE_READWRITE,
RADEON_DOMAIN_VRAM);
send_cmd(dec, RDECODE_CMD_BITSTREAM_BUFFER, bs_buf->res->buf, 0, RADEON_USAGE_READ,
RADEON_DOMAIN_GTT);
send_cmd(dec, RDECODE_CMD_DECODING_TARGET_BUFFER, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
send_cmd(dec, RDECODE_CMD_FEEDBACK_BUFFER, msg_fb_it_probs_buf->res->buf, FB_BUFFER_OFFSET,
RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
if (have_it(dec))
send_cmd(dec, RDECODE_CMD_IT_SCALING_TABLE_BUFFER, msg_fb_it_probs_buf->res->buf,
FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
@ -1442,8 +1404,7 @@ void send_cmd_dec(struct radeon_decoder *dec,
/**
* end decoding of the current frame
*/
static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
struct pipe_video_buffer *target,
static void radeon_dec_end_frame(struct pipe_video_codec *decoder, struct pipe_video_buffer *target,
struct pipe_picture_desc *picture)
{
struct radeon_decoder *dec = (struct radeon_decoder *)decoder;
@ -1549,14 +1510,14 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
else if (have_probs(dec))
msg_fb_it_probs_size += VP9_PROBS_TABLE_SIZE;
/* use vram to improve performance, workaround an unknown bug */
if (!si_vid_create_buffer(dec->screen, &dec->msg_fb_it_probs_buffers[i],
msg_fb_it_probs_size, PIPE_USAGE_DEFAULT)) {
if (!si_vid_create_buffer(dec->screen, &dec->msg_fb_it_probs_buffers[i], msg_fb_it_probs_size,
PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't allocated message buffers.\n");
goto error;
}
if (!si_vid_create_buffer(dec->screen, &dec->bs_buffers[i],
bs_buf_size, PIPE_USAGE_STAGING)) {
if (!si_vid_create_buffer(dec->screen, &dec->bs_buffers[i], bs_buf_size,
PIPE_USAGE_STAGING)) {
RVID_ERR("Can't allocated bitstream buffers.\n");
goto error;
}
@ -1569,8 +1530,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
void *ptr;
buf = &dec->msg_fb_it_probs_buffers[i];
ptr = dec->ws->buffer_map(
buf->res->buf, dec->cs,
ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
ptr += FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
fill_probs_table(ptr);
@ -1596,8 +1556,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
si_vid_clear_buffer(context, &dec->ctx);
}
if (!si_vid_create_buffer(dec->screen, &dec->sessionctx,
RDECODE_SESSION_CONTEXT_SIZE,
if (!si_vid_create_buffer(dec->screen, &dec->sessionctx, RDECODE_SESSION_CONTEXT_SIZE,
PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't allocated session ctx.\n");
goto error;
@ -1641,7 +1600,8 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
return &dec->base;
error:
if (dec->cs) dec->ws->cs_destroy(dec->cs);
if (dec->cs)
dec->ws->cs_destroy(dec->cs);
for (i = 0; i < NUM_BUFFERS; ++i) {
si_vid_destroy_buffer(&dec->msg_fb_it_probs_buffers[i]);

19
src/gallium/drivers/radeon/radeon_vcn_dec.h
View File

@ -39,9 +39,8 @@
#define RDECODE_PKT0_BASE_INDEX_S(x) (((unsigned)(x)&0xFFFF) << 0)
#define RDECODE_PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF)
#define RDECODE_PKT0_BASE_INDEX_C 0xFFFF0000
#define RDECODE_PKT0(index, count) (RDECODE_PKT_TYPE_S(0) | \
RDECODE_PKT0_BASE_INDEX_S(index) | \
RDECODE_PKT_COUNT_S(count))
#define RDECODE_PKT0(index, count) \
(RDECODE_PKT_TYPE_S(0) | RDECODE_PKT0_BASE_INDEX_S(index) | RDECODE_PKT_COUNT_S(count))
#define RDECODE_PKT2() (RDECODE_PKT_TYPE_S(2))
@ -49,9 +48,8 @@
#define RDECODE_PKT_RES_J(x) (((unsigned)(x)&0x3F) << 18)
#define RDECODE_PKT_COND_J(x) (((unsigned)(x)&0xF) << 24)
#define RDECODE_PKT_TYPE_J(x) (((unsigned)(x)&0xF) << 28)
#define RDECODE_PKTJ(reg, cond, type) (RDECODE_PKT_REG_J(reg) | \
RDECODE_PKT_RES_J(0) | \
RDECODE_PKT_COND_J(cond) | \
#define RDECODE_PKTJ(reg, cond, type) \
(RDECODE_PKT_REG_J(reg) | RDECODE_PKT_RES_J(0) | RDECODE_PKT_COND_J(cond) | \
RDECODE_PKT_TYPE_J(type))
#define RDECODE_CMD_MSG_BUFFER 0x00000000
@ -793,17 +791,14 @@ struct radeon_decoder {
unsigned cntl;
} reg;
struct jpeg_params jpg;
void (*send_cmd)(struct radeon_decoder *dec,
struct pipe_video_buffer *target,
void (*send_cmd)(struct radeon_decoder *dec, struct pipe_video_buffer *target,
struct pipe_picture_desc *picture);
};
void send_cmd_dec(struct radeon_decoder *dec,
struct pipe_video_buffer *target,
void send_cmd_dec(struct radeon_decoder *dec, struct pipe_video_buffer *target,
struct pipe_picture_desc *picture);
void send_cmd_jpeg(struct radeon_decoder *dec,
struct pipe_video_buffer *target,
void send_cmd_jpeg(struct radeon_decoder *dec, struct pipe_video_buffer *target,
struct pipe_picture_desc *picture);
struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,

77
src/gallium/drivers/radeon/radeon_vcn_dec_jpeg.c
View File

@ -25,26 +25,23 @@
*
**************************************************************************/
#include <assert.h>
#include <stdio.h>
#include "pipe/p_video_codec.h"
#include "radeon_vcn_dec.h"
#include "radeon_video.h"
#include "radeonsi/si_pipe.h"
#include "util/u_memory.h"
#include "util/u_video.h"
#include "radeonsi/si_pipe.h"
#include "radeon_video.h"
#include "radeon_vcn_dec.h"
#include <assert.h>
#include <stdio.h>
static struct pb_buffer *radeon_jpeg_get_decode_param(struct radeon_decoder *dec,
struct pipe_video_buffer *target,
struct pipe_picture_desc *picture)
{
struct si_texture *luma = (struct si_texture *)
((struct vl_video_buffer *)target)->resources[0];
struct si_texture *chroma = (struct si_texture *)
((struct vl_video_buffer *)target)->resources[1];
struct si_texture *luma = (struct si_texture *)((struct vl_video_buffer *)target)->resources[0];
struct si_texture *chroma =
(struct si_texture *)((struct vl_video_buffer *)target)->resources[1];
dec->jpg.bsd_size = align(dec->bs_size, 128);
dec->jpg.dt_luma_top_offset = luma->surface.u.gfx9.surf_offset;
@ -57,16 +54,15 @@ static struct pb_buffer *radeon_jpeg_get_decode_param(struct radeon_decoder *dec
}
/* add a new set register command to the IB */
static void set_reg_jpeg(struct radeon_decoder *dec, unsigned reg,
unsigned cond, unsigned type, uint32_t val)
static void set_reg_jpeg(struct radeon_decoder *dec, unsigned reg, unsigned cond, unsigned type,
uint32_t val)
{
radeon_emit(dec->cs, RDECODE_PKTJ(reg, cond, type));
radeon_emit(dec->cs, val);
}
/* send a bitstream buffer command */
static void send_cmd_bitstream(struct radeon_decoder *dec,
struct pb_buffer* buf, uint32_t off,
static void send_cmd_bitstream(struct radeon_decoder *dec, struct pb_buffer *buf, uint32_t off,
enum radeon_bo_usage usage, enum radeon_bo_domain domain)
{
uint64_t addr;
@ -89,13 +85,13 @@ static void send_cmd_bitstream(struct radeon_decoder *dec,
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
domain, 0);
dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
// set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH), COND0, TYPE0, (addr >> 32));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH), COND0, TYPE0,
(addr >> 32));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW), COND0, TYPE0, addr);
// set jpeg_rb_base
@ -109,25 +105,25 @@ static void send_cmd_bitstream(struct radeon_decoder *dec,
}
/* send a target buffer command */
static void send_cmd_target(struct radeon_decoder *dec,
struct pb_buffer* buf, uint32_t off,
static void send_cmd_target(struct radeon_decoder *dec, struct pb_buffer *buf, uint32_t off,
enum radeon_bo_usage usage, enum radeon_bo_domain domain)
{
uint64_t addr;
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_PITCH), COND0, TYPE0, (dec->jpg.dt_pitch >> 4));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_UV_PITCH), COND0, TYPE0, ((dec->jpg.dt_uv_pitch * 2) >> 4));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_UV_PITCH), COND0, TYPE0,
((dec->jpg.dt_uv_pitch * 2) >> 4));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_TILING_CTRL), COND0, TYPE0, 0);
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_UV_TILING_CTRL), COND0, TYPE0, 0);
dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
domain, 0);
dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
// set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH), COND0, TYPE0, (addr >> 32));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH), COND0, TYPE0,
(addr >> 32));
set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW), COND0, TYPE0, addr);
// set output buffer data address
@ -188,9 +184,9 @@ static void send_cmd_target(struct radeon_decoder *dec,
}
/* send a bitstream buffer command */
static void send_cmd_bitstream_direct(struct radeon_decoder *dec,
struct pb_buffer* buf, uint32_t off,
enum radeon_bo_usage usage, enum radeon_bo_domain domain)
static void send_cmd_bitstream_direct(struct radeon_decoder *dec, struct pb_buffer *buf,
uint32_t off, enum radeon_bo_usage usage,
enum radeon_bo_domain domain)
{
uint64_t addr;
@ -209,8 +205,7 @@ static void send_cmd_bitstream_direct(struct radeon_decoder *dec,
set_reg_jpeg(dec, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0 << 0x10));
set_reg_jpeg(dec, vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10));
dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
domain, 0);
dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
@ -229,8 +224,7 @@ static void send_cmd_bitstream_direct(struct radeon_decoder *dec,
}
/* send a target buffer command */
static void send_cmd_target_direct(struct radeon_decoder *dec,
struct pb_buffer* buf, uint32_t off,
static void send_cmd_target_direct(struct radeon_decoder *dec, struct pb_buffer *buf, uint32_t off,
enum radeon_bo_usage usage, enum radeon_bo_domain domain)
{
uint64_t addr;
@ -242,8 +236,7 @@ static void send_cmd_target_direct(struct radeon_decoder *dec,
set_reg_jpeg(dec, vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE, COND0, TYPE0, 0);
set_reg_jpeg(dec, vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE, COND0, TYPE0, 0);
dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
domain, 0);
dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
@ -260,7 +253,8 @@ static void send_cmd_target_direct(struct radeon_decoder *dec,
// set output buffer read pointer
set_reg_jpeg(dec, vcnipUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0);
set_reg_jpeg(dec, vcnipUVD_JPEG_OUTBUF_CNTL, COND0, TYPE0, ((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6)));
set_reg_jpeg(dec, vcnipUVD_JPEG_OUTBUF_CNTL, COND0, TYPE0,
((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6)));
// enable error interrupts
set_reg_jpeg(dec, vcnipUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFFFFFE);
@ -284,8 +278,7 @@ static void send_cmd_target_direct(struct radeon_decoder *dec,
/**
* send cmd for vcn jpeg
*/
void send_cmd_jpeg(struct radeon_decoder *dec,
struct pipe_video_buffer *target,
void send_cmd_jpeg(struct radeon_decoder *dec, struct pipe_video_buffer *target,
struct pipe_picture_desc *picture)
{
struct pb_buffer *dt;
@ -299,14 +292,10 @@ void send_cmd_jpeg(struct radeon_decoder *dec,
dt = radeon_jpeg_get_decode_param(dec, target, picture);
if (dec->jpg.direct_reg == true) {
send_cmd_bitstream_direct(dec, bs_buf->res->buf,
0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd_target_direct(dec, dt, 0,
RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
send_cmd_bitstream_direct(dec, bs_buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd_target_direct(dec, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
} else {
send_cmd_bitstream(dec, bs_buf->res->buf,
0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd_target(dec, dt, 0,
RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
send_cmd_bitstream(dec, bs_buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd_target(dec, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
}
}

108
src/gallium/drivers/radeon/radeon_vcn_enc.c
View File

@ -25,18 +25,16 @@
*
**************************************************************************/
#include <stdio.h>
#include "radeon_vcn_enc.h"
#include "pipe/p_video_codec.h"
#include "util/u_video.h"
#include "radeon_video.h"
#include "radeonsi/si_pipe.h"
#include "util/u_memory.h"
#include "util/u_video.h"
#include "vl/vl_video_buffer.h"
#include "radeonsi/si_pipe.h"
#include "radeon_video.h"
#include "radeon_vcn_enc.h"
#include <stdio.h>
static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
@ -69,8 +67,10 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_pic
enc->enc_pic.rc_layer_init.frame_rate_den = pic->rate_ctrl.frame_rate_den;
enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rate_ctrl.vbv_buffer_size;
enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rate_ctrl.target_bits_picture;
enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rate_ctrl.peak_bits_picture_integer;
enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rate_ctrl.peak_bits_picture_fraction;
enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer =
pic->rate_ctrl.peak_bits_picture_integer;
enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional =
pic->rate_ctrl.peak_bits_picture_fraction;
enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rate_ctrl.vbv_buf_lv;
enc->enc_pic.rc_per_pic.qp = pic->quant_i_frames;
enc->enc_pic.rc_per_pic.min_qp_app = 0;
@ -89,7 +89,8 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_pic
break;
case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE:
enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
enc->enc_pic.rc_session_init.rate_control_method =
RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
break;
default:
enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
@ -112,37 +113,47 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_pic
enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
enc->enc_pic.max_poc =
MAX2(16, util_next_power_of_two(pic->seq.intra_period));
enc->enc_pic.max_poc = MAX2(16, util_next_power_of_two(pic->seq.intra_period));
enc->enc_pic.log2_max_poc = 0;
for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
i = (i >> 1);
enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
enc->enc_pic.pic_width_in_luma_samples = pic->seq.pic_width_in_luma_samples;
enc->enc_pic.pic_height_in_luma_samples = pic->seq.pic_height_in_luma_samples;
enc->enc_pic.log2_diff_max_min_luma_coding_block_size = pic->seq.log2_diff_max_min_luma_coding_block_size;
enc->enc_pic.log2_min_transform_block_size_minus2 = pic->seq.log2_min_transform_block_size_minus2;
enc->enc_pic.log2_diff_max_min_transform_block_size = pic->seq.log2_diff_max_min_transform_block_size;
enc->enc_pic.max_transform_hierarchy_depth_inter = pic->seq.max_transform_hierarchy_depth_inter;
enc->enc_pic.max_transform_hierarchy_depth_intra = pic->seq.max_transform_hierarchy_depth_intra;
enc->enc_pic.log2_diff_max_min_luma_coding_block_size =
pic->seq.log2_diff_max_min_luma_coding_block_size;
enc->enc_pic.log2_min_transform_block_size_minus2 =
pic->seq.log2_min_transform_block_size_minus2;
enc->enc_pic.log2_diff_max_min_transform_block_size =
pic->seq.log2_diff_max_min_transform_block_size;
enc->enc_pic.max_transform_hierarchy_depth_inter =
pic->seq.max_transform_hierarchy_depth_inter;
enc->enc_pic.max_transform_hierarchy_depth_intra =
pic->seq.max_transform_hierarchy_depth_intra;
enc->enc_pic.log2_parallel_merge_level_minus2 = pic->pic.log2_parallel_merge_level_minus2;
enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
enc->enc_pic.sample_adaptive_offset_enabled_flag = pic->seq.sample_adaptive_offset_enabled_flag;
enc->enc_pic.sample_adaptive_offset_enabled_flag =
pic->seq.sample_adaptive_offset_enabled_flag;
enc->enc_pic.pcm_enabled_flag = pic->seq.pcm_enabled_flag;
enc->enc_pic.sps_temporal_mvp_enabled_flag = pic->seq.sps_temporal_mvp_enabled_flag;
enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled = pic->slice.slice_loop_filter_across_slices_enabled_flag;
enc->enc_pic.hevc_deblock.deblocking_filter_disabled = pic->slice.slice_deblocking_filter_disabled_flag;
enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled =
pic->slice.slice_loop_filter_across_slices_enabled_flag;
enc->enc_pic.hevc_deblock.deblocking_filter_disabled =
pic->slice.slice_deblocking_filter_disabled_flag;
enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 = pic->seq.log2_min_luma_coding_block_size_minus3;
enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 =
pic->seq.log2_min_luma_coding_block_size_minus3;
enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled = pic->seq.strong_intra_smoothing_enabled_flag;
enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = pic->pic.constrained_intra_pred_flag;
enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled =
pic->seq.strong_intra_smoothing_enabled_flag;
enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag =
pic->pic.constrained_intra_pred_flag;
enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
@ -153,7 +164,8 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_pic
enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rc.vbv_buffer_size;
enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rc.target_bits_picture;
enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rc.peak_bits_picture_integer;
enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rc.peak_bits_picture_fraction;
enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional =
pic->rc.peak_bits_picture_fraction;
enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc.vbv_buf_lv;
enc->enc_pic.rc_per_pic.qp = pic->rc.quant_i_frames;
enc->enc_pic.rc_per_pic.min_qp_app = 0;
@ -172,7 +184,8 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_pic
break;
case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE:
enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
enc->enc_pic.rc_session_init.rate_control_method =
RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
break;
default:
enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
@ -191,8 +204,7 @@ static void radeon_enc_flush(struct pipe_video_codec *encoder)
flush(enc);
}
static void radeon_enc_cs_flush(void *ctx, unsigned flags,
struct pipe_fence_handle **fence)
static void radeon_enc_cs_flush(void *ctx, unsigned flags, struct pipe_fence_handle **fence)
{
// just ignored
}
@ -262,8 +274,7 @@ static void radeon_enc_begin_frame(struct pipe_video_codec *encoder,
enc->enc_pic.rc_layer_init.target_bit_rate != pic->rate_ctrl.target_bitrate;
} else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
need_rate_control =
enc->enc_pic.rc_layer_init.target_bit_rate != pic->rc.target_bitrate;
need_rate_control = enc->enc_pic.rc_layer_init.target_bit_rate != pic->rc.target_bitrate;
}
radeon_vcn_enc_get_param(enc, picture);
@ -292,8 +303,7 @@ static void radeon_enc_begin_frame(struct pipe_video_codec *encoder,
static void radeon_enc_encode_bitstream(struct pipe_video_codec *encoder,
struct pipe_video_buffer *source,
struct pipe_resource *destination,
void **fb)
struct pipe_resource *destination, void **fb)
{
struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
enc->get_buffer(destination, &enc->bs_handle, NULL);
@ -310,8 +320,7 @@ static void radeon_enc_encode_bitstream(struct pipe_video_codec *encoder,
enc->encode(enc);
}
static void radeon_enc_end_frame(struct pipe_video_codec *encoder,
struct pipe_video_buffer *source,
static void radeon_enc_end_frame(struct pipe_video_codec *encoder, struct pipe_video_buffer *source,
struct pipe_picture_desc *picture)
{
struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
@ -337,15 +346,14 @@ static void radeon_enc_destroy(struct pipe_video_codec *encoder)
FREE(enc);
}
static void radeon_enc_get_feedback(struct pipe_video_codec *encoder,
void *feedback, unsigned *size)
static void radeon_enc_get_feedback(struct pipe_video_codec *encoder, void *feedback,
unsigned *size)
{
struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
struct rvid_buffer *fb = feedback;
if (size) {
uint32_t *ptr = enc->ws->buffer_map(
fb->res->buf, enc->cs,
uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs,
PIPE_TRANSFER_READ_WRITE | RADEON_TRANSFER_TEMPORARY);
if (ptr[1])
*size = ptr[6];
@ -388,8 +396,7 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
enc->bits_in_shifter = 0;
enc->screen = context->screen;
enc->ws = ws;
enc->cs = ws->cs_create(sctx->ctx, RING_VCN_ENC, radeon_enc_cs_flush,
enc, false);
enc->cs = ws->cs_create(sctx->ctx, RING_VCN_ENC, radeon_enc_cs_flush, enc, false);
if (!enc->cs) {
RVID_ERR("Can't get command submission context.\n");
@ -419,10 +426,10 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
cpb_size = (sscreen->info.chip_class < GFX9) ?
align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
align(tmp_surf->u.legacy.level[0].nblk_y, 32) :
align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
cpb_size = (sscreen->info.chip_class < GFX9)
? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
align(tmp_surf->u.legacy.level[0].nblk_y, 32)
: align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
align(tmp_surf->u.gfx9.surf_height, 32);
cpb_size = cpb_size * 3 / 2;
@ -452,11 +459,9 @@ error:
}
void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,
enum radeon_bo_usage usage, enum radeon_bo_domain domain,
signed offset)
enum radeon_bo_usage usage, enum radeon_bo_domain domain, signed offset)
{
enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
domain, 0);
enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
uint64_t addr;
addr = enc->ws->buffer_get_virtual_address(buf);
addr = addr + offset;
@ -476,7 +481,8 @@ void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte)
{
if (enc->byte_index == 0)
enc->cs->current.buf[enc->cs->current.cdw] = 0;
enc->cs->current.buf[enc->cs->current.cdw] |= ((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
enc->cs->current.buf[enc->cs->current.cdw] |=
((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
enc->byte_index++;
if (enc->byte_index >= 4) {
@ -497,13 +503,15 @@ void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char b
}
}
void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value, unsigned int num_bits)
void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value,
unsigned int num_bits)
{
unsigned int bits_to_pack = 0;
while (num_bits > 0) {
unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
bits_to_pack = num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
bits_to_pack =
num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
if (bits_to_pack < num_bits)
value_to_pack = value_to_pack >> (num_bits - bits_to_pack);

117
src/gallium/drivers/radeon/radeon_vcn_enc.h
View File

@ -124,31 +124,34 @@
#define RENCODE_FEEDBACK_BUFFER_MODE_CIRCULAR 1
#define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
#define RADEON_ENC_BEGIN(cmd) { \
#define RADEON_ENC_BEGIN(cmd) \
{ \
uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
RADEON_ENC_CS(cmd)
#define RADEON_ENC_READ(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
#define RADEON_ENC_WRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
#define RADEON_ENC_READWRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
#define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
enc->total_task_size += *begin;}
#define RADEON_ENC_READ(buf, domain, off) \
radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
#define RADEON_ENC_WRITE(buf, domain, off) \
radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
#define RADEON_ENC_READWRITE(buf, domain, off) \
radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
#define RADEON_ENC_END() \
*begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
enc->total_task_size += *begin; \
}
typedef struct rvcn_enc_session_info_s
{
typedef struct rvcn_enc_session_info_s {
uint32_t interface_version;
uint32_t sw_context_address_hi;
uint32_t sw_context_address_lo;
} rvcn_enc_session_info_t;
typedef struct rvcn_enc_task_info_s
{
typedef struct rvcn_enc_task_info_s {
uint32_t total_size_of_all_packages;
uint32_t task_id;
uint32_t allowed_max_num_feedbacks;
} rvcn_enc_task_info_t;
typedef struct rvcn_enc_session_init_s
{
typedef struct rvcn_enc_session_init_s {
uint32_t encode_standard;
uint32_t aligned_picture_width;
uint32_t aligned_picture_height;
@ -158,48 +161,39 @@ typedef struct rvcn_enc_session_init_s
uint32_t pre_encode_chroma_enabled;
} rvcn_enc_session_init_t;
typedef struct rvcn_enc_layer_control_s
{
typedef struct rvcn_enc_layer_control_s {
uint32_t max_num_temporal_layers;
uint32_t num_temporal_layers;
} rvcn_enc_layer_control_t;
typedef struct rvcn_enc_layer_select_s
{
typedef struct rvcn_enc_layer_select_s {
uint32_t temporal_layer_index;
} rvcn_enc_layer_select_t;
typedef struct rvcn_enc_h264_slice_control_s
{
typedef struct rvcn_enc_h264_slice_control_s {
uint32_t slice_control_mode;
union
{
union {
uint32_t num_mbs_per_slice;
uint32_t num_bits_per_slice;
};
} rvcn_enc_h264_slice_control_t;
typedef struct rvcn_enc_hevc_slice_control_s
{
typedef struct rvcn_enc_hevc_slice_control_s {
uint32_t slice_control_mode;
union
{
struct
{
union {
struct {
uint32_t num_ctbs_per_slice;
uint32_t num_ctbs_per_slice_segment;
} fixed_ctbs_per_slice;
struct
{
struct {
uint32_t num_bits_per_slice;
uint32_t num_bits_per_slice_segment;
} fixed_bits_per_slice;
};
} rvcn_enc_hevc_slice_control_t;
typedef struct rvcn_enc_h264_spec_misc_s
{
typedef struct rvcn_enc_h264_spec_misc_s {
uint32_t constrained_intra_pred_flag;
uint32_t cabac_enable;
uint32_t cabac_init_idc;
@ -209,8 +203,7 @@ typedef struct rvcn_enc_h264_spec_misc_s
uint32_t level_idc;
} rvcn_enc_h264_spec_misc_t;
typedef struct rvcn_enc_hevc_spec_misc_s
{
typedef struct rvcn_enc_hevc_spec_misc_s {
uint32_t log2_min_luma_coding_block_size_minus3;
uint32_t amp_disabled;
uint32_t strong_intra_smoothing_enabled;
@ -220,14 +213,12 @@ typedef struct rvcn_enc_hevc_spec_misc_s
uint32_t quarter_pel_enabled;
} rvcn_enc_hevc_spec_misc_t;
typedef struct rvcn_enc_rate_ctl_session_init_s
{
typedef struct rvcn_enc_rate_ctl_session_init_s {
uint32_t rate_control_method;
uint32_t vbv_buffer_level;
} rvcn_enc_rate_ctl_session_init_t;
typedef struct rvcn_enc_rate_ctl_layer_init_s
{
typedef struct rvcn_enc_rate_ctl_layer_init_s {
uint32_t target_bit_rate;
uint32_t peak_bit_rate;
uint32_t frame_rate_num;
@ -238,8 +229,7 @@ typedef struct rvcn_enc_rate_ctl_layer_init_s
uint32_t peak_bits_per_picture_fractional;
} rvcn_enc_rate_ctl_layer_init_t;
typedef struct rvcn_enc_rate_ctl_per_picture_s
{
typedef struct rvcn_enc_rate_ctl_per_picture_s {
uint32_t qp;
uint32_t min_qp_app;
uint32_t max_qp_app;
@ -249,23 +239,20 @@ typedef struct rvcn_enc_rate_ctl_per_picture_s
uint32_t enforce_hrd;
} rvcn_enc_rate_ctl_per_picture_t;
typedef struct rvcn_enc_quality_params_s
{
typedef struct rvcn_enc_quality_params_s {
uint32_t vbaq_mode;
uint32_t scene_change_sensitivity;
uint32_t scene_change_min_idr_interval;
uint32_t two_pass_search_center_map_mode;
} rvcn_enc_quality_params_t;
typedef struct rvcn_enc_direct_output_nalu_s
{
typedef struct rvcn_enc_direct_output_nalu_s {
uint32_t type;
uint32_t size;
uint32_t data[1];
} rvcn_enc_direct_output_nalu_t;
typedef struct rvcn_enc_slice_header_s
{
typedef struct rvcn_enc_slice_header_s {
uint32_t bitstream_template[RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS];
struct {
uint32_t instruction;
@ -273,8 +260,7 @@ typedef struct rvcn_enc_slice_header_s
} instructions[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS];
} rvcn_enc_slice_header_t;
typedef struct rvcn_enc_encode_params_s
{
typedef struct rvcn_enc_encode_params_s {
uint32_t pic_type;
uint32_t allowed_max_bitstream_size;
uint32_t input_picture_luma_address_hi;
@ -288,16 +274,14 @@ typedef struct rvcn_enc_encode_params_s
uint32_t reconstructed_picture_index;
} rvcn_enc_encode_params_t;
typedef struct rvcn_enc_h264_encode_params_s
{
typedef struct rvcn_enc_h264_encode_params_s {
uint32_t input_picture_structure;
uint32_t interlaced_mode;
uint32_t reference_picture_structure;
uint32_t reference_picture1_index;
} rvcn_enc_h264_encode_params_t;
typedef struct rvcn_enc_h264_deblocking_filter_s
{
typedef struct rvcn_enc_h264_deblocking_filter_s {
uint32_t disable_deblocking_filter_idc;
int32_t alpha_c0_offset_div2;
int32_t beta_offset_div2;
@ -305,8 +289,7 @@ typedef struct rvcn_enc_h264_deblocking_filter_s
int32_t cr_qp_offset;
} rvcn_enc_h264_deblocking_filter_t;
typedef struct rvcn_enc_hevc_deblocking_filter_s
{
typedef struct rvcn_enc_hevc_deblocking_filter_s {
uint32_t loop_filter_across_slices_enabled;
int32_t deblocking_filter_disabled;
int32_t beta_offset_div2;
@ -315,21 +298,18 @@ typedef struct rvcn_enc_hevc_deblocking_filter_s
int32_t cr_qp_offset;
} rvcn_enc_hevc_deblocking_filter_t;
typedef struct rvcn_enc_intra_refresh_s
{
typedef struct rvcn_enc_intra_refresh_s {
uint32_t intra_refresh_mode;
uint32_t offset;
uint32_t region_size;
} rvcn_enc_intra_refresh_t;
typedef struct rvcn_enc_reconstructed_picture_s
{
typedef struct rvcn_enc_reconstructed_picture_s {
uint32_t luma_offset;
uint32_t chroma_offset;
} rvcn_enc_reconstructed_picture_t;
typedef struct rvcn_enc_encode_context_buffer_s
{
typedef struct rvcn_enc_encode_context_buffer_s {
uint32_t encode_context_address_hi;
uint32_t encode_context_address_lo;
uint32_t swizzle_mode;
@ -339,12 +319,12 @@ typedef struct rvcn_enc_encode_context_buffer_s
rvcn_enc_reconstructed_picture_t reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES];
uint32_t pre_encode_picture_luma_pitch;
uint32_t pre_encode_picture_chroma_pitch;
rvcn_enc_reconstructed_picture_t pre_encode_reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES];
rvcn_enc_reconstructed_picture_t
pre_encode_reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES];
rvcn_enc_reconstructed_picture_t pre_encode_input_picture;
} rvcn_enc_encode_context_buffer_t;
typedef struct rvcn_enc_video_bitstream_buffer_s
{
typedef struct rvcn_enc_video_bitstream_buffer_s {
uint32_t mode;
uint32_t video_bitstream_buffer_address_hi;
uint32_t video_bitstream_buffer_address_lo;
@ -352,8 +332,7 @@ typedef struct rvcn_enc_video_bitstream_buffer_s
uint32_t video_bitstream_data_offset;
} rvcn_enc_video_bitstream_buffer_t;
typedef struct rvcn_enc_feedback_buffer_s
{
typedef struct rvcn_enc_feedback_buffer_s {
uint32_t mode;
uint32_t feedback_buffer_address_hi;
uint32_t feedback_buffer_address_lo;
@ -361,8 +340,7 @@ typedef struct rvcn_enc_feedback_buffer_s
uint32_t feedback_data_size;
} rvcn_enc_feedback_buffer_t;
typedef struct rvcn_enc_cmd_s
{
typedef struct rvcn_enc_cmd_s {
uint32_t session_info;
uint32_t task_info;
uint32_t session_init;
@ -391,8 +369,7 @@ typedef struct rvcn_enc_cmd_s
uint32_t output_format;
} rvcn_enc_cmd_t;
typedef void (*radeon_enc_get_buffer)(struct pipe_resource *resource,
struct pb_buffer **handle,
typedef void (*radeon_enc_get_buffer)(struct pipe_resource *resource, struct pb_buffer **handle,
struct radeon_surf **surface);
struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
@ -537,15 +514,13 @@ struct radeon_encoder {
};
void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,
enum radeon_bo_usage usage, enum radeon_bo_domain domain,
signed offset);
enum radeon_bo_usage usage, enum radeon_bo_domain domain, signed offset);
void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set);
void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte);
void radeon_enc_emulation_prevention(struct radeon_encoder *enc,
unsigned char byte);
void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte);
void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value,
unsigned int num_bits);

65
src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
View File

@ -25,15 +25,13 @@
*
**************************************************************************/
#include <stdio.h>
#include "pipe/p_video_codec.h"
#include "radeon_vcn_enc.h"
#include "radeon_video.h"
#include "si_pipe.h"
#include "util/u_video.h"
#include "si_pipe.h"
#include "radeon_video.h"
#include "radeon_vcn_enc.h"
#include <stdio.h>
#define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
#define RENCODE_FW_INTERFACE_MINOR_VERSION 2
@ -94,8 +92,10 @@ static void radeon_enc_session_init(struct radeon_encoder *enc)
enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
enc->enc_pic.session_init.padding_width =
enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
enc->enc_pic.session_init.padding_height =
enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
@ -115,8 +115,10 @@ static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
enc->enc_pic.session_init.padding_width =
enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
enc->enc_pic.session_init.padding_height =
enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
@ -154,7 +156,8 @@ static void radeon_enc_layer_select(struct radeon_encoder *enc)
static void radeon_enc_slice_control(struct radeon_encoder *enc)
{
enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
enc->enc_pic.slice_ctrl.num_mbs_per_slice = align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16;
enc->enc_pic.slice_ctrl.num_mbs_per_slice =
align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16;
RADEON_ENC_BEGIN(enc->cmd.slice_control_h264);
RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
@ -165,8 +168,10 @@ static void radeon_enc_slice_control(struct radeon_encoder *enc)
static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
{
enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice = align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment = enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice =
align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
RADEON_ENC_BEGIN(enc->cmd.slice_control_hevc);
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
@ -289,10 +294,11 @@ static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8);
radeon_enc_code_ue(enc, 0x0);
if(enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 || enc->enc_pic.spec_misc.profile_idc == 122 ||
enc->enc_pic.spec_misc.profile_idc == 244 || enc->enc_pic.spec_misc.profile_idc == 44 || enc->enc_pic.spec_misc.profile_idc == 83 ||
enc->enc_pic.spec_misc.profile_idc == 86 || enc->enc_pic.spec_misc.profile_idc == 118 || enc->enc_pic.spec_misc.profile_idc == 128 ||
enc->enc_pic.spec_misc.profile_idc == 138) {
if (enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 ||
enc->enc_pic.spec_misc.profile_idc == 122 || enc->enc_pic.spec_misc.profile_idc == 244 ||
enc->enc_pic.spec_misc.profile_idc == 44 || enc->enc_pic.spec_misc.profile_idc == 83 ||
enc->enc_pic.spec_misc.profile_idc == 86 || enc->enc_pic.spec_misc.profile_idc == 118 ||
enc->enc_pic.spec_misc.profile_idc == 128 || enc->enc_pic.spec_misc.profile_idc == 138) {
radeon_enc_code_ue(enc, 0x1);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 0x0);
@ -306,7 +312,8 @@ static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
radeon_enc_code_ue(enc, 1);
radeon_enc_code_ue(enc, (enc->base.max_references + 1));
radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0,
1);
radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1));
radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1));
bool progressive_only = true;
@ -399,7 +406,8 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
// Only support CTBSize 64
radeon_enc_code_ue(enc, 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
radeon_enc_code_ue(enc,
6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
@ -490,8 +498,7 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
radeon_enc_code_se(enc, 0x0);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
if (enc->enc_pic.rc_session_init.rate_control_method ==
RENCODE_RATE_CONTROL_METHOD_NONE)
if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
radeon_enc_code_fixed_bits(enc, 0x0, 1);
else {
radeon_enc_code_fixed_bits(enc, 0x1, 1);
@ -665,9 +672,15 @@ static void radeon_enc_slice_header(struct radeon_encoder *enc)
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
if (enc->enc_pic.h264_enc_params.input_picture_structure != RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
if (enc->enc_pic.h264_enc_params.input_picture_structure !=
RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.h264_enc_params.input_picture_structure == RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD ? 1 : 0, 1);
radeon_enc_code_fixed_bits(enc,
enc->enc_pic.h264_enc_params.input_picture_structure ==
RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
? 1
: 0,
1);
}
if (enc->enc_pic.is_idr)
@ -696,7 +709,8 @@ static void radeon_enc_slice_header(struct radeon_encoder *enc)
} else
radeon_enc_code_fixed_bits(enc, 0x0, 1);
if ((enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) && (enc->enc_pic.spec_misc.cabac_enable))
if ((enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) &&
(enc->enc_pic.spec_misc.cabac_enable))
radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
radeon_enc_flush_headers(enc);
@ -827,7 +841,8 @@ static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
(!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) {
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled,
1);
radeon_enc_flush_headers(enc);
bit_index++;

19
src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
View File

@ -25,15 +25,13 @@
*
**************************************************************************/
#include <stdio.h>
#include "pipe/p_video_codec.h"
#include "radeon_vcn_enc.h"
#include "radeon_video.h"
#include "si_pipe.h"
#include "util/u_video.h"
#include "si_pipe.h"
#include "radeon_video.h"
#include "radeon_vcn_enc.h"
#include <stdio.h>
#define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
#define RENCODE_FW_INTERFACE_MINOR_VERSION 1
@ -75,7 +73,6 @@
#define RENCODE_COLOR_PACKING_FORMAT_NV12 0
#define RENCODE_COLOR_PACKING_FORMAT_P010 1
static void radeon_enc_quality_params(struct radeon_encoder *enc)
{
enc->enc_pic.quality_params.vbaq_mode = 0;
@ -150,7 +147,8 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
// Only support CTBSize 64
radeon_enc_code_ue(enc, 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
radeon_enc_code_ue(enc,
6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
@ -206,8 +204,7 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
radeon_enc_code_se(enc, 0x0);
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
if (enc->enc_pic.rc_session_init.rate_control_method ==
RENCODE_RATE_CONTROL_METHOD_NONE)
if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
radeon_enc_code_fixed_bits(enc, 0x0, 1);
else {
radeon_enc_code_fixed_bits(enc, 0x1, 1);
@ -243,7 +240,6 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
RADEON_ENC_END();
}
static void radeon_enc_input_format(struct radeon_encoder *enc)
{
RADEON_ENC_BEGIN(enc->cmd.input_format);
@ -326,7 +322,6 @@ static void radeon_enc_ctx(struct radeon_encoder *enc)
RADEON_ENC_END();
}
static void encode(struct radeon_encoder *enc)
{
enc->session_info(enc);

22
src/gallium/drivers/radeon/radeon_video.c
View File

@ -25,17 +25,16 @@
*
**************************************************************************/
#include <unistd.h>
#include "radeon_video.h"
#include "radeon_vce.h"
#include "radeonsi/si_pipe.h"
#include "util/u_memory.h"
#include "util/u_video.h"
#include "vl/vl_defines.h"
#include "vl/vl_video_buffer.h"
#include "radeonsi/si_pipe.h"
#include "radeon_video.h"
#include "radeon_vce.h"
#include <unistd.h>
/* generate an stream handle */
unsigned si_vid_alloc_stream_handle()
@ -53,8 +52,8 @@ unsigned si_vid_alloc_stream_handle()
}
/* create a buffer in the winsys */
bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer,
unsigned size, unsigned usage)
bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer, unsigned size,
unsigned usage)
{
memset(buffer, 0, sizeof(*buffer));
buffer->usage = usage;
@ -63,8 +62,7 @@ bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer
* able to move buffers around individually, so request a
* non-sub-allocated buffer.
*/
buffer->res = si_resource(pipe_buffer_create(screen, PIPE_BIND_SHARED,
usage, size));
buffer->res = si_resource(pipe_buffer_create(screen, PIPE_BIND_SHARED, usage, size));
return buffer->res != NULL;
}
@ -88,13 +86,11 @@ bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_cmdbuf *cs,
if (!si_vid_create_buffer(screen, new_buf, new_size, new_buf->usage))
goto error;
src = ws->buffer_map(old_buf.res->buf, cs,
PIPE_TRANSFER_READ | RADEON_TRANSFER_TEMPORARY);
src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ | RADEON_TRANSFER_TEMPORARY);
if (!src)
goto error;
dst = ws->buffer_map(new_buf->res->buf, cs,
PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
dst = ws->buffer_map(new_buf->res->buf, cs, PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
if (!dst)
goto error;

7
src/gallium/drivers/radeon/radeon_video.h
View File

@ -37,8 +37,7 @@
#define UVD_FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
/* video buffer representation */
struct rvid_buffer
{
struct rvid_buffer {
unsigned usage;
struct si_resource *res;
};
@ -47,8 +46,8 @@ struct rvid_buffer
unsigned si_vid_alloc_stream_handle(void);
/* create a buffer in the winsys */
bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer,
unsigned size, unsigned usage);
bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer, unsigned size,
unsigned usage);
/* destroy a buffer */
void si_vid_destroy_buffer(struct rvid_buffer *buffer);

175
src/gallium/drivers/radeon/radeon_winsys.h
View File

@ -35,13 +35,13 @@
#define RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW \
(PIPE_FLUSH_ASYNC | RADEON_FLUSH_START_NEXT_GFX_IB_NOW)
#include "pipebuffer/pb_buffer.h"
#include "amd/common/ac_gpu_info.h"
#include "amd/common/ac_surface.h"
#include "pipebuffer/pb_buffer.h"
/* Tiling flags. */
enum radeon_bo_layout {
enum radeon_bo_layout
{
RADEON_LAYOUT_LINEAR = 0,
RADEON_LAYOUT_TILED,
RADEON_LAYOUT_SQUARETILED,
@ -49,7 +49,8 @@ enum radeon_bo_layout {
RADEON_LAYOUT_UNKNOWN
};
enum radeon_bo_domain { /* bitfield */
enum radeon_bo_domain
{ /* bitfield */
RADEON_DOMAIN_GTT = 2,
RADEON_DOMAIN_VRAM = 4,
RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
@ -57,7 +58,8 @@ enum radeon_bo_domain { /* bitfield */
RADEON_DOMAIN_OA = 16,
};
enum radeon_bo_flag { /* bitfield */
enum radeon_bo_flag
{ /* bitfield */
RADEON_FLAG_GTT_WC = (1 << 0),
RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
RADEON_FLAG_NO_SUBALLOC = (1 << 2),
@ -67,7 +69,8 @@ enum radeon_bo_flag { /* bitfield */
RADEON_FLAG_32BIT = (1 << 6),
};
enum radeon_dependency_flag {
enum radeon_dependency_flag
{
/* Add the dependency to the parallel compute IB only. */
RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY = 1 << 0,
@ -77,7 +80,8 @@ enum radeon_dependency_flag {
RADEON_DEPENDENCY_START_FENCE = 1 << 1,
};
enum radeon_bo_usage { /* bitfield */
enum radeon_bo_usage
{ /* bitfield */
RADEON_USAGE_READ = 2,
RADEON_USAGE_WRITE = 4,
RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
@ -88,7 +92,8 @@ enum radeon_bo_usage { /* bitfield */
RADEON_USAGE_SYNCHRONIZED = 8
};
enum radeon_transfer_flags {
enum radeon_transfer_flags
{
/* Indicates that the caller will unmap the buffer.
*
* Not unmapping buffers is an important performance optimization for
@ -99,7 +104,8 @@ enum radeon_transfer_flags {
#define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
enum radeon_value_id {
enum radeon_value_id
{
RADEON_REQUESTED_VRAM_MEMORY,
RADEON_REQUESTED_GTT_MEMORY,
RADEON_MAPPED_VRAM,
@ -123,7 +129,8 @@ enum radeon_value_id {
RADEON_CS_THREAD_TIME,
};
enum radeon_bo_priority {
enum radeon_bo_priority
{
/* Each group of two has the same priority. */
RADEON_PRIO_FENCE = 0,
RADEON_PRIO_TRACE,
@ -233,7 +240,8 @@ struct radeon_bo_metadata {
uint32_t metadata[64];
};
enum radeon_feature_id {
enum radeon_feature_id
{
RADEON_FID_R300_HYPERZ_ACCESS, /* ZMask + HiZ */
RADEON_FID_R300_CMASK_ACCESS,
};
@ -271,8 +279,7 @@ struct radeon_winsys {
* \param ws The winsys this function is called from.
* \param info Return structure
*/
void (*query_info)(struct radeon_winsys *ws,
struct radeon_info *info);
void (*query_info)(struct radeon_winsys *ws, struct radeon_info *info);
/**
* A hint for the winsys that it should pin its execution threads to
@ -300,11 +307,8 @@ struct radeon_winsys {
* \param domain A bitmask of the RADEON_DOMAIN_* flags.
* \return The created buffer object.
*/
struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
uint64_t size,
unsigned alignment,
enum radeon_bo_domain domain,
enum radeon_bo_flag flags);
struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws, uint64_t size, unsigned alignment,
enum radeon_bo_domain domain, enum radeon_bo_flag flags);
/**
* Map the entire data store of a buffer object into the client's address
@ -318,8 +322,7 @@ struct radeon_winsys {
* \param usage A bitmask of the PIPE_TRANSFER_* and RADEON_TRANSFER_* flags.
* \return The pointer at the beginning of the buffer.
*/
void *(*buffer_map)(struct pb_buffer *buf,
struct radeon_cmdbuf *cs,
void *(*buffer_map)(struct pb_buffer *buf, struct radeon_cmdbuf *cs,
enum pipe_transfer_usage usage);
/**
@ -337,8 +340,7 @@ struct radeon_winsys {
* The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
* is idle.
*/
bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
enum radeon_bo_usage usage);
bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout, enum radeon_bo_usage usage);
/**
* Return buffer metadata.
@ -347,8 +349,7 @@ struct radeon_winsys {
* \param buf A winsys buffer object to get the flags from.
* \param md Metadata
*/
void (*buffer_get_metadata)(struct pb_buffer *buf,
struct radeon_bo_metadata *md);
void (*buffer_get_metadata)(struct pb_buffer *buf, struct radeon_bo_metadata *md);
/**
* Set buffer metadata.
@ -357,8 +358,7 @@ struct radeon_winsys {
* \param buf A winsys buffer object to set the flags for.
* \param md Metadata
*/
void (*buffer_set_metadata)(struct pb_buffer *buf,
struct radeon_bo_metadata *md);
void (*buffer_set_metadata)(struct pb_buffer *buf, struct radeon_bo_metadata *md);
/**
* Get a winsys buffer from a winsys handle. The internal structure
@ -368,8 +368,7 @@ struct radeon_winsys {
* \param whandle A winsys handle pointer as was received from a state
* tracker.
*/
struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
struct winsys_handle *whandle,
struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws, struct winsys_handle *whandle,
unsigned vm_alignment);
/**
@ -380,8 +379,7 @@ struct radeon_winsys {
* \param pointer User pointer to turn into a buffer object.
* \param Size Size in bytes for the new buffer.
*/
struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
void *pointer, uint64_t size);
struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws, void *pointer, uint64_t size);
/**
* Whether the buffer was created from a user pointer.
@ -403,8 +401,7 @@ struct radeon_winsys {
* \param whandle A winsys handle pointer.
* \return true on success.
*/
bool (*buffer_get_handle)(struct radeon_winsys *ws,
struct pb_buffer *buf,
bool (*buffer_get_handle)(struct radeon_winsys *ws, struct pb_buffer *buf,
struct winsys_handle *whandle);
/**
@ -417,9 +414,7 @@ struct radeon_winsys {
*
* \return false on out of memory or other failure, true on success.
*/
bool (*buffer_commit)(struct pb_buffer *buf,
uint64_t offset, uint64_t size,
bool commit);
bool (*buffer_commit)(struct pb_buffer *buf, uint64_t offset, uint64_t size, bool commit);
/**
* Return the virtual address of a buffer.
@ -480,12 +475,10 @@ struct radeon_winsys {
* \param flush Flush callback function associated with the command stream.
* \param user User pointer that will be passed to the flush callback.
*/
struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys_ctx *ctx,
enum ring_type ring_type,
struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys_ctx *ctx, enum ring_type ring_type,
void (*flush)(void *ctx, unsigned flags,
struct pipe_fence_handle **fence),
void *flush_ctx,
bool stop_exec_on_failure);
void *flush_ctx, bool stop_exec_on_failure);
/**
* Add a parallel compute IB to a gfx IB. It will share the buffer list
@ -522,10 +515,8 @@ struct radeon_winsys {
* placed in the requested domain. 15 is the maximum.
* \return Buffer index.
*/
unsigned (*cs_add_buffer)(struct radeon_cmdbuf *cs,
struct pb_buffer *buf,
enum radeon_bo_usage usage,
enum radeon_bo_domain domain,
unsigned (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct pb_buffer *buf,
enum radeon_bo_usage usage, enum radeon_bo_domain domain,
enum radeon_bo_priority priority);
/**
@ -538,8 +529,7 @@ struct radeon_winsys {
* \param buf Buffer
* \return The buffer index, or -1 if the buffer has not been added.
*/
int (*cs_lookup_buffer)(struct radeon_cmdbuf *cs,
struct pb_buffer *buf);
int (*cs_lookup_buffer)(struct radeon_cmdbuf *cs, struct pb_buffer *buf);
/**
* Return true if there is enough memory in VRAM and GTT for the buffers
@ -561,8 +551,7 @@ struct radeon_winsys {
* the CP prefetch cache (to emulate PKT3_REWIND)
* \return true if there is enough space
*/
bool (*cs_check_space)(struct radeon_cmdbuf *cs, unsigned dw,
bool force_chaining);
bool (*cs_check_space)(struct radeon_cmdbuf *cs, unsigned dw, bool force_chaining);
/**
* Return the buffer list.
@ -574,8 +563,7 @@ struct radeon_winsys {
* \param list Returned buffer list. Set to NULL to query the count only.
* \return The buffer count.
*/
unsigned (*cs_get_buffer_list)(struct radeon_cmdbuf *cs,
struct radeon_bo_list_item *list);
unsigned (*cs_get_buffer_list)(struct radeon_cmdbuf *cs, struct radeon_bo_list_item *list);
/**
* Flush a command stream.
@ -587,9 +575,7 @@ struct radeon_winsys {
* \return Negative POSIX error code or 0 for success.
* Asynchronous submissions never return an error.
*/
int (*cs_flush)(struct radeon_cmdbuf *cs,
unsigned flags,
struct pipe_fence_handle **fence);
int (*cs_flush)(struct radeon_cmdbuf *cs, unsigned flags, struct pipe_fence_handle **fence);
/**
* Create a fence before the CS is flushed.
@ -606,8 +592,7 @@ struct radeon_winsys {
* \param cs A command stream.
* \param buf A winsys buffer.
*/
bool (*cs_is_buffer_referenced)(struct radeon_cmdbuf *cs,
struct pb_buffer *buf,
bool (*cs_is_buffer_referenced)(struct radeon_cmdbuf *cs, struct pb_buffer *buf,
enum radeon_bo_usage usage);
/**
@ -617,9 +602,7 @@ struct radeon_winsys {
* \param fid Feature ID, one of RADEON_FID_*
* \param enable Whether to enable or disable the feature.
*/
bool (*cs_request_feature)(struct radeon_cmdbuf *cs,
enum radeon_feature_id fid,
bool enable);
bool (*cs_request_feature)(struct radeon_cmdbuf *cs, enum radeon_feature_id fid, bool enable);
/**
* Make sure all asynchronous flush of the cs have completed
*
@ -633,15 +616,13 @@ struct radeon_winsys {
*
* \param dependency_flags Bitmask of RADEON_DEPENDENCY_*
*/
void (*cs_add_fence_dependency)(struct radeon_cmdbuf *cs,
struct pipe_fence_handle *fence,
void (*cs_add_fence_dependency)(struct radeon_cmdbuf *cs, struct pipe_fence_handle *fence,
unsigned dependency_flags);
/**
* Signal a syncobj when the CS finishes execution.
*/
void (*cs_add_syncobj_signal)(struct radeon_cmdbuf *cs,
struct pipe_fence_handle *fence);
void (*cs_add_syncobj_signal)(struct radeon_cmdbuf *cs, struct pipe_fence_handle *fence);
/**
* Wait for the fence and return true if the fence has been signalled.
@ -649,33 +630,27 @@ struct radeon_winsys {
* The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
* is signalled.
*/
bool (*fence_wait)(struct radeon_winsys *ws,
struct pipe_fence_handle *fence,
uint64_t timeout);
bool (*fence_wait)(struct radeon_winsys *ws, struct pipe_fence_handle *fence, uint64_t timeout);
/**
* Reference counting for fences.
*/
void (*fence_reference)(struct pipe_fence_handle **dst,
struct pipe_fence_handle *src);
void (*fence_reference)(struct pipe_fence_handle **dst, struct pipe_fence_handle *src);
/**
* Create a new fence object corresponding to the given syncobj fd.
*/
struct pipe_fence_handle *(*fence_import_syncobj)(struct radeon_winsys *ws,
int fd);
struct pipe_fence_handle *(*fence_import_syncobj)(struct radeon_winsys *ws, int fd);
/**
* Create a new fence object corresponding to the given sync_file.
*/
struct pipe_fence_handle *(*fence_import_sync_file)(struct radeon_winsys *ws,
int fd);
struct pipe_fence_handle *(*fence_import_sync_file)(struct radeon_winsys *ws, int fd);
/**
* Return a sync_file FD corresponding to the given fence object.
*/
int (*fence_export_sync_file)(struct radeon_winsys *ws,
struct pipe_fence_handle *fence);
int (*fence_export_sync_file)(struct radeon_winsys *ws, struct pipe_fence_handle *fence);
/**
* Return a sync file FD that is already signalled.
@ -692,17 +667,13 @@ struct radeon_winsys {
* \param mode Preferred tile mode. (linear, 1D, or 2D)
* \param surf Output structure
*/
int (*surface_init)(struct radeon_winsys *ws,
const struct pipe_resource *tex,
unsigned flags, unsigned bpe,
enum radeon_surf_mode mode,
struct radeon_surf *surf);
int (*surface_init)(struct radeon_winsys *ws, const struct pipe_resource *tex, unsigned flags,
unsigned bpe, enum radeon_surf_mode mode, struct radeon_surf *surf);
uint64_t (*query_value)(struct radeon_winsys *ws,
enum radeon_value_id value);
uint64_t (*query_value)(struct radeon_winsys *ws, enum radeon_value_id value);
bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
unsigned num_registers, uint32_t *out);
bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers,
uint32_t *out);
};
static inline bool radeon_emitted(struct radeon_cmdbuf *cs, unsigned num_dw)
@ -715,14 +686,15 @@ static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
cs->current.buf[cs->current.cdw++] = value;
}
static inline void radeon_emit_array(struct radeon_cmdbuf *cs,
const uint32_t *values, unsigned count)
static inline void radeon_emit_array(struct radeon_cmdbuf *cs, const uint32_t *values,
unsigned count)
{
memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
cs->current.cdw += count;
}
enum radeon_heap {
enum radeon_heap
{
RADEON_HEAP_VRAM_NO_CPU_ACCESS,
RADEON_HEAP_VRAM_READ_ONLY,
RADEON_HEAP_VRAM_READ_ONLY_32BIT,
@ -760,29 +732,24 @@ static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap hea
static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
{
unsigned flags = RADEON_FLAG_NO_INTERPROCESS_SHARING |
(heap != RADEON_HEAP_GTT ? RADEON_FLAG_GTT_WC : 0);
unsigned flags =
RADEON_FLAG_NO_INTERPROCESS_SHARING | (heap != RADEON_HEAP_GTT ? RADEON_FLAG_GTT_WC : 0);
switch (heap) {
case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
return flags |
RADEON_FLAG_NO_CPU_ACCESS;
return flags | RADEON_FLAG_NO_CPU_ACCESS;
case RADEON_HEAP_VRAM_READ_ONLY:
case RADEON_HEAP_GTT_WC_READ_ONLY:
return flags |
RADEON_FLAG_READ_ONLY;
return flags | RADEON_FLAG_READ_ONLY;
case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
return flags |
RADEON_FLAG_READ_ONLY |
RADEON_FLAG_32BIT;
return flags | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT;
case RADEON_HEAP_VRAM_32BIT:
case RADEON_HEAP_GTT_WC_32BIT:
return flags |
RADEON_FLAG_32BIT;
return flags | RADEON_FLAG_32BIT;
case RADEON_HEAP_VRAM:
case RADEON_HEAP_GTT_WC:
@ -793,8 +760,7 @@ static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
}
/* Return the heap index for winsys allocators, or -1 on failure. */
static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
enum radeon_bo_flag flags)
static inline int radeon_get_heap_index(enum radeon_bo_domain domain, enum radeon_bo_flag flags)
{
/* VRAM implies WC (write combining) */
assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
@ -806,18 +772,13 @@ static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
return -1;
/* Unsupported flags: NO_SUBALLOC, SPARSE. */
if (flags & ~(RADEON_FLAG_GTT_WC |
RADEON_FLAG_NO_CPU_ACCESS |
RADEON_FLAG_NO_INTERPROCESS_SHARING |
RADEON_FLAG_READ_ONLY |
RADEON_FLAG_32BIT))
if (flags & ~(RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS |
RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT))
return -1;
switch (domain) {
case RADEON_DOMAIN_VRAM:
switch (flags & (RADEON_FLAG_NO_CPU_ACCESS |
RADEON_FLAG_READ_ONLY |
RADEON_FLAG_32BIT)) {
switch (flags & (RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT)) {
case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY:
assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
@ -838,9 +799,7 @@ static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
}
break;
case RADEON_DOMAIN_GTT:
switch (flags & (RADEON_FLAG_GTT_WC |
RADEON_FLAG_READ_ONLY |
RADEON_FLAG_32BIT)) {
switch (flags & (RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT)) {
case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
return RADEON_HEAP_GTT_WC_READ_ONLY_32BIT;
case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY: