r600: align for mipmap tree changes
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afe84fa698
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7118db8700
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@ -312,16 +312,7 @@ static void r600TexParameter(GLcontext * ctx, GLenum target,
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case GL_TEXTURE_MAX_LEVEL:
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case GL_TEXTURE_MIN_LOD:
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case GL_TEXTURE_MAX_LOD:
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/* This isn't the most efficient solution but there doesn't appear to
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* be a nice alternative. Since there's no LOD clamping,
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* we just have to rely on loading the right subset of mipmap levels
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* to simulate a clamped LOD.
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*/
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if (t->mt) {
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radeon_miptree_unreference(t->mt);
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t->mt = 0;
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t->validated = GL_FALSE;
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}
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t->validated = GL_FALSE;
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break;
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case GL_DEPTH_TEXTURE_MODE:
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@ -369,10 +360,8 @@ static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
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t->bo = NULL;
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}
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if (t->mt) {
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radeon_miptree_unreference(t->mt);
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t->mt = 0;
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}
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radeon_miptree_unreference(&t->mt);
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_mesa_delete_texture_object(ctx, texObj);
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}
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@ -649,7 +649,6 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
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{
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radeonTexObj *t = radeon_tex_obj(texObj);
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const struct gl_texture_image *firstImage;
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int firstlevel = t->mt ? t->mt->firstLevel : 0;
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GLuint uTexelPitch, row_align;
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if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled &&
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@ -657,7 +656,7 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
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t->bo)
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return;
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firstImage = t->base.Image[0][firstlevel];
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firstImage = t->base.Image[0][t->minLod];
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if (!t->image_override) {
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if (!r600GetTexFormat(texObj, firstImage->TexFormat)) {
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@ -692,7 +691,8 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
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}
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row_align = rmesa->radeon.texture_row_align - 1;
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uTexelPitch = ((firstImage->Width * t->mt->bpp + row_align) & ~row_align) / t->mt->bpp;
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uTexelPitch = (_mesa_format_row_stride(firstImage->TexFormat, firstImage->Width) + row_align) & ~row_align;
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uTexelPitch = uTexelPitch / _mesa_get_format_bytes(firstImage->TexFormat);
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uTexelPitch = (uTexelPitch + R700_TEXEL_PITCH_ALIGNMENT_MASK)
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& ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
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@ -706,10 +706,10 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
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SETfield(t->SQ_TEX_RESOURCE1, firstImage->Height - 1,
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TEX_HEIGHT_shift, TEX_HEIGHT_mask);
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if ((t->mt->lastLevel - t->mt->firstLevel) > 0) {
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t->SQ_TEX_RESOURCE3 = t->mt->levels[0].size / 256;
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SETfield(t->SQ_TEX_RESOURCE4, t->mt->firstLevel, BASE_LEVEL_shift, BASE_LEVEL_mask);
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SETfield(t->SQ_TEX_RESOURCE5, t->mt->lastLevel, LAST_LEVEL_shift, LAST_LEVEL_mask);
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if ((t->maxLod - t->minLod) > 0) {
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t->SQ_TEX_RESOURCE3 = t->mt->levels[t->minLod].size / 256;
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SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask);
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SETfield(t->SQ_TEX_RESOURCE5, t->maxLod - t->minLod, LAST_LEVEL_shift, LAST_LEVEL_mask);
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}
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}
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@ -808,9 +808,8 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
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struct gl_texture_object *tObj =
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_mesa_lookup_texture(rmesa->radeon.glCtx, texname);
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radeonTexObjPtr t = radeon_tex_obj(tObj);
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int firstlevel = t->mt ? t->mt->firstLevel : 0;
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const struct gl_texture_image *firstImage;
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uint32_t pitch_val, size, row_align, bpp;
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uint32_t pitch_val, size, row_align;
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if (!tObj)
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return;
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@ -820,13 +819,9 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
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if (!offset)
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return;
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bpp = depth / 8;
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if (bpp == 3)
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bpp = 4;
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firstImage = t->base.Image[0][firstlevel];
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firstImage = t->base.Image[0][t->minLod];
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row_align = rmesa->radeon.texture_row_align - 1;
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size = ((firstImage->Width * bpp + row_align) & ~row_align) * firstImage->Height;
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size = ((_mesa_format_row_stride(firstImage->TexFormat, firstImage->Width) + row_align) & ~row_align) * firstImage->Height;
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if (t->bo) {
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radeon_bo_unref(t->bo);
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t->bo = NULL;
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@ -949,14 +944,10 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
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radeon_bo_unref(rImage->bo);
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rImage->bo = NULL;
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}
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if (t->mt) {
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radeon_miptree_unreference(t->mt);
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t->mt = NULL;
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}
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if (rImage->mt) {
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radeon_miptree_unreference(rImage->mt);
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rImage->mt = NULL;
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}
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radeon_miptree_unreference(&t->mt);
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radeon_miptree_unreference(&rImage->mt);
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_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
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rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
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texImage->RowStride = rb->pitch / rb->cpp;
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@ -54,11 +54,15 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
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for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
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if (ctx->Texture.Unit[i]._ReallyEnabled) {
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radeonTexObj *t = r700->textures[i];
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uint32_t offset;
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if (t) {
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if (!t->image_override)
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if (!t->image_override) {
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bo = t->mt->bo;
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else
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offset = get_base_teximage_offset(t);
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} else {
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bo = t->bo;
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offset = 0;
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}
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if (bo) {
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r700SyncSurf(context, bo,
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@ -77,7 +81,7 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
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R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
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R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
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bo,
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0,
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offset,
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RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
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R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
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bo,
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