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radv: compute CB_SHADER_MASK from the fragment shader outputs 

The fragment shader doesn't necessarily output the number of components
expected by the target format.

Fixes new dEQP-VK.draw.output_location.*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5427>
This commit is contained in:
Samuel Pitoiset 2020-06-11 16:27:17 +02:00 committed by Marge Bot
parent b848d88059
commit 70cc80805c
3 changed files with 31 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/amd/vulkan/radv_pipeline.c
View File

@ -530,7 +530,6 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
if (blend->mrt0_is_dual_src)
col_format |= (col_format & 0xf) << 4;
blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
blend->spi_shader_col_format = col_format;
}
@ -5119,6 +5118,11 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
}
blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
if (blend.mrt0_is_dual_src) {
blend.cb_shader_mask |= (blend.cb_shader_mask & 0xf) << 4;
}
if (extra &&
(extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||

1
src/amd/vulkan/radv_shader.h
View File

@ -310,6 +310,7 @@ struct radv_shader_info {
uint32_t explicit_shaded_mask;
uint32_t float16_shaded_mask;
uint32_t num_interp;
uint32_t cb_shader_mask;
bool can_discard;
bool early_fragment_test;
bool post_depth_coverage;

25
src/amd/vulkan/radv_shader_info.c
View File

@ -537,6 +537,17 @@ gather_info_output_decl_ps(const nir_shader *nir, const nir_variable *var,
default:
break;
}
if (idx >= FRAG_RESULT_DATA0 && idx <= FRAG_RESULT_DATA7) {
unsigned num_components = glsl_get_component_slots(glsl_without_array(var->type));
unsigned num_slots = glsl_count_attribute_slots(var->type, false);
unsigned write_mask = (1 << num_components) - 1;
unsigned slot = idx - FRAG_RESULT_DATA0;
for (unsigned i = 0; i < num_slots; i++) {
info->ps.cb_shader_mask |= write_mask << ((slot + i) * 4);
}
}
}
static void
@ -834,4 +845,18 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
}
info->float_controls_mode = nir->info.float_controls_execution_mode;
if (nir->info.stage == MESA_SHADER_FRAGMENT) {
/* If the i-th output is used, all previous outputs must be
* non-zero to match the target format.
* TODO: compact MRT to avoid holes and to remove this
* workaround.
*/
unsigned num_targets = (util_last_bit(info->ps.cb_shader_mask) + 3) / 4;
for (unsigned i = 0; i < num_targets; i++) {
if (!(info->ps.cb_shader_mask & (0xf << (i * 4)))) {
info->ps.cb_shader_mask |= 0xf << (i * 4);
}
}
}
}