radeonsi: add new SDMA texture copy code
This implements:
- Linear-to-linear partial copies. (unaligned)
- Tiled-to-linear and linear-to-tiled partial copies.
(unaligned except 1-2 Bpp)
- Tiled-to-tiled partial copies aligned to 8x8.
v2: Extend the SDMA L2T VM fault workaround to T2L.
- Same algorithm, just applied to T2L.
(and using a 0-based address and surface.bo_size instead of buf->size)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
parent
a512da36ae
commit
70934de00e
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@ -90,6 +90,440 @@ static void cik_sdma_copy_buffer(struct si_context *ctx,
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r600_dma_emit_wait_idle(&ctx->b);
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}
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static unsigned minify_as_blocks(unsigned width, unsigned level, unsigned blk_w)
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{
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width = u_minify(width, level);
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return DIV_ROUND_UP(width, blk_w);
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}
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static unsigned encode_tile_info(struct si_context *sctx,
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struct r600_texture *tex, unsigned level,
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bool set_bpp)
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{
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struct radeon_info *info = &sctx->screen->b.info;
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unsigned tile_index = tex->surface.tiling_index[level];
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unsigned macro_tile_index = tex->surface.macro_tile_index;
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unsigned tile_mode = info->si_tile_mode_array[tile_index];
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unsigned macro_tile_mode = info->cik_macrotile_mode_array[macro_tile_index];
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return (set_bpp ? util_logbase2(tex->surface.bpe) : 0) |
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(G_009910_ARRAY_MODE(tile_mode) << 3) |
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(G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) |
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/* Non-depth modes don't have TILE_SPLIT set. */
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((util_logbase2(tex->surface.tile_split >> 6)) << 11) |
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(G_009990_BANK_WIDTH(macro_tile_mode) << 15) |
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(G_009990_BANK_HEIGHT(macro_tile_mode) << 18) |
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(G_009990_NUM_BANKS(macro_tile_mode) << 21) |
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(G_009990_MACRO_TILE_ASPECT(macro_tile_mode) << 24) |
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(G_009910_PIPE_CONFIG(tile_mode) << 26);
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}
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static bool cik_sdma_copy_texture(struct si_context *sctx,
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struct pipe_resource *dst,
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unsigned dst_level,
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unsigned dstx, unsigned dsty, unsigned dstz,
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struct pipe_resource *src,
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unsigned src_level,
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const struct pipe_box *src_box)
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{
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struct radeon_info *info = &sctx->screen->b.info;
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struct r600_texture *rsrc = (struct r600_texture*)src;
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struct r600_texture *rdst = (struct r600_texture*)dst;
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unsigned bpp = rdst->surface.bpe;
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uint64_t dst_address = rdst->resource.gpu_address +
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rdst->surface.level[dst_level].offset;
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uint64_t src_address = rsrc->resource.gpu_address +
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rsrc->surface.level[src_level].offset;
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unsigned dst_mode = rdst->surface.level[dst_level].mode;
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unsigned src_mode = rsrc->surface.level[src_level].mode;
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unsigned dst_tile_index = rdst->surface.tiling_index[dst_level];
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unsigned src_tile_index = rsrc->surface.tiling_index[src_level];
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unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index];
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unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
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unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
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unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
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unsigned dst_pitch = rdst->surface.level[dst_level].pitch_bytes / bpp;
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unsigned src_pitch = rsrc->surface.level[src_level].pitch_bytes / bpp;
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uint64_t dst_slice_pitch = rdst->surface.level[dst_level].slice_size / bpp;
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uint64_t src_slice_pitch = rsrc->surface.level[src_level].slice_size / bpp;
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unsigned dst_width = minify_as_blocks(rdst->resource.b.b.width0,
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dst_level, rdst->surface.blk_w);
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unsigned src_width = minify_as_blocks(rsrc->resource.b.b.width0,
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src_level, rsrc->surface.blk_w);
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unsigned dst_height = minify_as_blocks(rdst->resource.b.b.height0,
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dst_level, rdst->surface.blk_h);
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unsigned src_height = minify_as_blocks(rsrc->resource.b.b.height0,
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src_level, rsrc->surface.blk_h);
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unsigned srcx = src_box->x / rsrc->surface.blk_w;
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unsigned srcy = src_box->y / rsrc->surface.blk_h;
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unsigned srcz = src_box->z;
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unsigned copy_width = DIV_ROUND_UP(src_box->width, rsrc->surface.blk_w);
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unsigned copy_height = DIV_ROUND_UP(src_box->height, rsrc->surface.blk_h);
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unsigned copy_depth = src_box->depth;
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assert(src_level <= src->last_level);
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assert(dst_level <= dst->last_level);
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assert(rdst->surface.level[dst_level].offset +
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dst_slice_pitch * bpp * (dstz + src_box->depth) <=
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rdst->resource.buf->size);
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assert(rsrc->surface.level[src_level].offset +
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src_slice_pitch * bpp * (srcz + src_box->depth) <=
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rsrc->resource.buf->size);
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/* Test CIK with radeon and amdgpu before enabling this. */
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if (sctx->b.chip_class == CIK)
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return false;
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if (!r600_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
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dstz, rsrc, src_level, src_box))
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return false;
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dstx /= rdst->surface.blk_w;
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dsty /= rdst->surface.blk_h;
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if (srcx >= (1 << 14) ||
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srcy >= (1 << 14) ||
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srcz >= (1 << 11) ||
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dstx >= (1 << 14) ||
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dsty >= (1 << 14) ||
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dstz >= (1 << 11))
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return false;
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/* Linear -> linear sub-window copy. */
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if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
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src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
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/* check if everything fits into the bitfields */
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src_pitch <= (1 << 14) &&
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dst_pitch <= (1 << 14) &&
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src_slice_pitch <= (1 << 28) &&
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dst_slice_pitch <= (1 << 28) &&
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copy_width <= (1 << 14) &&
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copy_height <= (1 << 14) &&
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copy_depth <= (1 << 11) &&
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/* HW limitation - CIK: */
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(sctx->b.chip_class != CIK ||
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(copy_width < (1 << 14) &&
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copy_height < (1 << 14) &&
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copy_depth < (1 << 11))) &&
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/* HW limitation - some CIK parts: */
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((sctx->b.family != CHIP_BONAIRE &&
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sctx->b.family != CHIP_KAVERI) ||
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(srcx + copy_width != (1 << 14) &&
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srcy + copy_height != (1 << 14)))) {
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struct radeon_winsys_cs *cs = sctx->b.dma.cs;
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r600_need_dma_space(&sctx->b, 13);
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.dma, &rsrc->resource,
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RADEON_USAGE_READ,
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RADEON_PRIO_SDMA_TEXTURE);
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.dma, &rdst->resource,
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RADEON_USAGE_WRITE,
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RADEON_PRIO_SDMA_TEXTURE);
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radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
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CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
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(util_logbase2(bpp) << 29));
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radeon_emit(cs, src_address);
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radeon_emit(cs, src_address >> 32);
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radeon_emit(cs, srcx | (srcy << 16));
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radeon_emit(cs, srcz | ((src_pitch - 1) << 16));
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radeon_emit(cs, src_slice_pitch - 1);
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radeon_emit(cs, dst_address);
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radeon_emit(cs, dst_address >> 32);
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radeon_emit(cs, dstx | (dsty << 16));
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radeon_emit(cs, dstz | ((dst_pitch - 1) << 16));
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radeon_emit(cs, dst_slice_pitch - 1);
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if (sctx->b.chip_class == CIK) {
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radeon_emit(cs, copy_width | (copy_height << 16));
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radeon_emit(cs, copy_depth);
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} else {
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radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
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radeon_emit(cs, (copy_depth - 1));
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}
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r600_dma_emit_wait_idle(&sctx->b);
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return true;
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}
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/* Tiled <-> linear sub-window copy. */
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if ((src_mode >= RADEON_SURF_MODE_1D) != (dst_mode >= RADEON_SURF_MODE_1D)) {
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struct r600_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? rsrc : rdst;
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struct r600_texture *linear = tiled == rsrc ? rdst : rsrc;
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unsigned tiled_level = tiled == rsrc ? src_level : dst_level;
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unsigned linear_level = linear == rsrc ? src_level : dst_level;
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unsigned tiled_x = tiled == rsrc ? srcx : dstx;
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unsigned linear_x = linear == rsrc ? srcx : dstx;
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unsigned tiled_y = tiled == rsrc ? srcy : dsty;
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unsigned linear_y = linear == rsrc ? srcy : dsty;
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unsigned tiled_z = tiled == rsrc ? srcz : dstz;
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unsigned linear_z = linear == rsrc ? srcz : dstz;
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unsigned tiled_width = tiled == rsrc ? src_width : dst_width;
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unsigned linear_width = linear == rsrc ? src_width : dst_width;
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unsigned tiled_pitch = tiled == rsrc ? src_pitch : dst_pitch;
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unsigned linear_pitch = linear == rsrc ? src_pitch : dst_pitch;
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unsigned tiled_slice_pitch = tiled == rsrc ? src_slice_pitch : dst_slice_pitch;
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unsigned linear_slice_pitch = linear == rsrc ? src_slice_pitch : dst_slice_pitch;
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uint64_t tiled_address = tiled == rsrc ? src_address : dst_address;
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uint64_t linear_address = linear == rsrc ? src_address : dst_address;
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unsigned tiled_micro_mode = tiled == rsrc ? src_micro_mode : dst_micro_mode;
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assert(tiled_pitch % 8 == 0);
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assert(tiled_slice_pitch % 64 == 0);
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unsigned pitch_tile_max = tiled_pitch / 8 - 1;
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unsigned slice_tile_max = tiled_slice_pitch / 64 - 1;
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unsigned xalign = MAX2(1, 4 / bpp);
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unsigned copy_width_aligned = copy_width;
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/* If the region ends at the last pixel and is unaligned, we
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* can copy the remainder of the line that is not visible to
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* make it aligned.
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*/
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if (copy_width % xalign != 0 &&
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linear_x + copy_width == linear_width &&
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tiled_x + copy_width == tiled_width &&
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linear_x + align(copy_width, xalign) <= linear_pitch &&
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tiled_x + align(copy_width, xalign) <= tiled_pitch)
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copy_width_aligned = align(copy_width, xalign);
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/* HW limitations. */
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if ((sctx->b.family == CHIP_BONAIRE ||
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sctx->b.family == CHIP_KAVERI) &&
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linear_pitch - 1 == 0x3fff &&
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bpp == 16)
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return false;
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if (sctx->b.chip_class == CIK &&
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(copy_width_aligned == (1 << 14) ||
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copy_height == (1 << 14) ||
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copy_depth == (1 << 11)))
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return false;
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if ((sctx->b.family == CHIP_BONAIRE ||
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sctx->b.family == CHIP_KAVERI ||
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sctx->b.family == CHIP_KABINI ||
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sctx->b.family == CHIP_MULLINS) &&
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(tiled_x + copy_width == (1 << 14) ||
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tiled_y + copy_height == (1 << 14)))
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return false;
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/* The hw can read outside of the given linear buffer bounds,
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* or access those pages but not touch the memory in case
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* of writes. (it still causes a VM fault)
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*
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* Out-of-bounds memory access or page directory access must
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* be prevented.
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*/
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int64_t start_linear_address, end_linear_address;
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unsigned granularity;
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/* Deduce the size of reads from the linear surface. */
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switch (tiled_micro_mode) {
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case V_009910_ADDR_SURF_DISPLAY_MICRO_TILING:
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granularity = bpp == 1 ? 64 / (8*bpp) :
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128 / (8*bpp);
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break;
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case V_009910_ADDR_SURF_THIN_MICRO_TILING:
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case V_009910_ADDR_SURF_DEPTH_MICRO_TILING:
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if (0 /* TODO: THICK microtiling */)
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granularity = bpp == 1 ? 32 / (8*bpp) :
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bpp == 2 ? 64 / (8*bpp) :
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bpp <= 8 ? 128 / (8*bpp) :
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256 / (8*bpp);
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else
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granularity = bpp <= 2 ? 64 / (8*bpp) :
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bpp <= 8 ? 128 / (8*bpp) :
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256 / (8*bpp);
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break;
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default:
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return false;
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}
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/* The linear reads start at tiled_x & ~(granularity - 1).
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* If linear_x == 0 && tiled_x % granularity != 0, the hw
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* starts reading from an address preceding linear_address!!!
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*/
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start_linear_address =
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linear->surface.level[linear_level].offset +
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bpp * (linear_z * linear_slice_pitch +
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linear_y * linear_pitch +
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linear_x);
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start_linear_address -= (int)(bpp * (tiled_x % granularity));
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end_linear_address =
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linear->surface.level[linear_level].offset +
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bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch +
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(linear_y + copy_height - 1) * linear_pitch +
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(linear_x + copy_width));
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if ((tiled_x + copy_width) % granularity)
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end_linear_address += granularity -
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(tiled_x + copy_width) % granularity;
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if (start_linear_address < 0 ||
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end_linear_address > linear->surface.bo_size)
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return false;
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/* Check requirements. */
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if (tiled_address % 256 == 0 &&
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linear_address % 4 == 0 &&
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linear_pitch % xalign == 0 &&
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linear_x % xalign == 0 &&
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tiled_x % xalign == 0 &&
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copy_width_aligned % xalign == 0 &&
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tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING &&
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/* check if everything fits into the bitfields */
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tiled->surface.tile_split <= 4096 &&
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pitch_tile_max < (1 << 11) &&
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slice_tile_max < (1 << 22) &&
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linear_pitch <= (1 << 14) &&
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linear_slice_pitch <= (1 << 28) &&
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copy_width_aligned <= (1 << 14) &&
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copy_height <= (1 << 14) &&
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copy_depth <= (1 << 11)) {
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struct radeon_winsys_cs *cs = sctx->b.dma.cs;
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r600_need_dma_space(&sctx->b, 14);
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.dma, &rsrc->resource,
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RADEON_USAGE_READ,
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RADEON_PRIO_SDMA_TEXTURE);
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.dma, &rdst->resource,
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RADEON_USAGE_WRITE,
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RADEON_PRIO_SDMA_TEXTURE);
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radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
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CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
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((linear == rdst) << 31));
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radeon_emit(cs, tiled_address);
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radeon_emit(cs, tiled_address >> 32);
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radeon_emit(cs, tiled_x | (tiled_y << 16));
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radeon_emit(cs, tiled_z | (pitch_tile_max << 16));
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radeon_emit(cs, slice_tile_max);
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radeon_emit(cs, encode_tile_info(sctx, tiled, tiled_level, true));
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radeon_emit(cs, linear_address);
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radeon_emit(cs, linear_address >> 32);
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radeon_emit(cs, linear_x | (linear_y << 16));
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radeon_emit(cs, linear_z | ((linear_pitch - 1) << 16));
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radeon_emit(cs, linear_slice_pitch - 1);
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if (sctx->b.chip_class == CIK) {
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radeon_emit(cs, copy_width_aligned | (copy_height << 16));
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radeon_emit(cs, copy_depth);
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} else {
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radeon_emit(cs, (copy_width_aligned - 1) | ((copy_height - 1) << 16));
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radeon_emit(cs, (copy_depth - 1));
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}
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r600_dma_emit_wait_idle(&sctx->b);
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return true;
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}
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}
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/* Tiled -> Tiled sub-window copy. */
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if (dst_mode >= RADEON_SURF_MODE_1D &&
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src_mode >= RADEON_SURF_MODE_1D &&
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/* check if these fit into the bitfields */
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src_address % 256 == 0 &&
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dst_address % 256 == 0 &&
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rsrc->surface.tile_split <= 4096 &&
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rdst->surface.tile_split <= 4096 &&
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dstx % 8 == 0 &&
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dsty % 8 == 0 &&
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srcx % 8 == 0 &&
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srcy % 8 == 0 &&
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/* this can either be equal, or display->rotated (VI only) */
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(src_micro_mode == dst_micro_mode ||
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(sctx->b.chip_class == VI &&
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src_micro_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING &&
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dst_micro_mode == V_009910_ADDR_SURF_ROTATED_MICRO_TILING))) {
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assert(src_pitch % 8 == 0);
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assert(dst_pitch % 8 == 0);
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assert(src_slice_pitch % 64 == 0);
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assert(dst_slice_pitch % 64 == 0);
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unsigned src_pitch_tile_max = src_pitch / 8 - 1;
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unsigned dst_pitch_tile_max = dst_pitch / 8 - 1;
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unsigned src_slice_tile_max = src_slice_pitch / 64 - 1;
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unsigned dst_slice_tile_max = dst_slice_pitch / 64 - 1;
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unsigned copy_width_aligned = copy_width;
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unsigned copy_height_aligned = copy_height;
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/* If the region ends at the last pixel and is unaligned, we
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* can copy the remainder of the tile that is not visible to
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* make it aligned.
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*/
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if (copy_width % 8 != 0 &&
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srcx + copy_width == src_width &&
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dstx + copy_width == dst_width)
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copy_width_aligned = align(copy_width, 8);
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||||
|
||||
if (copy_height % 8 != 0 &&
|
||||
srcy + copy_height == src_height &&
|
||||
dsty + copy_height == dst_height)
|
||||
copy_height_aligned = align(copy_height, 8);
|
||||
|
||||
/* check if these fit into the bitfields */
|
||||
if (src_pitch_tile_max < (1 << 11) &&
|
||||
dst_pitch_tile_max < (1 << 11) &&
|
||||
src_slice_tile_max < (1 << 22) &&
|
||||
dst_slice_tile_max < (1 << 22) &&
|
||||
copy_width_aligned <= (1 << 14) &&
|
||||
copy_height_aligned <= (1 << 14) &&
|
||||
copy_depth <= (1 << 11) &&
|
||||
copy_width_aligned % 8 == 0 &&
|
||||
copy_height_aligned % 8 == 0 &&
|
||||
/* HW limitation - CIK: */
|
||||
(sctx->b.chip_class != CIK ||
|
||||
(copy_width_aligned < (1 << 14) &&
|
||||
copy_height_aligned < (1 << 14) &&
|
||||
copy_depth < (1 << 11))) &&
|
||||
/* HW limitation - some CIK parts: */
|
||||
((sctx->b.family != CHIP_BONAIRE &&
|
||||
sctx->b.family != CHIP_KAVERI &&
|
||||
sctx->b.family != CHIP_KABINI &&
|
||||
sctx->b.family != CHIP_MULLINS) ||
|
||||
(srcx + copy_width_aligned != (1 << 14) &&
|
||||
srcy + copy_height_aligned != (1 << 14) &&
|
||||
dstx + copy_width != (1 << 14)))) {
|
||||
struct radeon_winsys_cs *cs = sctx->b.dma.cs;
|
||||
|
||||
r600_need_dma_space(&sctx->b, 15);
|
||||
radeon_add_to_buffer_list(&sctx->b, &sctx->b.dma, &rsrc->resource,
|
||||
RADEON_USAGE_READ,
|
||||
RADEON_PRIO_SDMA_TEXTURE);
|
||||
radeon_add_to_buffer_list(&sctx->b, &sctx->b.dma, &rdst->resource,
|
||||
RADEON_USAGE_WRITE,
|
||||
RADEON_PRIO_SDMA_TEXTURE);
|
||||
|
||||
radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
|
||||
CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0));
|
||||
radeon_emit(cs, src_address);
|
||||
radeon_emit(cs, src_address >> 32);
|
||||
radeon_emit(cs, srcx | (srcy << 16));
|
||||
radeon_emit(cs, srcz | (src_pitch_tile_max << 16));
|
||||
radeon_emit(cs, src_slice_tile_max);
|
||||
radeon_emit(cs, encode_tile_info(sctx, rsrc, src_level, true));
|
||||
radeon_emit(cs, dst_address);
|
||||
radeon_emit(cs, dst_address >> 32);
|
||||
radeon_emit(cs, dstx | (dsty << 16));
|
||||
radeon_emit(cs, dstz | (dst_pitch_tile_max << 16));
|
||||
radeon_emit(cs, dst_slice_tile_max);
|
||||
radeon_emit(cs, encode_tile_info(sctx, rdst, dst_level, false));
|
||||
if (sctx->b.chip_class == CIK) {
|
||||
radeon_emit(cs, copy_width_aligned |
|
||||
(copy_height_aligned << 16));
|
||||
radeon_emit(cs, copy_depth);
|
||||
} else {
|
||||
radeon_emit(cs, (copy_width_aligned - 8) |
|
||||
((copy_height_aligned - 8) << 16));
|
||||
radeon_emit(cs, (copy_depth - 1));
|
||||
}
|
||||
|
||||
r600_dma_emit_wait_idle(&sctx->b);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static void cik_sdma_copy(struct pipe_context *ctx,
|
||||
struct pipe_resource *dst,
|
||||
unsigned dst_level,
|
||||
|
|
@ -108,6 +542,10 @@ static void cik_sdma_copy(struct pipe_context *ctx,
|
|||
return;
|
||||
}
|
||||
|
||||
if (cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
|
||||
src, src_level, src_box))
|
||||
return;
|
||||
|
||||
fallback:
|
||||
si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
|
||||
src, src_level, src_box);
|
||||
|
|
|
|||
Loading…
Reference in New Issue