tu: Fix 3d GMEM store swizzle in texture descriptor
Even though image views for attachments must use the identity swizzle,
there are cases where we have to add in our own swizzle, in particular
for D24S8 when the view is depth-only/stencil-only. Therefore we have to
reset it to the identity, similar to what we do with input attachments.
Fixes: b157a5d
("tu: Implement non-aligned multisample GMEM STORE_OP_STORE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17058>
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@ -607,29 +607,6 @@ spec@!opengl 3.2@gl-3.2-adj-prims line cull-back pv-first,Fail
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spec@!opengl 3.2@gl-3.2-adj-prims line cull-front pv-first,Fail
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spec@!opengl 3.2@gl-3.2-adj-prims pv-first,Fail
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# Failures with unaligned gmem store
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint.compatibility_depth_zero_stencil_zero_testing_stencil,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_stencil,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_8_32.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_8_32.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_8_32.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_8_32.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_49_13.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_49_13.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_49_13.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_49_13.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_5_1.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_5_1.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_5_1.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_5_1.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
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spec@!opengl 1.0@depth-clear-precision-check,Fail
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spec@!opengl 1.0@depth-clear-precision-check@depth24,Fail
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spec@!opengl 1.0@depth-clear-precision-check@depth24_stencil8,Fail
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@ -945,9 +945,15 @@ r3d_src_gmem(struct tu_cmd_buffer *cmd,
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uint32_t desc[A6XX_TEX_CONST_DWORDS];
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memcpy(desc, iview->view.descriptor, sizeof(desc));
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/* patch the format so that depth/stencil get the right format */
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desc[0] &= ~A6XX_TEX_CONST_0_FMT__MASK;
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desc[0] |= A6XX_TEX_CONST_0_FMT(tu6_format_texture(format, TILE6_2).fmt);
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/* patch the format so that depth/stencil get the right format and swizzle */
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desc[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK |
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A6XX_TEX_CONST_0_SWIZ_X__MASK | A6XX_TEX_CONST_0_SWIZ_Y__MASK |
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A6XX_TEX_CONST_0_SWIZ_Z__MASK | A6XX_TEX_CONST_0_SWIZ_W__MASK);
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desc[0] |= A6XX_TEX_CONST_0_FMT(tu6_format_texture(format, TILE6_2).fmt) |
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A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_X) |
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A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_Y) |
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A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_Z) |
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A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_W);
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/* patched for gmem */
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desc[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
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