From 7016055c82400d583385991025c3c836c5993d13 Mon Sep 17 00:00:00 2001 From: Mike Blumenkrantz Date: Tue, 31 May 2022 15:17:50 -0400 Subject: [PATCH] zink: use dynamic cull mode more dynamic states = fewer pipeline cache misses Reviewed-by: Dave Airlie Part-of: --- src/gallium/drivers/zink/zink_draw.cpp | 4 +++- src/gallium/drivers/zink/zink_pipeline.c | 3 ++- src/gallium/drivers/zink/zink_pipeline.h | 3 ++- src/gallium/drivers/zink/zink_state.c | 6 +++++- src/gallium/drivers/zink/zink_state.h | 4 ++-- 5 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/zink/zink_draw.cpp b/src/gallium/drivers/zink/zink_draw.cpp index 7d75579cf23..e4360a29a7b 100644 --- a/src/gallium/drivers/zink/zink_draw.cpp +++ b/src/gallium/drivers/zink/zink_draw.cpp @@ -702,8 +702,10 @@ zink_draw(struct pipe_context *pctx, ctx->dsa_state_changed = false; bool rast_state_changed = ctx->rast_state_changed; - if (DYNAMIC_STATE != ZINK_NO_DYNAMIC_STATE && (BATCH_CHANGED || rast_state_changed)) + if (DYNAMIC_STATE != ZINK_NO_DYNAMIC_STATE && (BATCH_CHANGED || rast_state_changed)) { VKCTX(CmdSetFrontFaceEXT)(batch->state->cmdbuf, (VkFrontFace)ctx->gfx_pipeline_state.dyn_state1.front_face); + VKCTX(CmdSetCullModeEXT)(batch->state->cmdbuf, ctx->gfx_pipeline_state.dyn_state1.cull_mode); + } if ((BATCH_CHANGED || rast_state_changed) && screen->info.have_EXT_line_rasterization && rast_state->base.line_stipple_enable) VKCTX(CmdSetLineStippleEXT)(batch->state->cmdbuf, rast_state->base.line_stipple_factor, rast_state->base.line_stipple_pattern); diff --git a/src/gallium/drivers/zink/zink_pipeline.c b/src/gallium/drivers/zink/zink_pipeline.c index e34ecac0c5d..6824fd26a99 100644 --- a/src/gallium/drivers/zink/zink_pipeline.c +++ b/src/gallium/drivers/zink/zink_pipeline.c @@ -173,7 +173,7 @@ zink_create_gfx_pipeline(struct zink_screen *screen, rast_state.depthClampEnable = hw_rast_state->depth_clamp; rast_state.rasterizerDiscardEnable = state->dyn_state2.rasterizer_discard; rast_state.polygonMode = hw_rast_state->polygon_mode; - rast_state.cullMode = hw_rast_state->cull_mode; + rast_state.cullMode = state->dyn_state1.cull_mode; rast_state.frontFace = state->dyn_state1.front_face; rast_state.depthBiasEnable = VK_TRUE; @@ -225,6 +225,7 @@ zink_create_gfx_pipeline(struct zink_screen *screen, dynamicStateEnables[state_count++] = VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT; dynamicStateEnables[state_count++] = VK_DYNAMIC_STATE_FRONT_FACE_EXT; dynamicStateEnables[state_count++] = VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT; + dynamicStateEnables[state_count++] = VK_DYNAMIC_STATE_CULL_MODE_EXT; if (state->sample_locations_enabled) dynamicStateEnables[state_count++] = VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT; } else { diff --git a/src/gallium/drivers/zink/zink_pipeline.h b/src/gallium/drivers/zink/zink_pipeline.h index 5da7f859f06..28fee65de47 100644 --- a/src/gallium/drivers/zink/zink_pipeline.h +++ b/src/gallium/drivers/zink/zink_pipeline.h @@ -41,6 +41,7 @@ struct zink_vertex_elements_state; struct zink_pipeline_dynamic_state1 { uint8_t front_face; //VkFrontFace:1 + uint8_t cull_mode; //VkCullModeFlags:2 uint16_t num_viewports; struct zink_depth_stencil_alpha_hw_state *depth_stencil_alpha_state; //must be last }; @@ -48,7 +49,7 @@ struct zink_pipeline_dynamic_state1 { struct zink_gfx_pipeline_state { uint32_t rast_state : ZINK_RAST_HW_STATE_SIZE; //zink_rasterizer_hw_state uint32_t vertices_per_patch:5; - uint32_t rast_samples:8; //2 extra bits + uint32_t rast_samples:10; //4 extra bits uint32_t void_alpha_attachments:PIPE_MAX_COLOR_BUFS; VkSampleMask sample_mask; diff --git a/src/gallium/drivers/zink/zink_state.c b/src/gallium/drivers/zink/zink_state.c index f1bd120bb85..4cf441c094c 100644 --- a/src/gallium/drivers/zink/zink_state.c +++ b/src/gallium/drivers/zink/zink_state.c @@ -587,7 +587,7 @@ zink_create_rasterizer_state(struct pipe_context *pctx, if (rs_state->fill_back != rs_state->fill_front) debug_printf("BUG: vulkan doesn't support different front and back fill modes\n"); state->hw_state.polygon_mode = rs_state->fill_front; // same values - state->hw_state.cull_mode = rs_state->cull_face; // same bits + state->cull_mode = rs_state->cull_face; // same bits state->front_face = rs_state->front_ccw ? VK_FRONT_FACE_COUNTER_CLOCKWISE : @@ -660,6 +660,10 @@ zink_bind_rasterizer_state(struct pipe_context *pctx, void *cso) ctx->gfx_pipeline_state.dyn_state1.front_face = ctx->rast_state->front_face; ctx->gfx_pipeline_state.dirty |= !zink_screen(pctx->screen)->info.have_EXT_extended_dynamic_state; } + if (ctx->gfx_pipeline_state.dyn_state1.cull_mode != ctx->rast_state->cull_mode) { + ctx->gfx_pipeline_state.dyn_state1.cull_mode = ctx->rast_state->cull_mode; + ctx->gfx_pipeline_state.dirty |= !zink_screen(pctx->screen)->info.have_EXT_extended_dynamic_state; + } if (!ctx->primitives_generated_active) zink_set_rasterizer_discard(ctx, false); else if (rasterizer_discard != ctx->rast_state->base.rasterizer_discard) diff --git a/src/gallium/drivers/zink/zink_state.h b/src/gallium/drivers/zink/zink_state.h index 09dec833ca4..c4c425467d5 100644 --- a/src/gallium/drivers/zink/zink_state.h +++ b/src/gallium/drivers/zink/zink_state.h @@ -69,7 +69,6 @@ struct zink_vertex_state { struct zink_rasterizer_hw_state { unsigned polygon_mode : 2; //VkPolygonMode - unsigned cull_mode : 2; //VkCullModeFlags unsigned line_mode : 2; //VkLineRasterizationModeEXT unsigned depth_clamp:1; unsigned pv_last:1; @@ -77,7 +76,7 @@ struct zink_rasterizer_hw_state { unsigned force_persample_interp:1; unsigned clip_halfz:1; }; -#define ZINK_RAST_HW_STATE_SIZE 11 +#define ZINK_RAST_HW_STATE_SIZE 9 struct zink_rasterizer_state { @@ -86,6 +85,7 @@ struct zink_rasterizer_state { float offset_units, offset_clamp, offset_scale; float line_width; VkFrontFace front_face; + VkCullModeFlags cull_mode; struct zink_rasterizer_hw_state hw_state; };