From 6ffdcc335ee62e0f100eff8569781499bd0a4e29 Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Tue, 2 Nov 2021 03:36:04 -0700 Subject: [PATCH] iris: Use mi_builder in iris_load_indirect_location() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For example, this allows us to take advantage of command-streamer based register offsets in mi_builder. Ref: 06cf838cbdc ("intel/mi_builder: Support gen11 command-streamer based register offsets") Signed-off-by: Jordan Justen Reviewed-by: Tapani Pälli Part-of: --- src/gallium/drivers/iris/iris_state.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 581580682ad..342bb21d94e 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6929,18 +6929,14 @@ iris_load_indirect_location(struct iris_context *ice, struct iris_state_ref *grid_size = &ice->state.grid_size; struct iris_bo *bo = iris_resource_bo(grid_size->res); - iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { - lrm.RegisterAddress = GPGPU_DISPATCHDIMX; - lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 0); - } - iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { - lrm.RegisterAddress = GPGPU_DISPATCHDIMY; - lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 4); - } - iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { - lrm.RegisterAddress = GPGPU_DISPATCHDIMZ; - lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 8); - } + struct mi_builder b; + mi_builder_init(&b, &batch->screen->devinfo, batch); + struct mi_value size_x = mi_mem32(ro_bo(bo, grid_size->offset + 0)); + struct mi_value size_y = mi_mem32(ro_bo(bo, grid_size->offset + 4)); + struct mi_value size_z = mi_mem32(ro_bo(bo, grid_size->offset + 8)); + mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMX), size_x); + mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMY), size_y); + mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMZ), size_z); } #if GFX_VERx10 >= 125