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intel/genxml: Add a partial GT_MODE definition for Gen11+. 

I chose to drop "HW" from the name of this field because on Gen11
it applies to both HW and SW binding tables, so it's a bit of a
misnomer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
This commit is contained in:
Kenneth Graunke 2019-06-25 13:15:47 -07:00 committed by Jason Ekstrand
parent 6e6cd7d93c
commit 6fb93465bd
2 changed files with 16 additions and 0 deletions
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8
src/intel/genxml/gen11.xml
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@ -6891,6 +6891,14 @@
<field name="Color Compression Disable Mask" start="31" end="31" type="bool"/>
</register>
<register name="GT_MODE" length="1" num="0x7008">
<field name="Binding Table Alignment" start="10" end="10" type="uint">
<value name="BTP_15_5" value="0"/>
<value name="BTP_18_8" value="1"/>
</field>
<field name="Binding Table Alignment Mask" start="26" end="26" type="bool"/>
</register>
<register name="CACHE_MODE_SS" length="1" num="0x0e420">
<field name="Instruction Level 1 Cache Disable" start="0" end="0" type="bool"/>
<field name="Instruction Level 1 Cache and In-Flight Queue Disable " start="1" end="1" type="bool"/>

8
src/intel/genxml/gen12.xml
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@ -7073,6 +7073,14 @@
<field name="Color Compression Disable Mask" start="31" end="31" type="bool"/>
</register>
<register name="GT_MODE" length="1" num="0x7008">
<field name="Binding Table Alignment" start="10" end="10" type="uint">
<value name="BTP_15_5" value="0"/>
<value name="BTP_18_8" value="1"/>
</field>
<field name="Binding Table Alignment Mask" start="26" end="26" type="bool"/>
</register>
<register name="CACHE_MODE_SS" length="1" num="0x0e420">
<field name="Instruction Level 1 Cache Disable" start="0" end="0" type="bool"/>
<field name="Instruction Level 1 Cache and In-Flight Queue Disable " start="1" end="1" type="bool"/>