R6xx: fix rendering on r6xx/rs780 chips
You always need to emit a fetch shader (fs) even if you aren't using it. For now, just emit the fs with the vs address to make the kernel happy.
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@ -638,6 +638,47 @@ GLboolean r700SendVSState(context_t *context)
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return GL_TRUE;
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}
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GLboolean r700SendFSState(context_t *context)
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{
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R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
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struct radeon_renderbuffer *rrb;
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struct radeon_bo * pbo;
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offset_modifiers offset_mod;
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BATCH_LOCALS(&context->radeon);
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/* XXX fixme
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* R6xx chips require a FS be emitted, even if it's not used.
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* since we aren't using FS yet, just send the VS address to make
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* the kernel command checker happy
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*/
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pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
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r700->fs.SQ_PGM_START_FS.u32All = r700->vs.SQ_PGM_START_VS.u32All;
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r700->fs.SQ_PGM_RESOURCES_FS.u32All = 0;
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r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
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/* XXX */
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offset_mod.shift = NO_SHIFT;
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offset_mod.shiftbits = 0;
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offset_mod.mask = 0xFFFFFFFF;
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BEGIN_BATCH_NO_AUTOSTATE(3);
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R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
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R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
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pbo,
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r700->fs.SQ_PGM_START_FS.u32All,
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RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
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END_BATCH();
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BEGIN_BATCH_NO_AUTOSTATE(6);
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R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, r700->fs.SQ_PGM_RESOURCES_FS.u32All);
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R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, r700->fs.SQ_PGM_CF_OFFSET_FS.u32All);
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END_BATCH();
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COMMIT_BATCH();
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return GL_TRUE;
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}
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GLboolean r700SendViewportState(context_t *context, int id)
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{
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R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
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@ -491,7 +491,7 @@ typedef struct _R700_CHIP_CONTEXT
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VS_STATE_STRUCT vs;
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GS_STATE_STRUCT gs;
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ES_STATE_STRUCT es;
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PS_STATE_STRUCT fs;
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FS_STATE_STRUCT fs;
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// SQ CONFIG
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SQ_CONFIG_STRUCT sq_config;
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@ -311,6 +311,7 @@ static GLboolean r700RunRender(GLcontext * ctx,
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r700SetupShaders(ctx);
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r700SendFSState(context); // FIXME just a place holder for now
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r700SendPSState(context);
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r700SendVSState(context);
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