winsys/amdgpu: use pb_cache instead of pb_cache_manager
This is a prerequisite for the removal of radeon_winsys_cs_handle. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
parent
3fbf250dfa
commit
6f4e74d165
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@ -37,46 +37,15 @@
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#include <xf86drm.h>
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#include <stdio.h>
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static const struct pb_vtbl amdgpu_winsys_bo_vtbl;
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static inline struct amdgpu_winsys_bo *amdgpu_winsys_bo(struct pb_buffer *bo)
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{
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assert(bo->vtbl == &amdgpu_winsys_bo_vtbl);
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return (struct amdgpu_winsys_bo *)bo;
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}
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struct amdgpu_bomgr {
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struct pb_manager base;
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struct amdgpu_winsys *rws;
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};
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static struct amdgpu_winsys *get_winsys(struct pb_manager *mgr)
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{
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return ((struct amdgpu_bomgr*)mgr)->rws;
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}
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static struct amdgpu_winsys_bo *get_amdgpu_winsys_bo(struct pb_buffer *_buf)
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{
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struct amdgpu_winsys_bo *bo = NULL;
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if (_buf->vtbl == &amdgpu_winsys_bo_vtbl) {
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bo = amdgpu_winsys_bo(_buf);
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} else {
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struct pb_buffer *base_buf;
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pb_size offset;
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pb_get_base_buffer(_buf, &base_buf, &offset);
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if (base_buf->vtbl == &amdgpu_winsys_bo_vtbl)
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bo = amdgpu_winsys_bo(base_buf);
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}
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return bo;
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}
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static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t timeout,
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enum radeon_bo_usage usage)
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{
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struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(_buf);
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struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
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struct amdgpu_winsys *ws = bo->rws;
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int i;
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@ -154,7 +123,7 @@ static enum radeon_bo_domain amdgpu_bo_get_initial_domain(
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return ((struct amdgpu_winsys_bo*)buf)->initial_domain;
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}
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static void amdgpu_bo_destroy(struct pb_buffer *_buf)
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void amdgpu_bo_destroy(struct pb_buffer *_buf)
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{
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struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
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int i;
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@ -173,6 +142,16 @@ static void amdgpu_bo_destroy(struct pb_buffer *_buf)
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FREE(bo);
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}
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static void amdgpu_bo_destroy_or_cache(struct pb_buffer *_buf)
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{
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struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
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if (bo->use_reusable_pool)
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pb_cache_add_buffer(&bo->cache_entry);
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else
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amdgpu_bo_destroy(_buf);
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}
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static void *amdgpu_bo_map(struct radeon_winsys_cs_handle *buf,
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struct radeon_winsys_cs *rcs,
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enum pipe_transfer_usage usage)
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@ -260,42 +239,18 @@ static void amdgpu_bo_unmap(struct radeon_winsys_cs_handle *buf)
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amdgpu_bo_cpu_unmap(bo->bo);
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}
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static void amdgpu_bo_get_base_buffer(struct pb_buffer *buf,
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struct pb_buffer **base_buf,
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unsigned *offset)
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{
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*base_buf = buf;
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*offset = 0;
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}
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static enum pipe_error amdgpu_bo_validate(struct pb_buffer *_buf,
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struct pb_validate *vl,
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unsigned flags)
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{
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/* Always pinned */
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return PIPE_OK;
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}
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static void amdgpu_bo_fence(struct pb_buffer *buf,
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struct pipe_fence_handle *fence)
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{
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}
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static const struct pb_vtbl amdgpu_winsys_bo_vtbl = {
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amdgpu_bo_destroy,
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NULL, /* never called */
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NULL, /* never called */
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amdgpu_bo_validate,
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amdgpu_bo_fence,
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amdgpu_bo_get_base_buffer,
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amdgpu_bo_destroy_or_cache
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/* other functions are never called */
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};
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static struct pb_buffer *amdgpu_bomgr_create_bo(struct pb_manager *_mgr,
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pb_size size,
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const struct pb_desc *desc)
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static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *rws,
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unsigned size,
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unsigned alignment,
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unsigned usage,
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enum radeon_bo_domain initial_domain,
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unsigned flags)
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{
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struct amdgpu_winsys *rws = get_winsys(_mgr);
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struct amdgpu_bo_desc *rdesc = (struct amdgpu_bo_desc*)desc;
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struct amdgpu_bo_alloc_request request = {0};
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amdgpu_bo_handle buf_handle;
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uint64_t va = 0;
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@ -303,23 +258,24 @@ static struct pb_buffer *amdgpu_bomgr_create_bo(struct pb_manager *_mgr,
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amdgpu_va_handle va_handle;
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int r;
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assert(rdesc->initial_domain & RADEON_DOMAIN_VRAM_GTT);
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assert(initial_domain & RADEON_DOMAIN_VRAM_GTT);
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bo = CALLOC_STRUCT(amdgpu_winsys_bo);
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if (!bo) {
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return NULL;
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}
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pb_cache_init_entry(&rws->bo_cache, &bo->cache_entry, &bo->base);
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request.alloc_size = size;
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request.phys_alignment = desc->alignment;
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request.phys_alignment = alignment;
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if (rdesc->initial_domain & RADEON_DOMAIN_VRAM) {
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if (initial_domain & RADEON_DOMAIN_VRAM) {
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request.preferred_heap |= AMDGPU_GEM_DOMAIN_VRAM;
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if (rdesc->flags & RADEON_FLAG_CPU_ACCESS)
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if (flags & RADEON_FLAG_CPU_ACCESS)
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request.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
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}
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if (rdesc->initial_domain & RADEON_DOMAIN_GTT) {
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if (initial_domain & RADEON_DOMAIN_GTT) {
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request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;
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if (rdesc->flags & RADEON_FLAG_GTT_WC)
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if (flags & RADEON_FLAG_GTT_WC)
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request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
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}
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@ -327,13 +283,13 @@ static struct pb_buffer *amdgpu_bomgr_create_bo(struct pb_manager *_mgr,
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if (r) {
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fprintf(stderr, "amdgpu: Failed to allocate a buffer:\n");
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fprintf(stderr, "amdgpu: size : %d bytes\n", size);
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fprintf(stderr, "amdgpu: alignment : %d bytes\n", desc->alignment);
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fprintf(stderr, "amdgpu: domains : %d\n", rdesc->initial_domain);
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fprintf(stderr, "amdgpu: alignment : %d bytes\n", alignment);
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fprintf(stderr, "amdgpu: domains : %d\n", initial_domain);
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goto error_bo_alloc;
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}
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r = amdgpu_va_range_alloc(rws->dev, amdgpu_gpu_va_range_general,
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size, desc->alignment, 0, &va, &va_handle, 0);
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size, alignment, 0, &va, &va_handle, 0);
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if (r)
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goto error_va_alloc;
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@ -342,23 +298,23 @@ static struct pb_buffer *amdgpu_bomgr_create_bo(struct pb_manager *_mgr,
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goto error_va_map;
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pipe_reference_init(&bo->base.reference, 1);
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bo->base.alignment = desc->alignment;
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bo->base.usage = desc->usage;
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bo->base.alignment = alignment;
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bo->base.usage = usage;
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bo->base.size = size;
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bo->base.vtbl = &amdgpu_winsys_bo_vtbl;
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bo->rws = rws;
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bo->bo = buf_handle;
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bo->va = va;
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bo->va_handle = va_handle;
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bo->initial_domain = rdesc->initial_domain;
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bo->initial_domain = initial_domain;
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bo->unique_id = __sync_fetch_and_add(&rws->next_bo_unique_id, 1);
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if (rdesc->initial_domain & RADEON_DOMAIN_VRAM)
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if (initial_domain & RADEON_DOMAIN_VRAM)
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rws->allocated_vram += align(size, rws->gart_page_size);
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else if (rdesc->initial_domain & RADEON_DOMAIN_GTT)
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else if (initial_domain & RADEON_DOMAIN_GTT)
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rws->allocated_gtt += align(size, rws->gart_page_size);
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return &bo->base;
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return bo;
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error_va_map:
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amdgpu_va_range_free(va_handle);
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@ -371,48 +327,15 @@ error_bo_alloc:
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return NULL;
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}
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static void amdgpu_bomgr_flush(struct pb_manager *mgr)
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{
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/* NOP */
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}
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/* This is for the cache bufmgr. */
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static boolean amdgpu_bomgr_is_buffer_busy(struct pb_manager *_mgr,
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struct pb_buffer *_buf)
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bool amdgpu_bo_can_reclaim(struct pb_buffer *_buf)
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{
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struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
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if (amdgpu_bo_is_referenced_by_any_cs(bo)) {
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return TRUE;
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return false;
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}
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if (!amdgpu_bo_wait((struct pb_buffer*)bo, 0, RADEON_USAGE_READWRITE)) {
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return TRUE;
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}
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return FALSE;
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}
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static void amdgpu_bomgr_destroy(struct pb_manager *mgr)
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{
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FREE(mgr);
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}
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struct pb_manager *amdgpu_bomgr_create(struct amdgpu_winsys *rws)
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{
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struct amdgpu_bomgr *mgr;
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mgr = CALLOC_STRUCT(amdgpu_bomgr);
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if (!mgr)
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return NULL;
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mgr->base.destroy = amdgpu_bomgr_destroy;
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mgr->base.create_buffer = amdgpu_bomgr_create_bo;
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mgr->base.flush = amdgpu_bomgr_flush;
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mgr->base.is_buffer_busy = amdgpu_bomgr_is_buffer_busy;
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mgr->rws = rws;
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return &mgr->base;
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return amdgpu_bo_wait(_buf, 0, RADEON_USAGE_READWRITE);
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}
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static unsigned eg_tile_split(unsigned tile_split)
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@ -453,7 +376,7 @@ static void amdgpu_bo_get_tiling(struct pb_buffer *_buf,
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unsigned *mtilea,
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bool *scanout)
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{
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struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(_buf);
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struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
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struct amdgpu_bo_info info = {0};
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uint32_t tiling_flags;
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int r;
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@ -494,7 +417,7 @@ static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
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uint32_t pitch,
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bool scanout)
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{
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struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(_buf);
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struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
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struct amdgpu_bo_metadata metadata = {0};
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uint32_t tiling_flags = 0;
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@ -526,7 +449,7 @@ static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
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static struct radeon_winsys_cs_handle *amdgpu_get_cs_handle(struct pb_buffer *_buf)
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{
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/* return a direct pointer to amdgpu_winsys_bo. */
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return (struct radeon_winsys_cs_handle*)get_amdgpu_winsys_bo(_buf);
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return (struct radeon_winsys_cs_handle*)_buf;
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}
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static struct pb_buffer *
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@ -538,9 +461,8 @@ amdgpu_bo_create(struct radeon_winsys *rws,
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enum radeon_bo_flag flags)
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{
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struct amdgpu_winsys *ws = amdgpu_winsys(rws);
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struct amdgpu_bo_desc desc;
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struct pb_manager *provider;
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struct pb_buffer *buffer;
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struct amdgpu_winsys_bo *bo;
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unsigned usage = 0;
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/* Don't use VRAM if the GPU doesn't have much. This is only the initial
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* domain. The kernel is free to move the buffer if it wants to.
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@ -552,9 +474,6 @@ amdgpu_bo_create(struct radeon_winsys *rws,
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flags = RADEON_FLAG_GTT_WC;
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}
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memset(&desc, 0, sizeof(desc));
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desc.base.alignment = alignment;
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/* Align size to page size. This is the minimum alignment for normal
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* BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
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* like constant/uniform buffers, can benefit from better and more reuse.
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@ -565,26 +484,28 @@ amdgpu_bo_create(struct radeon_winsys *rws,
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* might consider different sets of domains / flags compatible
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*/
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if (domain == RADEON_DOMAIN_VRAM_GTT)
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desc.base.usage = 1 << 2;
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usage = 1 << 2;
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else
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desc.base.usage = domain >> 1;
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assert(flags < sizeof(desc.base.usage) * 8 - 3);
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desc.base.usage |= 1 << (flags + 3);
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usage = domain >> 1;
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assert(flags < sizeof(usage) * 8 - 3);
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usage |= 1 << (flags + 3);
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desc.initial_domain = domain;
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desc.flags = flags;
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/* Get a buffer from the cache. */
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if (use_reusable_pool) {
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bo = (struct amdgpu_winsys_bo*)
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pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment,
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usage);
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if (bo)
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return &bo->base;
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}
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/* Assign a buffer manager. */
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if (use_reusable_pool)
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provider = ws->cman;
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else
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provider = ws->kman;
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buffer = provider->create_buffer(provider, size, &desc.base);
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if (!buffer)
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/* Create a new one. */
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bo = amdgpu_create_bo(ws, size, alignment, usage, domain, flags);
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if (!bo)
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return NULL;
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return (struct pb_buffer*)buffer;
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bo->use_reusable_pool = use_reusable_pool;
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return &bo->base;
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}
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static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws,
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@ -680,12 +601,11 @@ static boolean amdgpu_bo_get_handle(struct pb_buffer *buffer,
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unsigned stride,
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struct winsys_handle *whandle)
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{
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struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(buffer);
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struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(buffer);
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enum amdgpu_bo_handle_type type;
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int r;
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if ((void*)bo != (void*)buffer)
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pb_cache_manager_remove_buffer(buffer);
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bo->use_reusable_pool = false;
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switch (whandle->type) {
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case DRM_API_HANDLE_TYPE_SHARED:
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@ -767,7 +687,7 @@ static uint64_t amdgpu_bo_get_va(struct radeon_winsys_cs_handle *buf)
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return ((struct amdgpu_winsys_bo*)buf)->va;
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}
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void amdgpu_bomgr_init_functions(struct amdgpu_winsys *ws)
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void amdgpu_bo_init_functions(struct amdgpu_winsys *ws)
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{
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ws->base.buffer_get_cs_handle = amdgpu_get_cs_handle;
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ws->base.buffer_set_tiling = amdgpu_bo_set_tiling;
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@ -36,15 +36,9 @@
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#include "amdgpu_winsys.h"
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#include "pipebuffer/pb_bufmgr.h"
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struct amdgpu_bo_desc {
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struct pb_desc base;
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enum radeon_bo_domain initial_domain;
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unsigned flags;
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};
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struct amdgpu_winsys_bo {
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struct pb_buffer base;
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struct pb_cache_entry cache_entry;
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struct amdgpu_winsys *rws;
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void *user_ptr; /* from buffer_from_ptr */
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@ -54,6 +48,7 @@ struct amdgpu_winsys_bo {
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amdgpu_va_handle va_handle;
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uint64_t va;
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enum radeon_bo_domain initial_domain;
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bool use_reusable_pool;
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/* how many command streams is this bo referenced in? */
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int num_cs_references;
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@ -67,8 +62,9 @@ struct amdgpu_winsys_bo {
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struct pipe_fence_handle *fence[RING_LAST];
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};
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struct pb_manager *amdgpu_bomgr_create(struct amdgpu_winsys *rws);
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void amdgpu_bomgr_init_functions(struct amdgpu_winsys *ws);
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bool amdgpu_bo_can_reclaim(struct pb_buffer *_buf);
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void amdgpu_bo_destroy(struct pb_buffer *_buf);
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void amdgpu_bo_init_functions(struct amdgpu_winsys *ws);
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static inline
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void amdgpu_winsys_bo_reference(struct amdgpu_winsys_bo **dst,
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@ -304,11 +304,8 @@ static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
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struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
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pipe_mutex_destroy(ws->bo_fence_lock);
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||||
ws->cman->destroy(ws->cman);
|
||||
ws->kman->destroy(ws->kman);
|
||||
pb_cache_deinit(&ws->bo_cache);
|
||||
AddrDestroy(ws->addrlib);
|
||||
|
||||
amdgpu_device_deinitialize(ws->dev);
|
||||
FREE(rws);
|
||||
}
|
||||
|
@ -461,13 +458,9 @@ amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
|
|||
goto fail;
|
||||
|
||||
/* Create managers. */
|
||||
ws->kman = amdgpu_bomgr_create(ws);
|
||||
if (!ws->kman)
|
||||
goto fail;
|
||||
ws->cman = pb_cache_manager_create(ws->kman, 500000, 2.0f, 0,
|
||||
(ws->info.vram_size + ws->info.gart_size) / 8);
|
||||
if (!ws->cman)
|
||||
goto fail;
|
||||
pb_cache_init(&ws->bo_cache, 500000, 2.0f, 0,
|
||||
(ws->info.vram_size + ws->info.gart_size) / 8,
|
||||
amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
|
||||
|
||||
/* init reference */
|
||||
pipe_reference_init(&ws->reference, 1);
|
||||
|
@ -480,7 +473,7 @@ amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
|
|||
ws->base.query_value = amdgpu_query_value;
|
||||
ws->base.read_registers = amdgpu_read_registers;
|
||||
|
||||
amdgpu_bomgr_init_functions(ws);
|
||||
amdgpu_bo_init_functions(ws);
|
||||
amdgpu_cs_init_functions(ws);
|
||||
amdgpu_surface_init_functions(ws);
|
||||
|
||||
|
@ -509,10 +502,7 @@ amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
|
|||
|
||||
fail:
|
||||
pipe_mutex_unlock(dev_tab_mutex);
|
||||
if (ws->cman)
|
||||
ws->cman->destroy(ws->cman);
|
||||
if (ws->kman)
|
||||
ws->kman->destroy(ws->kman);
|
||||
pb_cache_deinit(&ws->bo_cache);
|
||||
FREE(ws);
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
@ -32,6 +32,7 @@
|
|||
#ifndef AMDGPU_WINSYS_H
|
||||
#define AMDGPU_WINSYS_H
|
||||
|
||||
#include "pipebuffer/pb_cache.h"
|
||||
#include "gallium/drivers/radeon/radeon_winsys.h"
|
||||
#include "addrlib/addrinterface.h"
|
||||
#include "os/os_thread.h"
|
||||
|
@ -42,6 +43,7 @@ struct amdgpu_cs;
|
|||
struct amdgpu_winsys {
|
||||
struct radeon_winsys base;
|
||||
struct pipe_reference reference;
|
||||
struct pb_cache bo_cache;
|
||||
|
||||
amdgpu_device_handle dev;
|
||||
|
||||
|
@ -57,9 +59,6 @@ struct amdgpu_winsys {
|
|||
|
||||
struct radeon_info info;
|
||||
|
||||
struct pb_manager *kman;
|
||||
struct pb_manager *cman;
|
||||
|
||||
struct amdgpu_gpu_info amdinfo;
|
||||
ADDR_HANDLE addrlib;
|
||||
uint32_t rev_id;
|
||||
|
|
Loading…
Reference in New Issue