panfrost: Separate core ID range from core count
To query the core count, the hardware has a SHADERS_PRESENT register containing a mask of shader cores connected. The core count equals the number of 1-bits, regardless of placement. This value is useful for public consumption (like in clinfo). However, internally we are interested in the range of core IDs. We usually query core count to determine how many cores to allocate various per-core buffers for (performance counters, occlusion queries, and the stack). In each case, the hardware writes at the index of its core ID, so we have to allocate enough for entire range of core IDs. If the core mask is discontiguous, this necessarily overallocates. Rename the existing core_count to core_id_range, better reflecting its definition and purpose, and repurpose core_count for the actual core count. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17265>
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@ -1585,7 +1585,7 @@ panfrost_emit_shared_memory(struct panfrost_batch *batch,
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panfrost_batch_get_scratchpad(batch,
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ss->info.tls_size,
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dev->thread_tls_alloc,
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dev->core_count);
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dev->core_id_range);
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info.tls.ptr = bo->ptr.gpu;
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}
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@ -1593,7 +1593,7 @@ panfrost_emit_shared_memory(struct panfrost_batch *batch,
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unsigned size =
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pan_wls_adjust_size(info.wls.size) *
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pan_wls_instances(&info.wls.dim) *
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dev->core_count;
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dev->core_id_range;
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struct panfrost_bo *bo =
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panfrost_batch_get_shared_memory(batch, size, 1);
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@ -2732,7 +2732,7 @@ emit_tls(struct panfrost_batch *batch)
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panfrost_batch_get_scratchpad(batch,
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batch->stack_size,
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dev->thread_tls_alloc,
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dev->core_count):
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dev->core_id_range):
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NULL;
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struct pan_tls_info tls = {
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.tls = {
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@ -2754,7 +2754,7 @@ emit_fbd(struct panfrost_batch *batch, const struct pan_fb_info *fb)
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panfrost_batch_get_scratchpad(batch,
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batch->stack_size,
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dev->thread_tls_alloc,
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dev->core_count):
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dev->core_id_range):
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NULL;
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struct pan_tls_info tls = {
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.tls = {
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@ -869,7 +869,7 @@ panfrost_begin_query(struct pipe_context *pipe, struct pipe_query *q)
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case PIPE_QUERY_OCCLUSION_COUNTER:
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case PIPE_QUERY_OCCLUSION_PREDICATE:
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case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
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unsigned size = sizeof(uint64_t) * dev->core_count;
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unsigned size = sizeof(uint64_t) * dev->core_id_range;
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/* Allocate a resource for the query results to be stored */
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if (!query->rsrc) {
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@ -953,7 +953,7 @@ panfrost_get_query_result(struct pipe_context *pipe,
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if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
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uint64_t passed = 0;
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for (int i = 0; i < dev->core_count; ++i)
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for (int i = 0; i < dev->core_id_range; ++i)
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passed += result[i];
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if (dev->arch <= 5 && !query->msaa)
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@ -388,11 +388,11 @@ struct panfrost_bo *
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panfrost_batch_get_scratchpad(struct panfrost_batch *batch,
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unsigned size_per_thread,
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unsigned thread_tls_alloc,
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unsigned core_count)
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unsigned core_id_range)
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{
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unsigned size = panfrost_get_total_stack_size(size_per_thread,
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thread_tls_alloc,
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core_count);
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core_id_range);
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if (batch->scratchpad) {
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assert(batch->scratchpad->size >= size);
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@ -251,7 +251,7 @@ void
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panfrost_batch_adjust_stack_size(struct panfrost_batch *batch);
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struct panfrost_bo *
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panfrost_batch_get_scratchpad(struct panfrost_batch *batch, unsigned size, unsigned thread_tls_alloc, unsigned core_count);
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panfrost_batch_get_scratchpad(struct panfrost_batch *batch, unsigned size, unsigned thread_tls_alloc, unsigned core_id_range);
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struct panfrost_bo *
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panfrost_batch_get_shared_memory(struct panfrost_batch *batch, unsigned size, unsigned workgroup_count);
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@ -144,7 +144,7 @@ pan_wls_mem_size(const struct panfrost_device *dev,
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{
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unsigned instances = pan_wls_instances(dim);
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return pan_wls_adjust_size(wls_size) * instances * dev->core_count;
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return pan_wls_adjust_size(wls_size) * instances * dev->core_id_range;
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}
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#ifdef PAN_ARCH
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@ -184,7 +184,15 @@ struct panfrost_device {
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unsigned arch;
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unsigned gpu_id;
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unsigned revision;
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/* Number of shader cores */
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unsigned core_count;
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/* Range of core IDs, equal to the maximum core ID + 1. Satisfies
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* core_id_range >= core_count.
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*/
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unsigned core_id_range;
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unsigned thread_tls_alloc;
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struct panfrost_tiler_features tiler_features;
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const struct panfrost_model *model;
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@ -75,7 +75,7 @@ unsigned
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panfrost_get_total_stack_size(
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unsigned thread_size,
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unsigned threads_per_core,
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unsigned core_count);
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unsigned core_id_range);
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/* Attributes / instancing */
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@ -152,20 +152,21 @@ panfrost_query_tiler_features(int fd)
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}
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static unsigned
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panfrost_query_core_count(int fd)
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panfrost_query_core_count(int fd, unsigned *core_id_range)
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{
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/* On older kernels, worst-case to 16 cores */
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unsigned mask = panfrost_query_raw(fd,
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DRM_PANFROST_PARAM_SHADER_PRESENT, false, 0xffff);
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/* Some cores might be absent. For TLS computation purposes, we care
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* about the greatest ID + 1, which equals the core count if all cores
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* are present, but allocates space for absent cores if needed.
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* util_last_bit is defined to return the greatest bit set + 1, which
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* is exactly what we need. */
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/* Some cores might be absent. In some cases, we care
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* about the range of core IDs (that is, the greatest core ID + 1). If
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* the core mask is contiguous, this equals the core count.
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*/
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*core_id_range = util_last_bit(mask);
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return util_last_bit(mask);
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/* The actual core count skips overs the gaps */
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return util_bitcount(mask);
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}
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/* Architectural maximums, since this register may be not implemented
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@ -263,7 +264,7 @@ panfrost_open_device(void *memctx, int fd, struct panfrost_device *dev)
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dev->memctx = memctx;
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dev->gpu_id = panfrost_query_gpu_version(fd);
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dev->arch = pan_arch(dev->gpu_id);
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dev->core_count = panfrost_query_core_count(fd);
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dev->core_count = panfrost_query_core_count(fd, &dev->core_id_range);
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dev->thread_tls_alloc = panfrost_query_thread_tls_alloc(fd, dev->arch);
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dev->kernel_version = drmGetVersion(fd);
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dev->revision = panfrost_query_gpu_revision(fd);
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@ -78,10 +78,10 @@ unsigned
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panfrost_get_total_stack_size(
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unsigned thread_size,
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unsigned threads_per_core,
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unsigned core_count)
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unsigned core_id_range)
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{
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unsigned size_per_thread = (thread_size == 0) ? 0 :
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util_next_power_of_two(ALIGN_POT(thread_size, 16));
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return size_per_thread * threads_per_core * core_count;
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return size_per_thread * threads_per_core * core_id_range;
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}
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@ -42,7 +42,7 @@ panfrost_perf_counter_read(const struct panfrost_perf_counter *counter,
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// If counter belongs to shader core, accumulate values for all other cores
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if (counter->category_index == PAN_SHADER_CORE_INDEX) {
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for (uint32_t core = 1; core < perf->dev->core_count; ++core) {
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for (uint32_t core = 1; core < perf->dev->core_id_range; ++core) {
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ret += perf->counter_values[offset + PAN_COUNTERS_PER_CATEGORY * core];
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}
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}
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@ -77,7 +77,7 @@ panfrost_perf_init(struct panfrost_perf *perf, struct panfrost_device *dev)
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// Generally counter blocks are laid out in the following order:
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// Job manager, tiler, one or more L2 caches, and one or more shader cores.
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unsigned l2_slices = panfrost_query_l2_slices(dev);
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uint32_t n_blocks = 2 + l2_slices + dev->core_count;
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uint32_t n_blocks = 2 + l2_slices + dev->core_id_range;
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perf->n_counter_values = PAN_COUNTERS_PER_CATEGORY * n_blocks;
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perf->counter_values = ralloc_array(perf, uint32_t, perf->n_counter_values);
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@ -118,7 +118,7 @@ panvk_per_arch(cmd_close_batch)(struct panvk_cmd_buffer *cmdbuf)
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if (batch->tlsinfo.tls.size) {
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unsigned size = panfrost_get_total_stack_size(batch->tlsinfo.tls.size,
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pdev->thread_tls_alloc,
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pdev->core_count);
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pdev->core_id_range);
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batch->tlsinfo.tls.ptr =
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pan_pool_alloc_aligned(&cmdbuf->tls_pool.base, size, 4096).gpu;
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}
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