radeonsi/gfx9: update HTILE/CMASK/FMASK allocators
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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281542c690
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6f09b0d076
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@ -593,6 +593,12 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
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memset(out, 0, sizeof(*out));
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memset(out, 0, sizeof(*out));
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if (rscreen->chip_class >= GFX9) {
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out->alignment = rtex->surface.u.gfx9.fmask_alignment;
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out->size = rtex->surface.u.gfx9.fmask_size;
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return;
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}
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templ.nr_samples = 1;
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templ.nr_samples = 1;
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flags = rtex->surface.flags | RADEON_SURF_FMASK;
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flags = rtex->surface.flags | RADEON_SURF_FMASK;
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@ -698,6 +704,12 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
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unsigned num_pipes = rscreen->info.num_tile_pipes;
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unsigned num_pipes = rscreen->info.num_tile_pipes;
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unsigned cl_width, cl_height;
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unsigned cl_width, cl_height;
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if (rscreen->chip_class >= GFX9) {
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out->alignment = rtex->surface.u.gfx9.cmask_alignment;
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out->size = rtex->surface.u.gfx9.cmask_size;
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return;
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}
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switch (num_pipes) {
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switch (num_pipes) {
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case 2:
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case 2:
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cl_width = 32;
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cl_width = 32;
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@ -799,6 +811,8 @@ static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
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unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
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unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
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unsigned num_pipes = rscreen->info.num_tile_pipes;
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unsigned num_pipes = rscreen->info.num_tile_pipes;
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assert(rscreen->chip_class <= VI);
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rtex->surface.htile_size = 0;
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rtex->surface.htile_size = 0;
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if (rscreen->chip_class <= EVERGREEN &&
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if (rscreen->chip_class <= EVERGREEN &&
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@ -873,7 +887,7 @@ static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
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{
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{
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uint32_t clear_value;
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uint32_t clear_value;
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if (rtex->tc_compatible_htile) {
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if (rscreen->chip_class >= GFX9 || rtex->tc_compatible_htile) {
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clear_value = 0x0000030F;
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clear_value = 0x0000030F;
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} else {
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} else {
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r600_texture_get_htile_size(rscreen, rtex);
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r600_texture_get_htile_size(rscreen, rtex);
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