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Merge branch '965-glsl' 

Conflicts:

	src/mesa/drivers/dri/i965/brw_sf.h
	src/mesa/drivers/dri/i965/intel_context.c
This commit is contained in:
Zou Nan hai 2007-10-26 15:39:50 +08:00
parent ff042bfdee de803f538c
commit 6ef27b88e6
25 changed files with 1868 additions and 170 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
progs/glsl/CH11-toyball.frag.txt
View File

@ -49,14 +49,15 @@ void main()
inorout += dot(distance, vec4(1.0));
distance.x = dot(p, HalfSpace4);
distance.y = StripeWidth - abs(p.z);
// distance.y = StripeWidth - abs(p.z);
distance.y = StripeWidth - abs(p.y);
distance = smoothstep(-FWidth, FWidth, distance);
inorout += distance.x;
inorout = clamp(inorout, 0.0, 1.0);
surfColor = mix(Yellow, Red, inorout);
surfColor = mix(surfColor, Blue, distance.y);
surfColor = mix(Yellow, Blue, distance.y);
surfColor = mix(surfColor, Red, inorout);
// normal = point on surface for sphere at (0,0,0)
normal = p;

7
progs/glsl/CH11-toyball.vert.txt
View File

@ -14,10 +14,11 @@ uniform vec4 BallCenter; // ball center in modelling coordinates
void main()
{
//orig: ECposition = gl_ModelViewMatrix * gl_Vertex;
ECposition = gl_ModelViewMatrix * gl_Vertex;
ECposition = gl_TextureMatrix[0] * gl_Vertex;
ECposition = gl_ModelViewMatrix * ECposition;
// ECposition = gl_TextureMatrix[0] * gl_Vertex;
// ECposition = gl_MultiTexCoord0 * gl_Vertex;
// ECposition = gl_ModelViewMatrix * ECposition;
ECballCenter = gl_ModelViewMatrix * BallCenter;
gl_Position = ftransform();

1
src/mesa/drivers/dri/i965/Makefile
View File

@ -69,6 +69,7 @@ DRIVER_SOURCES = \
brw_wm_emit.c \
brw_wm_fp.c \
brw_wm_iz.c \
brw_wm_glsl.c \
brw_wm_pass0.c \
brw_wm_pass1.c \
brw_wm_pass2.c \

4
src/mesa/drivers/dri/i965/brw_clip.h
View File

@ -42,7 +42,7 @@
* up polygon offset and flatshading at this point:
*/
struct brw_clip_prog_key {
GLuint attrs:16;
GLuint attrs:32;
GLuint primitive:4;
GLuint nr_userclip:3;
GLuint do_flat_shading:1;
@ -51,7 +51,7 @@ struct brw_clip_prog_key {
GLuint fill_ccw:2; /* includes cull information */
GLuint offset_cw:1;
GLuint offset_ccw:1;
GLuint pad0:1;
GLuint pad0:17;
GLuint copy_bfc_cw:1;
GLuint copy_bfc_ccw:1;

27
src/mesa/drivers/dri/i965/brw_context.c
View File

@ -43,6 +43,8 @@
#include "api_noop.h"
#include "vtxfmt.h"
#include "shader/shader_api.h"
/***************************************
* Mesa's Driver Functions
***************************************/
@ -59,12 +61,37 @@ static const struct dri_extension brw_extensions[] =
{ NULL, NULL }
};
static void brwUseProgram(GLcontext *ctx, GLuint program)
{
struct brw_context *brw = brw_context(ctx);
struct gl_shader_program *sh_prog;
_mesa_use_program(ctx, program);
sh_prog = ctx->Shader.CurrentProgram;
if (sh_prog) {
if (sh_prog->VertexProgram) {
brw->attribs.VertexProgram->Current = sh_prog->VertexProgram;
ctx->VertexProgram.Enabled = GL_TRUE;
}else
ctx->VertexProgram.Enabled = GL_FALSE;
if (sh_prog->FragmentProgram) {
brw->attribs.FragmentProgram->Current = sh_prog->FragmentProgram;
ctx->FragmentProgram.Enabled = GL_TRUE;
} else
ctx->FragmentProgram.Enabled = GL_FALSE;
}
}
static void brwInitProgFuncs( struct dd_function_table *functions )
{
functions->UseProgram = brwUseProgram;
}
static void brwInitDriverFunctions( struct dd_function_table *functions )
{
intelInitDriverFunctions( functions );
brwInitTextureFuncs( functions );
brwInitFragProgFuncs( functions );
brwInitProgFuncs( functions );
}

17
src/mesa/drivers/dri/i965/brw_eu.h
View File

@ -648,6 +648,11 @@ static __inline struct brw_reg deref_1uw(struct brw_indirect ptr, GLint offset)
return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW);
}
static __inline struct brw_reg deref_1ud(struct brw_indirect ptr, GLint offset)
{
return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD);
}
static __inline struct brw_reg get_addr_reg(struct brw_indirect ptr)
{
return brw_address_reg(ptr.addr_subnr);
@ -668,7 +673,10 @@ static __inline struct brw_indirect brw_indirect( GLuint addr_subnr, GLint offse
return ptr;
}
static __inline struct brw_instruction *current_insn( struct brw_compile *p)
{
return &p->store[p->nr_insn];
}
void brw_pop_insn_state( struct brw_compile *p );
void brw_push_insn_state( struct brw_compile *p );
@ -808,9 +816,11 @@ void brw_ENDIF(struct brw_compile *p,
struct brw_instruction *brw_DO(struct brw_compile *p,
GLuint execute_size);
void brw_WHILE(struct brw_compile *p,
struct brw_instruction *brw_WHILE(struct brw_compile *p,
struct brw_instruction *patch_insn);
struct brw_instruction *brw_BREAK(struct brw_compile *p);
struct brw_instruction *brw_CONT(struct brw_compile *p);
/* Forward jumps:
*/
void brw_land_fwd_jump(struct brw_compile *p,
@ -860,5 +870,6 @@ void brw_math_invert( struct brw_compile *p,
struct brw_reg dst,
struct brw_reg src);
void brw_set_src1( struct brw_instruction *insn,
struct brw_reg reg );
#endif

44
src/mesa/drivers/dri/i965/brw_eu_emit.c
View File

@ -164,7 +164,7 @@ static void brw_set_src0( struct brw_instruction *insn,
}
static void brw_set_src1( struct brw_instruction *insn,
void brw_set_src1( struct brw_instruction *insn,
struct brw_reg reg )
{
assert(reg.file != BRW_MESSAGE_REGISTER_FILE);
@ -186,7 +186,7 @@ static void brw_set_src1( struct brw_instruction *insn,
* in the future:
*/
assert (reg.address_mode == BRW_ADDRESS_DIRECT);
assert (reg.file == BRW_GENERAL_REGISTER_FILE);
//assert (reg.file == BRW_GENERAL_REGISTER_FILE);
if (insn->header.access_mode == BRW_ALIGN_1) {
insn->bits3.da1.src1_subreg_nr = reg.subnr;
@ -597,6 +597,34 @@ void brw_ENDIF(struct brw_compile *p,
}
}
struct brw_instruction *brw_BREAK(struct brw_compile *p)
{
struct brw_instruction *insn;
insn = next_insn(p, BRW_OPCODE_BREAK);
brw_set_dest(insn, brw_ip_reg());
brw_set_src0(insn, brw_ip_reg());
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = BRW_EXECUTE_8;
insn->header.mask_control = BRW_MASK_DISABLE;
insn->bits3.if_else.pad0 = 0;
return insn;
}
struct brw_instruction *brw_CONT(struct brw_compile *p)
{
struct brw_instruction *insn;
insn = next_insn(p, BRW_OPCODE_CONTINUE);
brw_set_dest(insn, brw_ip_reg());
brw_set_src0(insn, brw_ip_reg());
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = BRW_EXECUTE_8;
insn->header.mask_control = BRW_MASK_DISABLE;
insn->bits3.if_else.pad0 = 0;
return insn;
}
/* DO/WHILE loop:
*/
struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
@ -608,13 +636,15 @@ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
/* Override the defaults for this instruction:
*/
brw_set_dest(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src0(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src1(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_dest(insn, brw_null_reg());
brw_set_src0(insn, brw_null_reg());
brw_set_src1(insn, brw_null_reg());
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = execute_size;
insn->header.predicate_control = BRW_PREDICATE_NONE;
/* insn->header.mask_control = BRW_MASK_ENABLE; */
insn->header.mask_control = BRW_MASK_DISABLE;
return insn;
}
@ -622,7 +652,7 @@ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
void brw_WHILE(struct brw_compile *p,
struct brw_instruction *brw_WHILE(struct brw_compile *p,
struct brw_instruction *do_insn)
{
struct brw_instruction *insn;
@ -653,7 +683,9 @@ void brw_WHILE(struct brw_compile *p,
/* insn->header.mask_control = BRW_MASK_ENABLE; */
insn->header.mask_control = BRW_MASK_DISABLE;
p->current->header.predicate_control = BRW_PREDICATE_NONE;
return insn;
}

4
src/mesa/drivers/dri/i965/brw_gs.h
View File

@ -40,11 +40,11 @@
#define MAX_GS_VERTS (4)
struct brw_gs_prog_key {
GLuint attrs:32;
GLuint primitive:4;
GLuint attrs:16;
GLuint hint_gs_always:1;
GLuint need_gs_prog:1;
GLuint pad:10;
GLuint pad:26;
};
struct brw_gs_compile {

2
src/mesa/drivers/dri/i965/brw_sf.h
View File

@ -45,10 +45,10 @@
#define SF_UNFILLED_TRIS 3
struct brw_sf_prog_key {
GLuint attrs:32;
GLuint primitive:2;
GLuint do_twoside_color:1;
GLuint do_flat_shading:1;
GLuint attrs:16;
GLuint frontface_ccw:1;
GLuint do_point_sprite:1;
GLuint pad:10;

6
src/mesa/drivers/dri/i965/brw_vs.h
View File

@ -67,6 +67,12 @@ struct brw_vs_compile {
struct brw_reg r1;
struct brw_reg regs[PROGRAM_ADDRESS+1][128];
struct brw_reg tmp;
struct brw_reg stack;
struct {
GLboolean used_in_src;
struct brw_reg reg;
} output_regs[128];
struct brw_reg userplane[6];

257
src/mesa/drivers/dri/i965/brw_vs_emit.c
View File

@ -134,6 +134,16 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
WRITEMASK_X);
reg++;
}
for (i = 0; i < 128; i++) {
if (c->output_regs[i].used_in_src) {
c->output_regs[i].reg = brw_vec8_grf(reg, 0);
reg++;
}
}
c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, reg, 0);
reg += 2;
/* Some opcodes need an internal temporary:
@ -213,57 +223,68 @@ static void unalias2( struct brw_vs_compile *c,
}
}
static void emit_sop( struct brw_compile *p,
struct brw_reg dst,
struct brw_reg arg0,
struct brw_reg arg1,
GLuint cond)
{
brw_push_insn_state(p);
brw_CMP(p, brw_null_reg(), cond, arg0, arg1);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
brw_MOV(p, dst, brw_imm_f(1.0f));
brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
brw_MOV(p, dst, brw_imm_f(0.0f));
brw_pop_insn_state(p);
}
static void emit_seq( struct brw_compile *p,
struct brw_reg dst,
struct brw_reg arg0,
struct brw_reg arg1 )
{
emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_EQ);
}
static void emit_sne( struct brw_compile *p,
struct brw_reg dst,
struct brw_reg arg0,
struct brw_reg arg1 )
{
emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_NEQ);
}
static void emit_slt( struct brw_compile *p,
struct brw_reg dst,
struct brw_reg arg0,
struct brw_reg arg1 )
{
/* Could be done with an if/else/endif, but this method uses half
* the instructions. Note that we are careful to reference the
* arguments before writing the dest. That means we emit the
* instructions in an odd order and have to play with the flag
* values.
*/
brw_push_insn_state(p);
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0, arg1);
/* Write all values to 1:
*/
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
brw_MOV(p, dst, brw_imm_f(1.0));
/* Where the test succeeded, overwite with zero:
*/
brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
brw_MOV(p, dst, brw_imm_f(0.0));
brw_pop_insn_state(p);
emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_L);
}
static void emit_sle( struct brw_compile *p,
struct brw_reg dst,
struct brw_reg arg0,
struct brw_reg arg1 )
{
emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_LE);
}
static void emit_sgt( struct brw_compile *p,
struct brw_reg dst,
struct brw_reg arg0,
struct brw_reg arg1 )
{
emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_G);
}
static void emit_sge( struct brw_compile *p,
struct brw_reg dst,
struct brw_reg arg0,
struct brw_reg arg1 )
{
brw_push_insn_state(p);
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0, arg1);
/* Write all values to zero:
*/
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
brw_MOV(p, dst, brw_imm_f(0));
/* Where the test succeeded, overwite with 1:
*/
brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
brw_MOV(p, dst, brw_imm_f(1.0));
brw_pop_insn_state(p);
emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_GE);
}
static void emit_max( struct brw_compile *p,
struct brw_reg dst,
struct brw_reg arg0,
@ -592,9 +613,13 @@ static struct brw_reg get_reg( struct brw_vs_compile *c,
case PROGRAM_TEMPORARY:
case PROGRAM_INPUT:
case PROGRAM_OUTPUT:
case PROGRAM_STATE_VAR:
assert(c->regs[file][index].nr != 0);
return c->regs[file][index];
case PROGRAM_STATE_VAR:
case PROGRAM_CONSTANT:
case PROGRAM_UNIFORM:
assert(c->regs[PROGRAM_STATE_VAR][index].nr != 0);
return c->regs[PROGRAM_STATE_VAR][index];
case PROGRAM_ADDRESS:
assert(index == 0);
return c->regs[file][index];
@ -668,28 +693,28 @@ static void emit_arl( struct brw_vs_compile *c,
* account.
*/
static struct brw_reg get_arg( struct brw_vs_compile *c,
struct prog_src_register src )
struct prog_src_register *src )
{
struct brw_reg reg;
if (src.File == PROGRAM_UNDEFINED)
if (src->File == PROGRAM_UNDEFINED)
return brw_null_reg();
if (src.RelAddr)
reg = deref(c, c->regs[PROGRAM_STATE_VAR][0], src.Index);
if (src->RelAddr)
reg = deref(c, c->regs[PROGRAM_STATE_VAR][0], src->Index);
else
reg = get_reg(c, src.File, src.Index);
reg = get_reg(c, src->File, src->Index);
/* Convert 3-bit swizzle to 2-bit.
*/
reg.dw1.bits.swizzle = BRW_SWIZZLE4(GET_SWZ(src.Swizzle, 0),
GET_SWZ(src.Swizzle, 1),
GET_SWZ(src.Swizzle, 2),
GET_SWZ(src.Swizzle, 3));
reg.dw1.bits.swizzle = BRW_SWIZZLE4(GET_SWZ(src->Swizzle, 0),
GET_SWZ(src->Swizzle, 1),
GET_SWZ(src->Swizzle, 2),
GET_SWZ(src->Swizzle, 3));
/* Note this is ok for non-swizzle instructions:
*/
reg.negate = src.NegateBase ? 1 : 0;
reg.negate = src->NegateBase ? 1 : 0;
return reg;
}
@ -891,17 +916,50 @@ static void emit_vertex_write( struct brw_vs_compile *c)
}
static void
post_vs_emit( struct brw_vs_compile *c, struct brw_instruction *end_inst )
{
GLuint nr_insns = c->vp->program.Base.NumInstructions;
GLuint insn, target_insn;
struct prog_instruction *inst1, *inst2;
struct brw_instruction *brw_inst1, *brw_inst2;
int offset;
for (insn = 0; insn < nr_insns; insn++) {
inst1 = &c->vp->program.Base.Instructions[insn];
brw_inst1 = inst1->Data;
switch (inst1->Opcode) {
case OPCODE_CAL:
case OPCODE_BRA:
target_insn = inst1->BranchTarget;
inst2 = &c->vp->program.Base.Instructions[target_insn];
brw_inst2 = inst2->Data;
offset = brw_inst2 - brw_inst1;
brw_set_src1(brw_inst1, brw_imm_d(offset*16));
break;
case OPCODE_END:
offset = end_inst - brw_inst1;
brw_set_src1(brw_inst1, brw_imm_d(offset*16));
break;
default:
break;
}
}
}
/* Emit the fragment program instructions here.
*/
void brw_vs_emit( struct brw_vs_compile *c )
void brw_vs_emit(struct brw_vs_compile *c )
{
#define MAX_IFSN 32
struct brw_compile *p = &c->func;
GLuint nr_insns = c->vp->program.Base.NumInstructions;
GLuint insn;
GLuint insn, if_insn = 0;
struct brw_instruction *end_inst;
struct brw_instruction *if_inst[MAX_IFSN];
struct brw_indirect stack_index = brw_indirect(0, 0);
GLuint index;
GLuint file;
if (INTEL_DEBUG & DEBUG_VS) {
_mesa_printf("\n\n\nvs-emit:\n");
@ -912,9 +970,24 @@ void brw_vs_emit( struct brw_vs_compile *c )
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_access_mode(p, BRW_ALIGN_16);
/* Message registers can't be read, so copy the output into GRF register
if they are used in source registers */
for (insn = 0; insn < nr_insns; insn++) {
GLuint i;
struct prog_instruction *inst = &c->vp->program.Base.Instructions[insn];
for (i = 0; i < 3; i++) {
struct prog_src_register *src = &inst->SrcReg[i];
GLuint index = src->Index;
GLuint file = src->File;
if (file == PROGRAM_OUTPUT && index != VERT_RESULT_HPOS)
c->output_regs[index].used_in_src = GL_TRUE;
}
}
/* Static register allocation
*/
brw_vs_alloc_regs(c);
brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
for (insn = 0; insn < nr_insns; insn++) {
@ -924,17 +997,29 @@ void brw_vs_emit( struct brw_vs_compile *c )
/* Get argument regs. SWZ is special and does this itself.
*/
inst->Data = &p->store[p->nr_insn];
if (inst->Opcode != OPCODE_SWZ)
for (i = 0; i < 3; i++)
args[i] = get_arg(c, inst->SrcReg[i]);
for (i = 0; i < 3; i++) {
struct prog_src_register *src = &inst->SrcReg[i];
index = src->Index;
file = src->File;
if (file == PROGRAM_OUTPUT&&c->output_regs[index].used_in_src)
args[i] = c->output_regs[index].reg;
else
args[i] = get_arg(c, src);
}
/* Get dest regs. Note that it is possible for a reg to be both
* dst and arg, given the static allocation of registers. So
* care needs to be taken emitting multi-operation instructions.
*/
dst = get_dst(c, inst->DstReg);
*/
index = inst->DstReg.Index;
file = inst->DstReg.File;
if (file == PROGRAM_OUTPUT && c->output_regs[index].used_in_src)
dst = c->output_regs[index].reg;
else
dst = get_dst(c, inst->DstReg);
switch (inst->Opcode) {
case OPCODE_ABS:
brw_MOV(p, dst, brw_abs(args[0]));
@ -1003,12 +1088,25 @@ void brw_vs_emit( struct brw_vs_compile *c )
case OPCODE_RSQ:
emit_math1(c, BRW_MATH_FUNCTION_RSQ, dst, args[0], BRW_MATH_PRECISION_FULL);
break;
case OPCODE_SEQ:
emit_seq(p, dst, args[0], args[1]);
break;
case OPCODE_SNE:
emit_sne(p, dst, args[0], args[1]);
break;
case OPCODE_SGE:
emit_sge(p, dst, args[0], args[1]);
break;
case OPCODE_SGT:
emit_sgt(p, dst, args[0], args[1]);
break;
case OPCODE_SLT:
emit_slt(p, dst, args[0], args[1]);
break;
case OPCODE_SLE:
emit_sle(p, dst, args[0], args[1]);
break;
case OPCODE_SUB:
brw_ADD(p, dst, args[0], negate(args[1]));
break;
@ -1021,21 +1119,60 @@ void brw_vs_emit( struct brw_vs_compile *c )
case OPCODE_XPD:
emit_xpd(p, dst, args[0], args[1]);
break;
case OPCODE_IF:
assert(if_insn < MAX_IFSN);
if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8);
break;
case OPCODE_ELSE:
if_inst[if_insn-1] = brw_ELSE(p, if_inst[if_insn-1]);
break;
case OPCODE_ENDIF:
assert(if_insn > 0);
brw_ENDIF(p, if_inst[--if_insn]);
break;
case OPCODE_BRA:
brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
brw_set_predicate_control_flag_value(p, 0xff);
break;
case OPCODE_CAL:
brw_set_access_mode(p, BRW_ALIGN_1);
brw_ADD(p, deref_1uw(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16));
brw_set_access_mode(p, BRW_ALIGN_16);
brw_ADD(p, get_addr_reg(stack_index),
get_addr_reg(stack_index), brw_imm_d(4));
inst->Data = &p->store[p->nr_insn];
brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
break;
case OPCODE_RET:
brw_ADD(p, get_addr_reg(stack_index),
get_addr_reg(stack_index), brw_imm_d(-4));
brw_set_access_mode(p, BRW_ALIGN_1);
brw_MOV(p, brw_ip_reg(), deref_1uw(stack_index, 0));
brw_set_access_mode(p, BRW_ALIGN_16);
case OPCODE_END:
brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
break;
case OPCODE_PRINT:
case OPCODE_BGNSUB:
case OPCODE_ENDSUB:
break;
default:
_mesa_printf("Unsupport opcode %d in vertex shader\n", inst->Opcode);
break;
}
if (inst->DstReg.File == PROGRAM_OUTPUT
&&inst->DstReg.Index != VERT_RESULT_HPOS
&&c->output_regs[inst->DstReg.Index].used_in_src)
brw_MOV(p, get_dst(c, inst->DstReg), dst);
release_tmps(c);
}
end_inst = &p->store[p->nr_insn];
emit_vertex_write(c);
post_vs_emit(c, end_inst);
for (insn = 0; insn < nr_insns; insn++)
c->vp->program.Base.Instructions[insn].Data = NULL;
}

2
src/mesa/drivers/dri/i965/brw_vs_tnl.c
View File

@ -855,7 +855,7 @@ static struct ureg calculate_light_attenuation( struct tnl_program *p,
struct ureg slt = get_temp(p);
emit_op2(p, OPCODE_DP3, spot, 0, ureg_negate(VPpli), spot_dir_norm);
emit_op2(p, OPCODE_SLT, slt, 0, swizzle1(spot_dir_norm,W), spot);
emit_op2(p, OPCODE_SLT, slt, 0, spot, swizzle1(spot_dir_norm,W));
emit_op2(p, OPCODE_POW, spot, 0, spot, swizzle1(attenuation, W));
emit_op2(p, OPCODE_MUL, att, 0, slt, spot);

84
src/mesa/drivers/dri/i965/brw_wm.c
View File

@ -66,7 +66,11 @@ GLuint brw_wm_nr_args( GLuint opcode )
case OPCODE_POW:
case OPCODE_SUB:
case OPCODE_SGE:
case OPCODE_SGT:
case OPCODE_SLE:
case OPCODE_SLT:
case OPCODE_SEQ:
case OPCODE_SNE:
case OPCODE_ADD:
case OPCODE_MAX:
case OPCODE_MIN:
@ -150,47 +154,49 @@ static void do_wm_prog( struct brw_context *brw,
c->fp = fp;
c->env_param = brw->intel.ctx.FragmentProgram.Parameters;
/* Augment fragment program. Add instructions for pre- and
* post-fragment-program tasks such as interpolation and fogging.
*/
brw_wm_pass_fp(c);
/* Translate to intermediate representation. Build register usage
* chains.
*/
brw_wm_pass0(c);
/* Dead code removal.
*/
brw_wm_pass1(c);
/* Hal optimization
*/
brw_wm_pass_hal (c);
/* Register allocation.
*/
c->grf_limit = BRW_WM_MAX_GRF/2;
/* This is where we start emitting gen4 code:
*/
brw_init_compile(&c->func);
brw_wm_pass2(c);
c->prog_data.total_grf = c->max_wm_grf;
if (c->last_scratch) {
c->prog_data.total_scratch =
c->last_scratch + 0x40;
if (brw_wm_is_glsl(&c->fp->program)) {
brw_wm_glsl_emit(c);
} else {
c->prog_data.total_scratch = 0;
/* Augment fragment program. Add instructions for pre- and
* post-fragment-program tasks such as interpolation and fogging.
*/
brw_wm_pass_fp(c);
/* Translate to intermediate representation. Build register usage
* chains.
*/
brw_wm_pass0(c);
/* Dead code removal.
*/
brw_wm_pass1(c);
/* Hal optimization
*/
brw_wm_pass_hal (c);
/* Register allocation.
*/
c->grf_limit = BRW_WM_MAX_GRF/2;
/* This is where we start emitting gen4 code:
*/
brw_init_compile(&c->func);
brw_wm_pass2(c);
c->prog_data.total_grf = c->max_wm_grf;
if (c->last_scratch) {
c->prog_data.total_scratch =
c->last_scratch + 0x40;
} else {
c->prog_data.total_scratch = 0;
}
/* Emit GEN4 code.
*/
brw_wm_emit(c);
}
/* Emit GEN4 code.
*/
brw_wm_emit(c);
/* get the program
*/
program = brw_get_program(&c->func, &program_size);

12
src/mesa/drivers/dri/i965/brw_wm.h
View File

@ -194,6 +194,7 @@ struct brw_wm_compile {
GLuint nr_fp_insns;
GLuint fp_temp;
GLuint fp_interp_emitted;
GLuint fp_deriv_emitted;
struct prog_src_register pixel_xy;
struct prog_src_register delta_xy;
@ -231,6 +232,15 @@ struct brw_wm_compile {
GLuint grf_limit;
GLuint max_wm_grf;
GLuint last_scratch;
struct {
GLboolean inited;
struct brw_reg reg;
} wm_regs[PROGRAM_PAYLOAD+1][256][4];
struct brw_reg stack;
struct brw_reg emit_mask_reg;
GLuint reg_index;
GLuint tmp_index;
};
@ -259,4 +269,6 @@ void brw_wm_lookup_iz( GLuint line_aa,
GLuint lookup,
struct brw_wm_prog_key *key );
GLboolean brw_wm_is_glsl(struct gl_fragment_program *fp);
void brw_wm_glsl_emit(struct brw_wm_compile *c);
#endif

120
src/mesa/drivers/dri/i965/brw_wm_emit.c
View File

@ -229,20 +229,20 @@ static void emit_cinterp( struct brw_compile *p,
GLuint mask,
const struct brw_reg *arg0 )
{
struct brw_reg interp[4];
GLuint nr = arg0[0].nr;
GLuint i;
struct brw_reg interp[4];
GLuint nr = arg0[0].nr;
GLuint i;
interp[0] = brw_vec1_grf(nr, 0);
interp[1] = brw_vec1_grf(nr, 4);
interp[2] = brw_vec1_grf(nr+1, 0);
interp[3] = brw_vec1_grf(nr+1, 4);
interp[0] = brw_vec1_grf(nr, 0);
interp[1] = brw_vec1_grf(nr, 4);
interp[2] = brw_vec1_grf(nr+1, 0);
interp[3] = brw_vec1_grf(nr+1, 4);
for(i = 0; i < 4; i++ ) {
if (mask & (1<<i)) {
brw_MOV(p, dst[i], suboffset(interp[i],3)); /* TODO: optimize away like other moves */
}
}
for(i = 0; i < 4; i++ ) {
if (mask & (1<<i)) {
brw_MOV(p, dst[i], suboffset(interp[i],3)); /* TODO: optimize away like other moves */
}
}
}
@ -343,7 +343,24 @@ static void emit_lrp( struct brw_compile *p,
}
}
}
static void emit_sop( struct brw_compile *p,
const struct brw_reg *dst,
GLuint mask,
GLuint cond,
const struct brw_reg *arg0,
const struct brw_reg *arg1 )
{
GLuint i;
for (i = 0; i < 4; i++) {
if (mask & (1<<i)) {
brw_MOV(p, dst[i], brw_imm_f(0));
brw_CMP(p, brw_null_reg(), cond, arg0[i], arg1[i]);
brw_MOV(p, dst[i], brw_imm_f(1.0));
brw_set_predicate_control_flag_value(p, 0xff);
}
}
}
static void emit_slt( struct brw_compile *p,
const struct brw_reg *dst,
@ -351,39 +368,53 @@ static void emit_slt( struct brw_compile *p,
const struct brw_reg *arg0,
const struct brw_reg *arg1 )
{
GLuint i;
for (i = 0; i < 4; i++) {
if (mask & (1<<i)) {
brw_MOV(p, dst[i], brw_imm_f(0));
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0[i], arg1[i]);
brw_MOV(p, dst[i], brw_imm_f(1.0));
brw_set_predicate_control_flag_value(p, 0xff);
}
}
emit_sop(p, dst, mask, BRW_CONDITIONAL_L, arg0, arg1);
}
static void emit_sle( struct brw_compile *p,
const struct brw_reg *dst,
GLuint mask,
const struct brw_reg *arg0,
const struct brw_reg *arg1 )
{
emit_sop(p, dst, mask, BRW_CONDITIONAL_LE, arg0, arg1);
}
static void emit_sgt( struct brw_compile *p,
const struct brw_reg *dst,
GLuint mask,
const struct brw_reg *arg0,
const struct brw_reg *arg1 )
{
emit_sop(p, dst, mask, BRW_CONDITIONAL_G, arg0, arg1);
}
/* Isn't this just the same as the above with the args swapped?
*/
static void emit_sge( struct brw_compile *p,
const struct brw_reg *dst,
GLuint mask,
const struct brw_reg *arg0,
const struct brw_reg *arg1 )
{
GLuint i;
for (i = 0; i < 4; i++) {
if (mask & (1<<i)) {
brw_MOV(p, dst[i], brw_imm_f(0));
brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0[i], arg1[i]);
brw_MOV(p, dst[i], brw_imm_f(1.0));
brw_set_predicate_control_flag_value(p, 0xff);
}
}
emit_sop(p, dst, mask, BRW_CONDITIONAL_GE, arg0, arg1);
}
static void emit_seq( struct brw_compile *p,
const struct brw_reg *dst,
GLuint mask,
const struct brw_reg *arg0,
const struct brw_reg *arg1 )
{
emit_sop(p, dst, mask, BRW_CONDITIONAL_EQ, arg0, arg1);
}
static void emit_sne( struct brw_compile *p,
const struct brw_reg *dst,
GLuint mask,
const struct brw_reg *arg0,
const struct brw_reg *arg1 )
{
emit_sop(p, dst, mask, BRW_CONDITIONAL_NEQ, arg0, arg1);
}
static void emit_cmp( struct brw_compile *p,
const struct brw_reg *dst,
@ -543,8 +574,8 @@ static void emit_math1( struct brw_compile *p,
GLuint mask,
const struct brw_reg *arg0 )
{
assert((mask & WRITEMASK_XYZW) == WRITEMASK_X ||
function == BRW_MATH_FUNCTION_SINCOS);
//assert((mask & WRITEMASK_XYZW) == WRITEMASK_X ||
// function == BRW_MATH_FUNCTION_SINCOS);
brw_MOV(p, brw_message_reg(2), arg0[0]);
@ -671,6 +702,8 @@ static void emit_tex( struct brw_wm_compile *c,
msgLength,
0);
if (shadow)
brw_MOV(p, dst[3], brw_imm_f(1.0));
}
@ -1208,9 +1241,21 @@ void brw_wm_emit( struct brw_wm_compile *c )
emit_slt(p, dst, dst_flags, args[0], args[1]);
break;
case OPCODE_SLE:
emit_sle(p, dst, dst_flags, args[0], args[1]);
break;
case OPCODE_SGT:
emit_sgt(p, dst, dst_flags, args[0], args[1]);
break;
case OPCODE_SGE:
emit_sge(p, dst, dst_flags, args[0], args[1]);
break;
case OPCODE_SEQ:
emit_seq(p, dst, dst_flags, args[0], args[1]);
break;
case OPCODE_SNE:
emit_sne(p, dst, dst_flags, args[0], args[1]);
break;
case OPCODE_LIT:
emit_lit(p, dst, dst_flags, args[0]);
@ -1231,7 +1276,8 @@ void brw_wm_emit( struct brw_wm_compile *c )
break;
default:
assert(0);
_mesa_printf("unsupport opcode %d in fragment program\n",
inst->opcode);
}
for (i = 0; i < 4; i++)

53
src/mesa/drivers/dri/i965/brw_wm_fp.c
View File

@ -176,6 +176,7 @@ static struct prog_instruction *emit_insn(struct brw_wm_compile *c,
{
struct prog_instruction *inst = get_fp_inst(c);
*inst = *inst0;
inst->Data = (void *)inst0;
return inst;
}
@ -201,7 +202,6 @@ static struct prog_instruction * emit_op(struct brw_wm_compile *c,
inst->SrcReg[0] = src0;
inst->SrcReg[1] = src1;
inst->SrcReg[2] = src2;
return inst;
}
@ -361,6 +361,37 @@ static void emit_interp( struct brw_wm_compile *c,
c->fp_interp_emitted |= 1<<idx;
}
static void emit_ddx( struct brw_wm_compile *c,
const struct prog_instruction *inst )
{
GLuint idx = inst->SrcReg[0].Index;
struct prog_src_register interp = src_reg(PROGRAM_PAYLOAD, idx);
c->fp_deriv_emitted |= 1<<idx;
emit_op(c,
OPCODE_DDX,
inst->DstReg,
0, 0, 0,
interp,
get_pixel_w(c),
src_undef());
}
static void emit_ddy( struct brw_wm_compile *c,
const struct prog_instruction *inst )
{
GLuint idx = inst->SrcReg[0].Index;
struct prog_src_register interp = src_reg(PROGRAM_PAYLOAD, idx);
c->fp_deriv_emitted |= 1<<idx;
emit_op(c,
OPCODE_DDY,
inst->DstReg,
0, 0, 0,
interp,
get_pixel_w(c),
src_undef());
}
/***********************************************************************
* Hacks to extend the program parameter and constant lists.
@ -957,8 +988,16 @@ void brw_wm_pass_fp( struct brw_wm_compile *c )
*/
out->DstReg.WriteMask = 0;
break;
case OPCODE_DDX:
emit_ddx(c, inst);
break;
case OPCODE_DDY:
emit_ddy(c, inst);
break;
case OPCODE_END:
emit_fog(c);
emit_fb_write(c);
break;
case OPCODE_PRINT:
break;
@ -967,15 +1006,11 @@ void brw_wm_pass_fp( struct brw_wm_compile *c )
break;
}
}
emit_fog(c);
emit_fb_write(c);
if (INTEL_DEBUG & DEBUG_WM) {
_mesa_printf("\n\n\npass_fp:\n");
print_insns( c->prog_instructions, c->nr_fp_insns );
_mesa_printf("\n");
_mesa_printf("\n\n\npass_fp:\n");
print_insns( c->prog_instructions, c->nr_fp_insns );
_mesa_printf("\n");
}
}

1354
src/mesa/drivers/dri/i965/brw_wm_glsl.c Normal file
View File

File diff suppressed because it is too large Load Diff

4
src/mesa/drivers/dri/i965/brw_wm_pass0.c
View File

@ -168,6 +168,7 @@ static const struct brw_wm_ref *pass0_get_reg( struct brw_wm_compile *c,
case PROGRAM_PAYLOAD:
case PROGRAM_TEMPORARY:
case PROGRAM_OUTPUT:
case PROGRAM_VARYING:
break;
case PROGRAM_LOCAL_PARAM:
@ -179,6 +180,8 @@ static const struct brw_wm_ref *pass0_get_reg( struct brw_wm_compile *c,
break;
case PROGRAM_STATE_VAR:
case PROGRAM_UNIFORM:
case PROGRAM_CONSTANT:
case PROGRAM_NAMED_PARAM: {
struct gl_program_parameter_list *plist = c->fp->program.Base.Parameters;
@ -197,6 +200,7 @@ static const struct brw_wm_ref *pass0_get_reg( struct brw_wm_compile *c,
break;
case PROGRAM_STATE_VAR:
case PROGRAM_UNIFORM:
/* These may change from run to run:
*/
ref = get_param_ref(c, &plist->ParameterValues[idx][component] );

5
src/mesa/drivers/dri/i965/brw_wm_pass1.c
View File

@ -155,7 +155,11 @@ void brw_wm_pass1( struct brw_wm_compile *c )
case OPCODE_SUB:
case OPCODE_SLT:
case OPCODE_SLE:
case OPCODE_SGE:
case OPCODE_SGT:
case OPCODE_SEQ:
case OPCODE_SNE:
case OPCODE_ADD:
case OPCODE_MAX:
case OPCODE_MIN:
@ -257,7 +261,6 @@ void brw_wm_pass1( struct brw_wm_compile *c )
case OPCODE_DST:
case OPCODE_TXP:
default:
assert(0);
break;
}

2
src/mesa/drivers/dri/i965/brw_wm_pass2.c
View File

@ -328,7 +328,7 @@ void brw_wm_pass2( struct brw_wm_compile *c )
c->state = PASS2_DONE;
if (INTEL_DEBUG & DEBUG_WM) {
brw_wm_print_program(c, "pass2/done");
brw_wm_print_program(c, "pass2/done");
}
}

7
src/mesa/drivers/dri/i965/brw_wm_state.c
View File

@ -34,6 +34,7 @@
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
#include "brw_wm.h"
#include "bufmgr.h"
/***********************************************************************
@ -134,9 +135,13 @@ static void upload_wm_unit(struct brw_context *brw )
if (fp->UsesKill ||
brw->attribs.Color->AlphaEnabled)
wm.wm5.program_uses_killpixel = 1;
if (brw_wm_is_glsl(fp))
wm.wm5.enable_8_pix = 1;
else
wm.wm5.enable_16_pix = 1;
}
wm.wm5.enable_16_pix = 1;
wm.wm5.thread_dispatch_enable = 1; /* AKA: color_write */
wm.wm5.legacy_line_rast = 0;
wm.wm5.legacy_global_depth_bias = 0;

14
src/mesa/drivers/dri/i965/intel_context.c
View File

@ -84,6 +84,11 @@ int INTEL_DEBUG = (0);
#define need_GL_EXT_multi_draw_arrays
#define need_GL_EXT_secondary_color
#define need_GL_EXT_point_parameters
#define need_GL_VERSION_2_0
#define need_GL_VERSION_2_1
#define need_GL_ARB_shader_objects
#define need_GL_ARB_vertex_shader
#include "extension_helper.h"
#ifndef VERBOSE
@ -190,6 +195,13 @@ const struct dri_extension card_extensions[] =
{ "GL_MESA_ycbcr_texture", NULL },
{ "GL_NV_blend_square", NULL },
{ "GL_SGIS_generate_mipmap", NULL },
{ "GL_ARB_shading_language_100", GL_VERSION_2_0_functions},
{ "GL_ARB_shading_language_120", GL_VERSION_2_1_functions},
{ "GL_ARB_shader_objects", GL_ARB_shader_objects_functions},
{ "GL_ARB_vertex_shader", GL_ARB_vertex_shader_functions},
{ "GL_ARB_fragment_shader", NULL },
/* XXX not implement yet, to compile builtin glsl lib */
{ "GL_ARB_draw_buffers", NULL },
{ NULL, NULL }
};
@ -559,6 +571,8 @@ void intelDestroyContext(__DRIcontextPrivate *driContextPriv)
#endif
/* free the Mesa context */
intel->ctx.VertexProgram.Current = NULL;
intel->ctx.FragmentProgram.Current = NULL;
_mesa_destroy_context(&intel->ctx);
}

2
src/mesa/main/texenvprogram.c
View File

@ -1242,7 +1242,7 @@ _mesa_UpdateTexEnvProgram( GLcontext *ctx )
/* If a conventional fragment program/shader isn't in effect... */
if (!ctx->FragmentProgram._Enabled &&
!ctx->Shader.CurrentProgram) {
(!ctx->Shader.CurrentProgram || !ctx->Shader.CurrentProgram->FragmentProgram)) {
make_state_key(ctx, &key);
hash = hash_key(&key);

2
src/mesa/shader/program.c
View File

@ -285,6 +285,8 @@ _mesa_init_vertex_program( GLcontext *ctx, struct gl_vertex_program *prog,
struct gl_program *
_mesa_new_program(GLcontext *ctx, GLenum target, GLuint id)
{
if (ctx->Driver.NewProgram)
return ctx->Driver.NewProgram(ctx, target, id);
switch (target) {
case GL_VERTEX_PROGRAM_ARB: /* == GL_VERTEX_PROGRAM_NV */
return _mesa_init_vertex_program(ctx, CALLOC_STRUCT(gl_vertex_program),

1
src/mesa/shader/slang/slang_codegen.c
View File

@ -1847,6 +1847,7 @@ _slang_gen_var_decl(slang_assemble_ctx *A, slang_variable *var)
n->Store->File = PROGRAM_TEMPORARY;
n->Store->Size = _slang_sizeof_type_specifier(&n->Var->type.specifier);
A->program->NumTemporaries++;
assert(n->Store->Size > 0);
}
return n;