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ac: set the TCC line size for Aldebaran 

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9389>
This commit is contained in:
Marek Olšák 2021-03-02 23:37:55 -05:00 committed by Marge Bot
parent 230a6dc55d
commit 6edf1978d3
1 changed files with 6 additions and 2 deletions
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8
src/amd/common/ac_gpu_info.c
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@ -642,6 +642,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->mid_command_buffer_preemption_enabled = amdinfo->ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION;
info->has_tmz_support = has_tmz_support(dev, info, amdinfo);
info->kernel_has_modifiers = info->chip_class >= GFX9 && info->drm_minor >= 40;
info->has_graphics = gfx.available_rings > 0;
info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
info->max_render_backends = amdinfo->rb_pipes;
@ -673,7 +674,11 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->tcc_harvested = (info->vram_size / info->max_tcc_blocks) != 512 * 1024 * 1024;
}
} else {
info->tcc_cache_line_size = 64;
if (!info->has_graphics && info->family >= CHIP_ALDEBARAN)
info->tcc_cache_line_size = 128;
else
info->tcc_cache_line_size = 64;
info->num_tcc_blocks = info->max_tcc_blocks;
}
@ -732,7 +737,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
info->has_graphics = gfx.available_rings > 0;
info->num_rings[RING_GFX] = util_bitcount(gfx.available_rings);
info->num_rings[RING_COMPUTE] = util_bitcount(compute.available_rings);
info->num_rings[RING_DMA] = util_bitcount(dma.available_rings);