radeonsi/gfx10: fix intensity formats
move the ALPHA_IS_ON_MSB fixup into vi_alpha_is_on_msb Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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6944f99176
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6eb219e963
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@ -99,18 +99,23 @@ enum pipe_format si_simplify_cb_format(enum pipe_format format)
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return util_format_intensity_to_red(format);
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}
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bool vi_alpha_is_on_msb(enum pipe_format format)
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bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format)
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{
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format = si_simplify_cb_format(format);
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const struct util_format_description *desc = util_format_description(format);
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/* Formats with 3 channels can't have alpha. */
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if (util_format_description(format)->nr_channels == 3)
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if (desc->nr_channels == 3)
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return true; /* same as xxxA; is any value OK here? */
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if (sscreen->info.chip_class >= GFX10 && desc->nr_channels == 1)
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return desc->swizzle[3] == PIPE_SWIZZLE_X;
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return si_translate_colorswap(format, false) <= 1;
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}
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static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
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static bool vi_get_fast_clear_parameters(struct si_screen *sscreen,
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enum pipe_format base_format,
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enum pipe_format surface_format,
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const union pipe_color_union *color,
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uint32_t* clear_value,
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@ -142,8 +147,8 @@ static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
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if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
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return true; /* need ELIMINATE_FAST_CLEAR */
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bool base_alpha_is_on_msb = vi_alpha_is_on_msb(base_format);
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bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(surface_format);
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bool base_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, base_format);
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bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, surface_format);
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/* Formats with 3 channels can't have alpha. */
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if (desc->nr_channels == 3)
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@ -483,7 +488,8 @@ static void si_do_fast_color_clear(struct si_context *sctx,
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!tex->surface.u.legacy.level[level].dcc_fast_clear_size)
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continue;
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if (!vi_get_fast_clear_parameters(tex->buffer.b.b.format,
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if (!vi_get_fast_clear_parameters(sctx->screen,
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tex->buffer.b.b.format,
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fb->cbufs[i]->format,
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color, &reset_value,
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&eliminate_needed))
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@ -739,7 +739,7 @@ static void si_set_shader_image_desc(struct si_context *ctx,
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if (uses_dcc && !skip_decompress &&
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(view->access & PIPE_IMAGE_ACCESS_WRITE ||
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!vi_dcc_formats_compatible(res->b.b.format, view->format))) {
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!vi_dcc_formats_compatible(screen, res->b.b.format, view->format))) {
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/* If DCC can't be disabled, at least decompress it.
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* The decompression is relatively cheap if the surface
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* has been decompressed already.
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@ -1265,7 +1265,7 @@ void si_init_buffer_functions(struct si_context *sctx);
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/* si_clear.c */
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enum pipe_format si_simplify_cb_format(enum pipe_format format);
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bool vi_alpha_is_on_msb(enum pipe_format format);
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bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
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void vi_dcc_clear_level(struct si_context *sctx,
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struct si_texture *tex,
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unsigned level, unsigned clear_value);
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@ -1486,7 +1486,8 @@ void si_print_texture_info(struct si_screen *sscreen,
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struct si_texture *tex, struct u_log_context *log);
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struct pipe_resource *si_texture_create(struct pipe_screen *screen,
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const struct pipe_resource *templ);
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bool vi_dcc_formats_compatible(enum pipe_format format1,
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bool vi_dcc_formats_compatible(struct si_screen *sscreen,
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enum pipe_format format1,
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enum pipe_format format2);
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bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
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unsigned level,
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@ -3979,7 +3979,7 @@ gfx10_make_texture_descriptor(struct si_screen *screen,
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if (tex->dcc_offset) {
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state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
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S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
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S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
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S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
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}
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/* Initialize the sampler view for FMASK. */
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@ -4260,7 +4260,7 @@ si_make_texture_descriptor(struct si_screen *screen,
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}
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if (tex->dcc_offset) {
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state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
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state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
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} else {
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/* The last dword is unused by hw. The shader uses it to clear
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* bits in the first dword of sampler state.
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@ -2056,7 +2056,8 @@ static const struct u_resource_vtbl si_texture_vtbl =
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/* Return if it's allowed to reinterpret one format as another with DCC enabled.
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*/
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bool vi_dcc_formats_compatible(enum pipe_format format1,
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bool vi_dcc_formats_compatible(struct si_screen *sscreen,
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enum pipe_format format1,
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enum pipe_format format2)
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{
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const struct util_format_description *desc1, *desc2;
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@ -2098,7 +2099,7 @@ bool vi_dcc_formats_compatible(enum pipe_format format1,
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/* If the clear values are all 1 or all 0, this constraint can be
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* ignored. */
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if (vi_alpha_is_on_msb(format1) != vi_alpha_is_on_msb(format2))
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if (vi_alpha_is_on_msb(sscreen, format1) != vi_alpha_is_on_msb(sscreen, format2))
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return false;
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/* Channel types must match if the clear value of 1 is used.
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@ -2120,7 +2121,8 @@ bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
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struct si_texture *stex = (struct si_texture *)tex;
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return vi_dcc_enabled(stex, level) &&
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!vi_dcc_formats_compatible(tex->format, view_format);
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!vi_dcc_formats_compatible((struct si_screen*)tex->screen,
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tex->format, view_format);
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}
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/* This can't be merged with the above function, because
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