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radeonsi: merge radeon_llvm_context and si_shader_context 

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
This commit is contained in:
Marek Olšák 2016-10-17 12:42:12 +02:00
parent 5ab25bb4ba
commit 6e475fefa1
4 changed files with 289 additions and 316 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

464
src/gallium/drivers/radeonsi/si_shader.c
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File diff suppressed because it is too large Load Diff

87
src/gallium/drivers/radeonsi/si_shader_internal.h
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@ -45,26 +45,32 @@ struct radeon_shader_binary;
struct radeon_llvm_flow;
struct radeon_llvm_context {
struct si_shader_context {
struct lp_build_tgsi_soa_context soa;
struct gallivm_state gallivm;
struct si_shader *shader;
struct si_screen *screen;
/*=== Front end configuration ===*/
/* Instructions that are not described by any of the TGSI opcodes. */
unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
bool is_gs_copy_shader;
/* Whether to generate the optimized shader variant compiled as a whole
* (without a prolog and epilog)
*/
bool is_monolithic;
/** This function is responsible for initilizing the inputs array and will be
* called once for each input declared in the TGSI shader.
*/
void (*load_input)(struct radeon_llvm_context *,
void (*load_input)(struct si_shader_context *,
unsigned input_index,
const struct tgsi_full_declaration *decl,
LLVMValueRef out[4]);
void (*load_system_value)(struct radeon_llvm_context *,
void (*load_system_value)(struct si_shader_context *,
unsigned index,
const struct tgsi_full_declaration *decl);
void (*declare_memory_region)(struct radeon_llvm_context *,
void (*declare_memory_region)(struct si_shader_context *,
const struct tgsi_full_declaration *decl);
/** This array contains the input values for the shader. Typically these
@ -83,8 +89,6 @@ struct radeon_llvm_context {
unsigned temps_count;
LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
/*=== Private Members ===*/
struct radeon_llvm_flow *flow;
unsigned flow_depth;
unsigned flow_depth_max;
@ -97,16 +101,63 @@ struct radeon_llvm_context {
LLVMValueRef main_fn;
LLVMTypeRef return_type;
int param_streamout_config;
int param_streamout_write_index;
int param_streamout_offset[4];
int param_vertex_id;
int param_rel_auto_id;
int param_vs_prim_id;
int param_instance_id;
int param_vertex_index0;
int param_tes_u;
int param_tes_v;
int param_tes_rel_patch_id;
int param_tes_patch_id;
int param_es2gs_offset;
int param_oc_lds;
/* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
* 0x800000 for VS, 0x1 for ES.
*/
int param_tess_offchip;
LLVMTargetMachineRef tm;
unsigned invariant_load_md_kind;
unsigned range_md_kind;
unsigned uniform_md_kind;
unsigned fpmath_md_kind;
LLVMValueRef fpmath_md_2p5_ulp;
LLVMValueRef empty_md;
struct gallivm_state gallivm;
/* Preloaded descriptors. */
LLVMValueRef esgs_ring;
LLVMValueRef gsvs_ring[4];
LLVMValueRef lds;
LLVMValueRef gs_next_vertex[4];
LLVMValueRef return_value;
LLVMTypeRef voidt;
LLVMTypeRef i1;
LLVMTypeRef i8;
LLVMTypeRef i32;
LLVMTypeRef i64;
LLVMTypeRef i128;
LLVMTypeRef f32;
LLVMTypeRef v16i8;
LLVMTypeRef v2i32;
LLVMTypeRef v4i32;
LLVMTypeRef v4f32;
LLVMTypeRef v8i32;
LLVMValueRef shared_memory;
};
static inline struct radeon_llvm_context *
radeon_llvm_context(struct lp_build_tgsi_context *bld_base)
static inline struct si_shader_context *
si_shader_context(struct lp_build_tgsi_context *bld_base)
{
return (struct radeon_llvm_context*)bld_base;
return (struct si_shader_context*)bld_base;
}
void radeon_llvm_add_attribute(LLVMValueRef F, const char *name, int value);
@ -124,22 +175,22 @@ LLVMTypeRef tgsi2llvmtype(struct lp_build_tgsi_context *bld_base,
LLVMValueRef bitcast(struct lp_build_tgsi_context *bld_base,
enum tgsi_opcode_type type, LLVMValueRef value);
LLVMValueRef radeon_llvm_bound_index(struct radeon_llvm_context *ctx,
LLVMValueRef radeon_llvm_bound_index(struct si_shader_context *ctx,
LLVMValueRef index,
unsigned num);
void radeon_llvm_context_init(struct radeon_llvm_context *ctx,
void radeon_llvm_context_init(struct si_shader_context *ctx,
const char *triple,
const struct tgsi_shader_info *info,
const struct tgsi_token *tokens);
void radeon_llvm_create_func(struct radeon_llvm_context *ctx,
void radeon_llvm_create_func(struct si_shader_context *ctx,
LLVMTypeRef *return_types, unsigned num_return_elems,
LLVMTypeRef *ParamTypes, unsigned ParamCount);
void radeon_llvm_dispose(struct radeon_llvm_context *ctx);
void radeon_llvm_dispose(struct si_shader_context *ctx);
void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx,
void radeon_llvm_finalize_module(struct si_shader_context *ctx,
bool run_verifier);
LLVMValueRef radeon_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base,

2
src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
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@ -695,7 +695,7 @@ static void emit_fdiv(const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
emit_data->output[emit_data->chan] =
LLVMBuildFDiv(bld_base->base.gallivm->builder,

52
src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
View File

@ -285,7 +285,7 @@ LLVMValueRef bitcast(struct lp_build_tgsi_context *bld_base,
* Return a value that is equal to the given i32 \p index if it lies in [0,num)
* or an undefined value in the same interval otherwise.
*/
LLVMValueRef radeon_llvm_bound_index(struct radeon_llvm_context *ctx,
LLVMValueRef radeon_llvm_bound_index(struct si_shader_context *ctx,
LLVMValueRef index,
unsigned num)
{
@ -311,7 +311,7 @@ LLVMValueRef radeon_llvm_bound_index(struct radeon_llvm_context *ctx,
}
static struct radeon_llvm_flow *
get_current_flow(struct radeon_llvm_context *ctx)
get_current_flow(struct si_shader_context *ctx)
{
if (ctx->flow_depth > 0)
return &ctx->flow[ctx->flow_depth - 1];
@ -319,7 +319,7 @@ get_current_flow(struct radeon_llvm_context *ctx)
}
static struct radeon_llvm_flow *
get_innermost_loop(struct radeon_llvm_context *ctx)
get_innermost_loop(struct si_shader_context *ctx)
{
for (unsigned i = ctx->flow_depth; i > 0; --i) {
if (ctx->flow[i - 1].loop_entry_block)
@ -329,7 +329,7 @@ get_innermost_loop(struct radeon_llvm_context *ctx)
}
static struct radeon_llvm_flow *
push_flow(struct radeon_llvm_context *ctx)
push_flow(struct si_shader_context *ctx)
{
struct radeon_llvm_flow *flow;
@ -380,7 +380,7 @@ get_temp_array_id(struct lp_build_tgsi_context *bld_base,
unsigned reg_index,
const struct tgsi_ind_register *reg)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
unsigned num_arrays = ctx->soa.bld_base.info->array_max[TGSI_FILE_TEMPORARY];
unsigned i;
@ -402,7 +402,7 @@ get_array_range(struct lp_build_tgsi_context *bld_base,
unsigned File, unsigned reg_index,
const struct tgsi_ind_register *reg)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
struct tgsi_declaration_range range;
if (File == TGSI_FILE_TEMPORARY) {
@ -438,7 +438,7 @@ emit_array_index(struct lp_build_tgsi_soa_context *bld,
* must be used.
*/
static LLVMValueRef
get_pointer_into_array(struct radeon_llvm_context *ctx,
get_pointer_into_array(struct si_shader_context *ctx,
unsigned file,
unsigned swizzle,
unsigned reg_index,
@ -556,7 +556,7 @@ load_value_from_array(struct lp_build_tgsi_context *bld_base,
unsigned reg_index,
const struct tgsi_ind_register *reg_indirect)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
@ -592,7 +592,7 @@ store_value_to_array(struct lp_build_tgsi_context *bld_base,
unsigned reg_index,
const struct tgsi_ind_register *reg_indirect)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
@ -639,7 +639,7 @@ LLVMValueRef radeon_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base,
enum tgsi_opcode_type type,
unsigned swizzle)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
LLVMBuilderRef builder = bld_base->base.gallivm->builder;
LLVMValueRef result = NULL, ptr, ptr2;
@ -737,7 +737,7 @@ static LLVMValueRef fetch_system_value(struct lp_build_tgsi_context *bld_base,
enum tgsi_opcode_type type,
unsigned swizzle)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMValueRef cval = ctx->system_values[reg->Register.Index];
@ -751,7 +751,7 @@ static LLVMValueRef fetch_system_value(struct lp_build_tgsi_context *bld_base,
static void emit_declaration(struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_declaration *decl)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
LLVMBuilderRef builder = bld_base->base.gallivm->builder;
unsigned first, last, i;
switch(decl->Declaration.File) {
@ -944,7 +944,7 @@ void radeon_llvm_emit_store(struct lp_build_tgsi_context *bld_base,
const struct tgsi_opcode_info *info,
LLVMValueRef dst[4])
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
const struct tgsi_full_dst_register *reg = &inst->Dst[0];
@ -1045,7 +1045,7 @@ static void set_basicblock_name(LLVMBasicBlockRef bb, const char *base, int pc)
/* Append a basic block at the level of the parent flow.
*/
static LLVMBasicBlockRef append_basic_block(struct radeon_llvm_context *ctx,
static LLVMBasicBlockRef append_basic_block(struct si_shader_context *ctx,
const char *name)
{
struct gallivm_state *gallivm = &ctx->gallivm;
@ -1076,7 +1076,7 @@ static void bgnloop_emit(const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
struct radeon_llvm_flow *flow = push_flow(ctx);
flow->loop_entry_block = append_basic_block(ctx, "LOOP");
@ -1090,7 +1090,7 @@ static void brk_emit(const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
struct radeon_llvm_flow *flow = get_innermost_loop(ctx);
@ -1101,7 +1101,7 @@ static void cont_emit(const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
struct radeon_llvm_flow *flow = get_innermost_loop(ctx);
@ -1112,7 +1112,7 @@ static void else_emit(const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
struct radeon_llvm_flow *current_branch = get_current_flow(ctx);
LLVMBasicBlockRef endif_block;
@ -1132,7 +1132,7 @@ static void endif_emit(const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
struct radeon_llvm_flow *current_branch = get_current_flow(ctx);
@ -1149,7 +1149,7 @@ static void endloop_emit(const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
struct radeon_llvm_flow *current_loop = get_current_flow(ctx);
@ -1167,7 +1167,7 @@ static void if_cond_emit(const struct lp_build_tgsi_action *action,
struct lp_build_emit_data *emit_data,
LLVMValueRef cond)
{
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
struct radeon_llvm_flow *flow = push_flow(ctx);
LLVMBasicBlockRef if_block;
@ -1211,7 +1211,7 @@ static void emit_immediate(struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_immediate *imm)
{
unsigned i;
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
struct si_shader_context *ctx = si_shader_context(bld_base);
for (i = 0; i < 4; ++i) {
ctx->soa.immediates[ctx->soa.num_immediates][i] =
@ -1221,7 +1221,7 @@ static void emit_immediate(struct lp_build_tgsi_context *bld_base,
ctx->soa.num_immediates++;
}
void radeon_llvm_context_init(struct radeon_llvm_context *ctx, const char *triple,
void radeon_llvm_context_init(struct si_shader_context *ctx, const char *triple,
const struct tgsi_shader_info *info,
const struct tgsi_token *tokens)
{
@ -1302,7 +1302,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context *ctx, const char *tripl
bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
}
void radeon_llvm_create_func(struct radeon_llvm_context *ctx,
void radeon_llvm_create_func(struct si_shader_context *ctx,
LLVMTypeRef *return_types, unsigned num_return_elems,
LLVMTypeRef *ParamTypes, unsigned ParamCount)
{
@ -1325,7 +1325,7 @@ void radeon_llvm_create_func(struct radeon_llvm_context *ctx,
LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body);
}
void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx,
void radeon_llvm_finalize_module(struct si_shader_context *ctx,
bool run_verifier)
{
struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
@ -1362,7 +1362,7 @@ void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx,
gallivm_dispose_target_library_info(target_library_info);
}
void radeon_llvm_dispose(struct radeon_llvm_context *ctx)
void radeon_llvm_dispose(struct si_shader_context *ctx)
{
LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module);
LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context);