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i965: Emit MI_FLUSH before PSP on Ironlake for clip max threads errata.

This commit is contained in:
Eric Anholt 2010-05-23 20:25:02 -07:00
parent 80689ae615
commit 6e2330daa6
1 changed files with 7 additions and 0 deletions
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7
src/mesa/drivers/dri/i965/brw_misc_state.c
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@ -182,6 +182,13 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
{
struct intel_context *intel = &brw->intel;
if (intel->gen == 5) {
/* Need to flush before changing clip max threads for errata. */
BEGIN_BATCH(1);
OUT_BATCH(MI_FLUSH);
ADVANCE_BATCH();
}
BEGIN_BATCH(7);
OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);