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freedreno/hw/isa: Add description of ir3 ISA 

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
This commit is contained in:
Rob Clark 2020-12-13 16:20:40 -08:00 committed by Marge Bot
parent e7630ec278
commit 6d94f575d2
12 changed files with 3414 additions and 0 deletions
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src/freedreno/isa/ir3-cat0.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright © 2020 Google, Inc.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
-->
<isa>
<!--
Cat0 Instructions:
-->
<bitset name="#instruction-cat0" extends="#instruction">
<!--
TODO immed size is 16b for a3xx, 20b for a4xx, 32b for a5xx+.. should we
try to express this? Also, not all cat0 take an immed, so maybe push
this further down the hierarchy?
-->
<field name="IMMED" low="0" high="31" type="branch"/>
<field name="REPEAT" low="40" high="42" type="#rptN"/>
<pattern pos="43">x</pattern>
<field name="SS" pos="44" type="bool" display="(ss)"/>
<field name="EQ" pos="48" type="bool" display="(eq)"/>
<field name="JP" pos="59" type="bool" display="(jp)"/>
<field name="SY" pos="60" type="bool" display="(sy)"/>
<pattern low="61" high="63">000</pattern> <!-- cat0 -->
<encode>
<map name="IMMED">src->cat0.immed</map>
<map name="COMP1">src->cat0.comp1</map>
<map name="COMP2">src->cat0.comp2</map>
<map name="INV1">src->cat0.inv1</map>
<map name="INV2">src->cat0.inv2</map>
</encode>
</bitset>
<bitset name="#instruction-cat0-0src" extends="#instruction-cat0">
<display>
{SY}{SS}{EQ}{JP}{REPEAT}{NAME}
</display>
<pattern low="32" high="36">00000</pattern>
<pattern low="37" high="39">000</pattern> <!-- BRTYPE -->
<pattern low="45" high="47">000</pattern> <!-- src1 -->
<pattern low="52" high="54">000</pattern> <!-- src0 -->
</bitset>
<bitset name="nop" extends="#instruction-cat0-0src">
<pattern low="49" high="51">xx0</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">0000</pattern> <!-- OPC -->
</bitset>
<bitset name="end" extends="#instruction-cat0-0src">
<pattern low="49" high="51">xx0</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">0110</pattern> <!-- OPC -->
</bitset>
<bitset name="ret" extends="#instruction-cat0-0src">
<pattern low="49" high="51">xx0</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">0100</pattern> <!-- OPC -->
</bitset>
<bitset name="emit" extends="#instruction-cat0-0src">
<pattern low="49" high="51">xx0</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">0111</pattern> <!-- OPC -->
</bitset>
<bitset name="cut" extends="#instruction-cat0-0src">
<pattern low="49" high="51">xx0</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">1000</pattern> <!-- OPC -->
</bitset>
<bitset name="chmask" extends="#instruction-cat0-0src">
<pattern low="49" high="51">xx0</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">1001</pattern> <!-- OPC -->
</bitset>
<bitset name="chsh" extends="#instruction-cat0-0src">
<pattern low="49" high="51">xx0</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">1010</pattern> <!-- OPC -->
</bitset>
<bitset name="flow_rev" extends="#instruction-cat0-0src">
<pattern low="49" high="51">xx0</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">1011</pattern> <!-- OPC -->
</bitset>
<bitset name="shpe" extends="#instruction-cat0-0src">
<doc>SHader Prologue End</doc>
<pattern low="49" high="51">xx1</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">1000</pattern> <!-- OPC -->
</bitset>
<bitset name="prede" extends="#instruction-cat0-0src">
<pattern low="49" high="51">xx1</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">1111</pattern> <!-- OPC -->
</bitset>
<bitset name="#instruction-cat0-1src" extends="#instruction-cat0">
<display>
{SY}{SS}{EQ}{JP}{NAME} {INV1}p0.{COMP1}
</display>
<pattern low="32" high="36">00000</pattern>
<pattern low="37" high="39">000</pattern> <!-- BRTYPE -->
<pattern low="45" high="47">000</pattern> <!-- src1 -->
<field name="INV1" pos="52" type="bool" display="!">
<doc>Invert source condition</doc>
</field>
<field name="COMP1" low="53" high="54" type="#swiz">
<doc>Predicate register (p0.c) component for source</doc>
</field>
</bitset>
<bitset name="kill" extends="#instruction-cat0-1src">
<pattern low="49" high="51">xx0</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">0101</pattern> <!-- OPC -->
</bitset>
<bitset name="predt" extends="#instruction-cat0-1src">
<pattern low="49" high="51">xx1</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">1101</pattern> <!-- OPC -->
</bitset>
<bitset name="predf" extends="#instruction-cat0-1src">
<pattern low="49" high="51">xx1</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">1110</pattern> <!-- OPC -->
</bitset>
<bitset name="#instruction-cat0-immed" extends="#instruction-cat0">
<display>
{SY}{SS}{JP}{NAME} #{IMMED}
</display>
<pattern low="32" high="36">xxxxx</pattern> <!-- INDEX -->
<pattern low="37" high="39">xxx</pattern> <!-- BRTYPE -->
<pattern low="45" high="47">xxx</pattern> <!-- src1 -->
<pattern low="52" high="54">xxx</pattern> <!-- src0 -->
</bitset>
<bitset name="jump" extends="#instruction-cat0-immed">
<pattern low="49" high="51">xx0</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">0010</pattern> <!-- OPC -->
</bitset>
<bitset name="call" extends="#instruction-cat0-immed">
<pattern low="49" high="51">xx0</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">0011</pattern> <!-- OPC -->
</bitset>
<bitset name="bkt" extends="#instruction-cat0-immed">
<pattern low="49" high="51">xx1</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">0000</pattern> <!-- OPC -->
</bitset>
<bitset name="getone" extends="#instruction-cat0-immed">
<pattern low="49" high="51">xx1</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">0101</pattern> <!-- OPC -->
</bitset>
<bitset name="shps" extends="#instruction-cat0-immed">
<doc>SHader Prologue Start</doc>
<pattern low="49" high="51">xx1</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">0111</pattern> <!-- OPC -->
</bitset>
<bitset name="#instruction-cat0-branch" extends="#instruction-cat0">
<pattern low="49" high="51">xx0</pattern> <!-- OPC_HI -->
<pattern low="55" high="58">0001</pattern> <!-- OPC -->
</bitset>
<bitset name="brac" extends="#instruction-cat0-branch">
<display>
{SY}{SS}{EQ}{JP}{NAME}.{INDEX} #{IMMED}
</display>
<field name="INDEX" low="32" high="36" type="uint"/>
<pattern low="37" high="39">011</pattern> <!-- BRTYPE -->
<pattern low="45" high="47">xxx</pattern> <!-- src1 -->
<pattern low="52" high="54">xxx</pattern> <!-- src0 -->
<encode>
<map name="INDEX">src->cat0.idx</map>
</encode>
</bitset>
<bitset name="brax" extends="#instruction-cat0-branch">
<pattern low="32" high="36">xxxxx</pattern>
<pattern low="37" high="39">110</pattern> <!-- BRTYPE -->
<pattern low="45" high="47">xxx</pattern> <!-- src1 -->
<pattern low="52" high="54">xxx</pattern> <!-- src0 -->
</bitset>
<bitset name="#instruction-cat0-branch-1src" extends="#instruction-cat0-branch">
<display>
{SY}{SS}{EQ}{JP}{NAME} {INV1}p0.{COMP1}, #{IMMED}
</display>
<pattern low="32" high="36">xxxxx</pattern>
<pattern low="45" high="47">xxx</pattern> <!-- src1 -->
<field name="INV1" pos="52" type="bool" display="!">
<doc>Invert source condition</doc>
</field>
<field name="COMP1" low="53" high="54" type="#swiz">
<doc>Predicate register (p0.c) component for source</doc>
</field>
</bitset>
<bitset name="br" extends="#instruction-cat0-branch-1src">
<pattern low="37" high="39">000</pattern> <!-- BRTYPE -->
</bitset>
<bitset name="bany" extends="#instruction-cat0-branch-1src">
<pattern low="37" high="39">100</pattern> <!-- BRTYPE -->
</bitset>
<bitset name="ball" extends="#instruction-cat0-branch-1src">
<pattern low="37" high="39">101</pattern> <!-- BRTYPE -->
</bitset>
<bitset name="#instruction-cat0-branch-2src" extends="#instruction-cat0-branch">
<display>
{SY}{SS}{EQ}{JP}{NAME} {INV1}p0.{COMP1}, {INV2}p0.{COMP2}, #{IMMED}
</display>
<pattern low="32" high="36">xxxxx</pattern>
<!-- src1: -->
<field name="INV2" pos="45" type="bool" display="!">
<doc>Invert source 2 condition</doc>
</field>
<field name="COMP2" low="46" high="47" type="#swiz">
<doc>Predicate register (p0.c) component for source 2</doc>
</field>
<!-- src0: -->
<field name="INV1" pos="52" type="bool" display="!">
<doc>Invert source 1 condition</doc>
</field>
<field name="COMP1" low="53" high="54" type="#swiz">
<doc>Predicate register (p0.c) component for source 1</doc>
</field>
</bitset>
<bitset name="brao" extends="#instruction-cat0-branch-2src">
<pattern low="37" high="39">001</pattern> <!-- BRTYPE -->
</bitset>
<bitset name="braa" extends="#instruction-cat0-branch-2src">
<pattern low="37" high="39">010</pattern> <!-- BRTYPE -->
</bitset>
<!-- TODO rest of cat0 -->
</isa>

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src/freedreno/isa/ir3-cat1.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright © 2020 Google, Inc.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
-->
<isa>
<!--
Cat1 Instruction(s):
-->
<bitset name="#cat1-dst" size="8">
<doc>
Unlike other instruction categories, cat1 can have relative dest
</doc>
<override>
<expr>
({OFFSET} == 0) &amp;&amp; {DST_REL}
</expr>
<display>
r&lt;a0.x&gt;
</display>
<field name="OFFSET" low="0" high="7" type="uint"/>
</override>
<override>
<expr>
{DST_REL}
</expr>
<display>
r&lt;a0.x + {OFFSET}&gt;
</display>
<field name="OFFSET" low="0" high="7" type="uint"/>
</override>
<display>
{DST}
</display>
<field name="DST" low="0" high="7" type="#reg-gpr"/>
<encode type="struct ir3_register *">
<map name="DST">src</map>
<map name="OFFSET">src->array.offset</map>
</encode>
</bitset>
<bitset name="#instruction-cat1" extends="#instruction">
<field name="DST" low="32" high="39" type="#cat1-dst">
<param name="DST_REL"/>
</field>
<field name="REPEAT" low="40" high="42" type="#rptN"/>
<field name="SS" pos="44" type="bool" display="(ss)"/>
<field name="UL" pos="45" type="bool" display="(ul)"/>
<field name="DST_REL" pos="49" type="bool"/>
<field name="EVEN" pos="55" type="bool" display="(even)"/>
<field name="POS_INF" pos="56" type="bool" display="(pos_infinity)"/>
<field name="JP" pos="59" type="bool" display="(jp)"/>
<field name="SY" pos="60" type="bool" display="(sy)"/>
<pattern low="61" high="63">001</pattern> <!-- cat1 -->
<encode>
<map name="SRC">src->regs[1]</map>
<map name="SRC_R">!!(src->regs[1]->flags &amp; IR3_REG_R)</map>
<map name="UL">!!(src->flags &amp; IR3_INSTR_UL)</map>
<map name="DST_TYPE">src->cat1.dst_type</map>
<map name="DST_REL">!!(src->regs[0]->flags &amp; IR3_REG_RELATIV)</map>
<map name="SRC_TYPE">src->cat1.src_type</map>
<map name="EVEN">!!(src->regs[0]->flags &amp; IR3_REG_EVEN)</map>
<map name="POS_INF">!!(src->regs[0]->flags &amp; IR3_REG_POS_INF)</map>
</encode>
</bitset>
<bitset name="#instruction-cat1-mov" extends="#instruction-cat1">
<override>
<expr>
({DST} == 0xf4 /* a0.x */) &amp;&amp; ({SRC_TYPE} == 4 /* s16 */) &amp;&amp; ({DST_TYPE} == 4)
</expr>
<display>
{SY}{SS}{JP}{REPEAT}{UL}mova {EVEN}{POS_INF}a0.x, {SRC}
</display>
<assert low="32" high="39">11110100</assert> <!-- DST==a0.x -->
<assert low="46" high="48">100</assert> <!-- DST_TYPE==s16 -->
<assert low="50" high="52">100</assert> <!-- SRC_TYPE==s16 -->
</override>
<override>
<expr>
({DST} == 0xf5 /* a0.y */) &amp;&amp; ({SRC_TYPE} == 2 /* u16 */) &amp;&amp; ({DST_TYPE} == 2)
</expr>
<display>
{SY}{SS}{JP}{REPEAT}{UL}mova1 {EVEN}{POS_INF}a1.x, {SRC}
</display>
<assert low="32" high="39">11110101</assert> <!-- DST==a0.y -->
<assert low="46" high="48">010</assert> <!-- DST_TYPE==u16 -->
<assert low="50" high="52">010</assert> <!-- SRC_TYPE==u16 -->
</override>
<override>
<expr>
{SRC_TYPE} != {DST_TYPE}
</expr>
<display>
{SY}{SS}{JP}{REPEAT}{UL}cov.{SRC_TYPE}{DST_TYPE} {EVEN}{POS_INF}{DST_HALF}{DST}, {SRC}
</display>
</override>
<display>
{SY}{SS}{JP}{REPEAT}{UL}mov.{SRC_TYPE}{DST_TYPE} {EVEN}{POS_INF}{DST_HALF}{DST}, {SRC}
</display>
<pattern low="57" high="58">00</pattern> <!-- OPC -->
<derived name="HALF" type="bool" display="h">
<expr>
({SRC_TYPE} == 0) /* f16 */ ||
({SRC_TYPE} == 2) /* u16 */ ||
({SRC_TYPE} == 4) /* s16 */ ||
({SRC_TYPE} == 6) /* u8 */ ||
({SRC_TYPE} == 7) /* s8 */
</expr>
</derived>
<derived name="DST_HALF" type="bool" display="h">
<expr>
({DST_TYPE} == 0) /* f16 */ ||
({DST_TYPE} == 2) /* u16 */ ||
({DST_TYPE} == 4) /* s16 */ ||
({DST_TYPE} == 6) /* u8 */ ||
({DST_TYPE} == 7) /* s8 */
</expr>
</derived>
<field name="DST_TYPE" low="46" high="48" type="#type"/>
<field name="SRC_TYPE" low="50" high="52" type="#type"/>
</bitset>
<!--
Helpers for displaying cat1 source forms.. split out so the toplevel
instruction can just refer to {SRC}. This decouples the cov/mov/mova
permultations from the different src type permutations
-->
<bitset name="#cat1-immed-src" size="32">
<override>
<expr>
{SRC_TYPE} == 0 /* f16 */
</expr>
<display>
h({IMMED})
</display>
<field name="IMMED" low="0" high="15" type="float"/>
</override>
<override>
<expr>
{SRC_TYPE} == 1 /* f32 */
</expr>
<display>
({IMMED})
</display>
<field name="IMMED" low="0" high="31" type="float"/>
</override>
<override>
<expr>
({SRC_TYPE} == 3 /* u32 */) &amp;&amp; ({IMMED} > 0x1000)
</expr>
<display>
0x{IMMED}
</display>
<field name="IMMED" low="0" high="31" type="hex"/>
</override>
<override>
<expr>
{SRC_TYPE} == 4 /* s16 */
</expr>
<field name="IMMED" low="0" high="15" type="int"/>
</override>
<override>
<expr>
{SRC_TYPE} == 5 /* s32 */
</expr>
<field name="IMMED" low="0" high="31" type="int"/>
</override>
<display>
{IMMED}
</display>
<field name="IMMED" low="0" high="31" type="uint"/>
<encode type="struct ir3_register *">
<map name="IMMED">src->uim_val</map>
</encode>
</bitset>
<bitset name="#cat1-const-src" size="11">
<display>
{SRC_R}{HALF}{CONST}
</display>
<field name="CONST" low="0" high="10" type="#reg-const"/>
<encode type="struct ir3_register *">
<map name="CONST">src</map>
</encode>
</bitset>
<bitset name="#cat1-gpr-src" size="8">
<display>
{SRC_R}{HALF}{SRC}
</display>
<field name="SRC" low="0" high="7" type="#reg-gpr"/>
<encode type="struct ir3_register *">
<map name="SRC">src</map>
</encode>
</bitset>
<bitset name="#cat1-relative-gpr-src" size="10">
<display>
{SRC_R}{HALF}{SRC}
</display>
<field name="SRC" low="0" high="9" type="#reg-relative-gpr"/>
<encode type="struct ir3_register *">
<map name="SRC">src</map>
</encode>
</bitset>
<bitset name="#cat1-relative-const-src" size="10">
<display>
{SRC_R}{HALF}{SRC}
</display>
<field name="SRC" low="0" high="9" type="#reg-relative-const"/>
<encode type="struct ir3_register *">
<map name="SRC">src</map>
</encode>
</bitset>
<!--
cov/mov/mova permutations based on src type:
-->
<bitset name="mov-immed" extends="#instruction-cat1-mov">
<field name="SRC" low="0" high="31" type="#cat1-immed-src">
<param name="SRC_TYPE"/>
</field>
<pattern pos="43">0</pattern> <!-- SRC_R -->
<pattern low="53" high="54">10</pattern>
</bitset>
<bitset name="mov-const" extends="#instruction-cat1-mov">
<field name="SRC" low="0" high="10" type="#cat1-const-src">
<param name="SRC_R"/>
<param name="HALF"/>
</field>
<pattern low="11" high="31">000000000000000000000</pattern>
<field name="SRC_R" pos="43" type="bool" display="(r)"/>
<pattern low="53" high="54">01</pattern>
</bitset>
<bitset name="mov-gpr" extends="#instruction-cat1-mov">
<field name="SRC" low="0" high="7" type="#cat1-gpr-src">
<param name="SRC_R"/>
<param name="HALF"/>
</field>
<pattern low="8" high="31">000000000000000000000000</pattern>
<field name="SRC_R" pos="43" type="bool" display="(r)"/>
<pattern low="53" high="54">00</pattern>
</bitset>
<bitset name="#instruction-cat1-relative" extends="#instruction-cat1-mov">
<pattern pos="11">1</pattern>
<pattern low="12" high="31">00000000000000000000</pattern>
<field name="SRC_R" pos="43" type="bool" display="(r)"/>
<pattern low="53" high="54">00</pattern>
</bitset>
<bitset name="mov-relgpr" extends="#instruction-cat1-relative">
<field name="SRC" low="0" high="9" type="#cat1-relative-gpr-src">
<param name="SRC_R"/>
<param name="HALF"/>
</field>
<pattern pos="10">0</pattern>
</bitset>
<bitset name="mov-relconst" extends="#instruction-cat1-relative">
<field name="SRC" low="0" high="9" type="#cat1-relative-const-src">
<param name="SRC_R"/>
<param name="HALF"/>
</field>
<pattern pos="10">1</pattern>
</bitset>
<!--
Other newer cat1 instructions
-->
<bitset name="movmsk" extends="#instruction-cat1">
<display>
{SY}{SS}{JP}{UL}movmsk.w{W} {DST}
</display>
<derived name="W" type="uint">
<expr>
({REPEAT} + 1) * 32
</expr>
</derived>
<pattern low="0" high="31">00000000000000000000000000000000</pattern>
<pattern pos="43">0</pattern> <!-- SRC_R -->
<pattern low="46" high="48">011</pattern> <!-- DST_TYPE==u32 -->
<pattern low="50" high="52">011</pattern> <!-- SRC_TYPE==u32 -->
<pattern low="53" high="54">00</pattern>
<pattern low="57" high="58">11</pattern> <!-- OPC -->
<!--
TODO in ir3 things are encoded w/ instr->repeat==0 and repeat field is
reconstructed from wrmask.. but I'm not sure if that is actually accurate
(in terms of how delay slots work).. for now, work around that to match
the existing stuff:
-->
<encode>
<map name="REPEAT">util_last_bit(src->regs[0]->wrmask) - 1</map>
</encode>
</bitset>
</isa>

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src/freedreno/isa/ir3-cat2.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright © 2020 Google, Inc.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
-->
<isa>
<!--
Cat2 Instructions: one and two src ALU instructions
-->
<bitset name="#instruction-cat2" extends="#instruction">
<field name="DST" low="32" high="39" type="#reg-gpr"/>
<field name="REPEAT" low="40" high="41" type="#rptN"/>
<field name="SAT" pos="42" type="bool" display="(sat)"/>
<field name="SS" pos="44" type="bool" display="(ss)"/>
<field name="UL" pos="45" type="bool" display="(ul)"/>
<field name="DST_CONV" pos="46" type="bool">
<doc>
Destination register is opposite precision as source, ie.
if {FULL} is true then destination is half precision, and
visa versa.
</doc>
</field>
<derived name="DST_HALF" expr="#dest-half" type="bool" display="h"/>
<field name="EI" pos="47" type="bool" display="(ei)"/>
<field name="FULL" pos="52" type="bool">
<doc>Full precision source registers</doc>
</field>
<field name="JP" pos="59" type="bool" display="(jp)"/>
<field name="SY" pos="60" type="bool" display="(sy)"/>
<pattern low="61" high="63">010</pattern> <!-- cat2 -->
<!--
NOTE, both SRC1_R and SRC2_R are defined at this level because
SRC2_R is still a valid bit for (nopN) (REPEAT==0) for cat2
instructions with only a single src
-->
<field name="SRC1_R" pos="43" type="bool" display="(r)"/>
<field name="SRC2_R" pos="51" type="bool" display="(r)"/>
<derived name="ZERO" expr="#zero" type="bool" display=""/>
<encode>
<map name="SAT">!!(src->flags &amp; IR3_INSTR_SAT)</map>
<map name="DST_CONV">
((src->regs[0]->num >> 2) == 62) ? 0 :
!!((src->regs[1]->flags ^ src->regs[0]->flags) &amp; IR3_REG_HALF)
</map>
<map name="EI">!!(src->regs[0]->flags &amp; IR3_REG_EI)</map>
<map name="FULL">!(src->regs[1]->flags &amp; IR3_REG_HALF)</map>
<map name="SRC1_R">extract_SRC1_R(src)</map>
<map name="SRC2_R">extract_SRC2_R(src)</map>
</encode>
</bitset>
<bitset name="#instruction-cat2-1src" extends="#instruction-cat2">
<override expr="#cat2-cat3-nop-encoding">
<display>
{SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME} {EI}{DST_HALF}{DST}, {SRC1}
</display>
<derived name="NOP" expr="#cat2-cat3-nop-value" type="uint"/>
<field name="SRC1" low="0" high="15" type="#multisrc">
<param name="ZERO" as="SRC_R"/>
<param name="FULL"/>
</field>
</override>
<display>
{SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {EI}{DST_HALF}{DST}, {SRC1}
</display>
<pattern low="16" high="31">xxxxxxxxxxxxxxxx</pattern>
<pattern low="48" high="50">xxx</pattern> <!-- COND -->
<field name="SRC1" low="0" high="15" type="#multisrc">
<param name="SRC1_R" as="SRC_R"/>
<param name="FULL"/>
</field>
</bitset>
<!-- TODO rest of cat2-1src -->
<bitset name="#instruction-cat2-2src" extends="#instruction-cat2">
<override expr="#cat2-cat3-nop-encoding">
<display>
{SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME} {EI}{DST_HALF}{DST}, {SRC1}, {SRC2}
</display>
<derived name="NOP" expr="#cat2-cat3-nop-value" type="uint"/>
<field name="SRC1" low="0" high="15" type="#multisrc">
<param name="ZERO" as="SRC_R"/>
<param name="FULL"/>
</field>
<field name="SRC2" low="16" high="31" type="#multisrc">
<param name="ZERO" as="SRC_R"/>
<param name="FULL"/>
</field>
</override>
<display>
{SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {EI}{DST_HALF}{DST}, {SRC1}, {SRC2}
</display>
<field name="SRC1" low="0" high="15" type="#multisrc">
<param name="SRC1_R" as="SRC_R"/>
<param name="FULL"/>
</field>
<field name="SRC2" low="16" high="31" type="#multisrc">
<param name="SRC2_R" as="SRC_R"/>
<param name="FULL"/>
</field>
<pattern low="48" high="50">xxx</pattern> <!-- COND -->
</bitset>
<!-- The cmp*.* instructions additionally have a condition code: -->
<bitset name="#instruction-cat2-2src-cond" extends="#instruction-cat2">
<override expr="#cat2-cat3-nop-encoding">
<display>
{SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME}.{COND} {EI}{DST_HALF}{DST}, {SRC1}, {SRC2}
</display>
<derived name="NOP" expr="#cat2-cat3-nop-value" type="uint"/>
<field name="SRC1" low="0" high="15" type="#multisrc">
<param name="ZERO" as="SRC_R"/>
<param name="FULL"/>
</field>
<field name="SRC2" low="16" high="31" type="#multisrc">
<param name="ZERO" as="SRC_R"/>
<param name="FULL"/>
</field>
</override>
<display>
{SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME}.{COND} {EI}{DST_HALF}{DST}, {SRC1}, {SRC2}
</display>
<field name="SRC1" low="0" high="15" type="#multisrc">
<param name="SRC1_R" as="SRC_R"/>
<param name="FULL"/>
</field>
<field name="SRC2" low="16" high="31" type="#multisrc">
<param name="SRC2_R" as="SRC_R"/>
<param name="FULL"/>
</field>
<field name="COND" low="48" high="50" type="#cond"/>
<encode>
<map name="COND">src->cat2.condition</map>
</encode>
</bitset>
<bitset name="add.f" extends="#instruction-cat2-2src">
<pattern low="53" high="58">000000</pattern>
</bitset>
<bitset name="min.f" extends="#instruction-cat2-2src">
<pattern low="53" high="58">000001</pattern>
</bitset>
<bitset name="max.f" extends="#instruction-cat2-2src">
<pattern low="53" high="58">000010</pattern>
</bitset>
<bitset name="mul.f" extends="#instruction-cat2-2src">
<pattern low="53" high="58">000011</pattern>
</bitset>
<bitset name="sign.f" extends="#instruction-cat2-1src">
<pattern low="53" high="58">000100</pattern>
</bitset>
<bitset name="cmps.f" extends="#instruction-cat2-2src-cond">
<pattern low="53" high="58">000101</pattern>
</bitset>
<bitset name="absneg.f" extends="#instruction-cat2-1src">
<pattern low="53" high="58">000110</pattern>
</bitset>
<bitset name="cmpv.f" extends="#instruction-cat2-2src-cond">
<pattern low="53" high="58">000111</pattern>
</bitset>
<bitset name="floor.f" extends="#instruction-cat2-1src">
<pattern low="53" high="58">001001</pattern>
</bitset>
<bitset name="ceil.f" extends="#instruction-cat2-1src">
<pattern low="53" high="58">001010</pattern>
</bitset>
<bitset name="rndne.f" extends="#instruction-cat2-1src">
<pattern low="53" high="58">001011</pattern>
</bitset>
<bitset name="rndaz.f" extends="#instruction-cat2-1src">
<pattern low="53" high="58">001100</pattern>
</bitset>
<bitset name="trunc.f" extends="#instruction-cat2-1src">
<pattern low="53" high="58">001101</pattern>
</bitset>
<bitset name="add.u" extends="#instruction-cat2-2src">
<pattern low="53" high="58">010000</pattern>
</bitset>
<bitset name="add.s" extends="#instruction-cat2-2src">
<pattern low="53" high="58">010001</pattern>
</bitset>
<bitset name="sub.u" extends="#instruction-cat2-2src">
<pattern low="53" high="58">010010</pattern>
</bitset>
<bitset name="sub.s" extends="#instruction-cat2-2src">
<pattern low="53" high="58">010011</pattern>
</bitset>
<bitset name="cmps.u" extends="#instruction-cat2-2src-cond">
<pattern low="53" high="58">010100</pattern>
</bitset>
<bitset name="cmps.s" extends="#instruction-cat2-2src-cond">
<pattern low="53" high="58">010101</pattern>
</bitset>
<bitset name="min.u" extends="#instruction-cat2-2src">
<pattern low="53" high="58">010110</pattern>
</bitset>
<bitset name="min.s" extends="#instruction-cat2-2src">
<pattern low="53" high="58">010111</pattern>
</bitset>
<bitset name="max.u" extends="#instruction-cat2-2src">
<pattern low="53" high="58">011000</pattern>
</bitset>
<bitset name="max.s" extends="#instruction-cat2-2src">
<pattern low="53" high="58">011001</pattern>
</bitset>
<bitset name="absneg.s" extends="#instruction-cat2-1src">
<pattern low="53" high="58">011010</pattern>
</bitset>
<bitset name="and.b" extends="#instruction-cat2-2src">
<pattern low="53" high="58">011100</pattern>
</bitset>
<bitset name="or.b" extends="#instruction-cat2-2src">
<pattern low="53" high="58">011101</pattern>
</bitset>
<bitset name="not.b" extends="#instruction-cat2-1src">
<pattern low="53" high="58">011110</pattern>
</bitset>
<bitset name="xor.b" extends="#instruction-cat2-2src">
<pattern low="53" high="58">011111</pattern>
</bitset>
<bitset name="cmpv.u" extends="#instruction-cat2-2src-cond">
<pattern low="53" high="58">100001</pattern>
</bitset>
<bitset name="cmpv.s" extends="#instruction-cat2-2src-cond">
<pattern low="53" high="58">100010</pattern>
</bitset>
<bitset name="mul.u24" extends="#instruction-cat2-2src">
<pattern low="53" high="58">110000</pattern>
</bitset>
<bitset name="mul.s24" extends="#instruction-cat2-2src">
<pattern low="53" high="58">110001</pattern>
</bitset>
<bitset name="mull.u" extends="#instruction-cat2-2src">
<pattern low="53" high="58">110010</pattern>
</bitset>
<bitset name="bfrev.b" extends="#instruction-cat2-1src">
<pattern low="53" high="58">110011</pattern>
</bitset>
<bitset name="clz.s" extends="#instruction-cat2-1src">
<pattern low="53" high="58">110100</pattern>
</bitset>
<bitset name="clz.b" extends="#instruction-cat2-1src">
<pattern low="53" high="58">110101</pattern>
</bitset>
<bitset name="shl.b" extends="#instruction-cat2-2src">
<pattern low="53" high="58">110110</pattern>
</bitset>
<bitset name="shr.b" extends="#instruction-cat2-2src">
<pattern low="53" high="58">110111</pattern>
</bitset>
<bitset name="ashr.b" extends="#instruction-cat2-2src">
<pattern low="53" high="58">111000</pattern>
</bitset>
<bitset name="bary.f" extends="#instruction-cat2-2src">
<pattern low="53" high="58">111001</pattern>
</bitset>
<bitset name="mgen.b" extends="#instruction-cat2-2src">
<pattern low="53" high="58">111010</pattern>
</bitset>
<bitset name="getbit.b" extends="#instruction-cat2-2src">
<pattern low="53" high="58">111011</pattern>
</bitset>
<bitset name="setrm" extends="#instruction-cat2-1src">
<pattern low="53" high="58">111100</pattern>
</bitset>
<bitset name="cbits.b" extends="#instruction-cat2-1src">
<pattern low="53" high="58">111101</pattern>
</bitset>
<bitset name="shb" extends="#instruction-cat2-2src">
<pattern low="53" high="58">111110</pattern>
</bitset>
<bitset name="msad" extends="#instruction-cat2-2src">
<pattern low="53" high="58">111111</pattern>
</bitset>
</isa>

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<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright © 2020 Google, Inc.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
-->
<isa>
<!--
Cat3 Instructions: three-source ALU instructions
-->
<bitset name="#cat3-src" size="13">
<doc>
cat3 src1 and src2, some parts are similar to cat2/cat4 src
encoding, but a few extra bits trimmed out to squeeze in the
3rd src register (dropping (abs), immed encoding, and moving
a few other bits elsewhere)
</doc>
<encode type="struct ir3_register *" case-prefix="REG_"/>
</bitset>
<bitset name="#cat3-src-gpr" extends="#cat3-src">
<display>
{HALF}{SRC}
</display>
<field name="SRC" low="0" high="7" type="#reg-gpr"/>
<pattern low="8" high="12">00000</pattern>
<encode>
<map name="SRC">src</map>
</encode>
</bitset>
<bitset name="#cat3-src-const" extends="#cat3-src">
<display>
{HALF}c{CONST}.{SWIZ}
</display>
<field name="SWIZ" low="0" high="1" type="#swiz"/>
<field name="CONST" low="2" high="10" type="uint"/>
<pattern low="11" high="12">10</pattern>
<encode>
<map name="CONST">src->num >> 2</map>
<map name="SWIZ">src->num &amp; 0x3</map>
</encode>
</bitset>
<bitset name="#cat3-src-relative" extends="#cat3-src">
<pattern low="11" high="12">01</pattern>
<encode>
<map name="OFFSET">src->array.offset</map>
</encode>
</bitset>
<bitset name="#cat3-src-relative-gpr" extends="#cat3-src-relative">
<display>
{HALF}r&lt;a0.x + {OFFSET}&gt;
</display>
<field name="OFFSET" low="0" high="9" type="int"/>
<pattern pos="10">0</pattern>
</bitset>
<bitset name="#cat3-src-relative-const" extends="#cat3-src-relative">
<display>
{HALF}c&lt;a0.x + {OFFSET}&gt;
</display>
<field name="OFFSET" low="0" high="9" type="int"/>
<pattern pos="10">1</pattern>
</bitset>
<bitset name="#instruction-cat3" extends="#instruction">
<override expr="#cat2-cat3-nop-encoding">
<display>
{SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME} {DST_HALF}{DST}, {SRC1_NEG}{SRC1}, {SRC2_NEG}{HALF}{SRC2}, {SRC3_NEG}{SRC3}
</display>
<derived name="NOP" expr="#cat2-cat3-nop-value" type="uint"/>
</override>
<display>
{SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {DST_HALF}{DST}, {SRC1_NEG}{SRC1_R}{SRC1}, {SRC2_NEG}{SRC2_R}{HALF}{SRC2}, {SRC3_NEG}{SRC3_R}{SRC3}
</display>
<field name="SRC1" low="0" high="12" type="#cat3-src">
<param name="HALF"/>
</field>
<!--
Note b13 triggers some different disasm, so possibly this
becomes OPC_HI ?
-->
<pattern pos="13">x</pattern>
<field name="SRC1_NEG" pos="14" type="bool" display="(neg)"/>
<field name="SRC2_R" pos="15" type="bool" display="(r)"/>
<field name="SRC3" low="16" high="28" type="#cat3-src">
<param name="HALF"/>
</field>
<field name="SRC3_R" pos="29" type="bool" display="(r)"/>
<field name="SRC2_NEG" pos="30" type="bool" display="(neg)"/>
<field name="SRC3_NEG" pos="31" type="bool" display="(neg)"/>
<field name="DST" low="32" high="39" type="#reg-gpr"/>
<field name="REPEAT" low="40" high="41" type="#rptN"/>
<field name="SAT" pos="42" type="bool" display="(sat)"/>
<field name="SRC1_R" pos="43" type="bool" display="(r)"/>
<field name="SS" pos="44" type="bool" display="(ss)"/>
<field name="UL" pos="45" type="bool" display="(ul)"/>
<field name="DST_CONV" pos="46" type="bool">
<doc>
The source precision is determined by the instruction
opcode. If {DST_CONV} the result is widened/narrowed
to the opposite precision.
</doc>
</field>
<field name="SRC2" low="47" high="54" type="#reg-gpr"/>
<!-- opcode, 4 bits -->
<field name="JP" pos="59" type="bool" display="(jp)"/>
<field name="SY" pos="60" type="bool" display="(sy)"/>
<pattern low="61" high="63">011</pattern> <!-- cat3 -->
<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
<derived name="DST_HALF" expr="#dest-half" type="bool" display="h"/>
<encode>
<map name="SRC1_NEG">!!(src->regs[1]->flags &amp; (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map>
<map name="SRC1_R">extract_SRC1_R(src)</map>
<map name="SRC2_R">extract_SRC2_R(src)</map>
<map name="SRC3_R">!!(src->regs[3]->flags &amp; IR3_REG_R)</map>
<map name="SRC2_NEG">!!(src->regs[2]->flags &amp; (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map>
<map name="SRC3_NEG">!!(src->regs[3]->flags &amp; (IR3_REG_FNEG | IR3_REG_SNEG | IR3_REG_BNOT))</map>
<map name="SRC1">src->regs[1]</map>
<map name="DST_CONV">
((src->regs[0]->num >> 2) == 62) ? 0 :
!!((src->regs[1]->flags ^ src->regs[0]->flags) &amp; IR3_REG_HALF)
</map>
</encode>
</bitset>
<bitset name="mad.u16" extends="#instruction-cat3">
<pattern low="55" high="58">0000</pattern> <!-- OPC -->
<derived name="FULL" expr="#false" type="bool"/>
</bitset>
<bitset name="madsh.u16" extends="#instruction-cat3">
<pattern low="55" high="58">0001</pattern> <!-- OPC -->
<derived name="FULL" expr="#true" type="bool"/>
</bitset>
<bitset name="mad.s16" extends="#instruction-cat3">
<pattern low="55" high="58">0010</pattern> <!-- OPC -->
<derived name="FULL" expr="#false" type="bool"/>
</bitset>
<bitset name="madsh.m16" extends="#instruction-cat3">
<pattern low="55" high="58">0011</pattern> <!-- OPC -->
<derived name="FULL" expr="#true" type="bool"/>
</bitset>
<bitset name="mad.u24" extends="#instruction-cat3">
<pattern low="55" high="58">0100</pattern> <!-- OPC -->
<derived name="FULL" expr="#true" type="bool"/>
</bitset>
<bitset name="mad.s24" extends="#instruction-cat3">
<pattern low="55" high="58">0101</pattern> <!-- OPC -->
<derived name="FULL" expr="#true" type="bool"/>
</bitset>
<bitset name="mad.f16" extends="#instruction-cat3">
<pattern low="55" high="58">0110</pattern> <!-- OPC -->
<derived name="FULL" expr="#false" type="bool"/>
</bitset>
<bitset name="mad.f32" extends="#instruction-cat3">
<pattern low="55" high="58">0111</pattern> <!-- OPC -->
<derived name="FULL" expr="#true" type="bool"/>
</bitset>
<bitset name="sel.b16" extends="#instruction-cat3">
<pattern low="55" high="58">1000</pattern> <!-- OPC -->
<derived name="FULL" expr="#false" type="bool"/>
</bitset>
<bitset name="sel.b32" extends="#instruction-cat3">
<pattern low="55" high="58">1001</pattern> <!-- OPC -->
<derived name="FULL" expr="#true" type="bool"/>
</bitset>
<bitset name="sel.s16" extends="#instruction-cat3">
<pattern low="55" high="58">1010</pattern> <!-- OPC -->
<derived name="FULL" expr="#false" type="bool"/>
</bitset>
<bitset name="sel.s32" extends="#instruction-cat3">
<pattern low="55" high="58">1011</pattern> <!-- OPC -->
<derived name="FULL" expr="#true" type="bool"/>
</bitset>
<bitset name="sel.f16" extends="#instruction-cat3">
<pattern low="55" high="58">1100</pattern> <!-- OPC -->
<derived name="FULL" expr="#false" type="bool"/>
</bitset>
<bitset name="sel.f32" extends="#instruction-cat3">
<pattern low="55" high="58">1101</pattern> <!-- OPC -->
<derived name="FULL" expr="#true" type="bool"/>
</bitset>
<bitset name="sad.s16" extends="#instruction-cat3">
<pattern low="55" high="58">1110</pattern> <!-- OPC -->
<derived name="FULL" expr="#false" type="bool"/>
</bitset>
<bitset name="sad.s32" extends="#instruction-cat3">
<pattern low="55" high="58">1111</pattern> <!-- OPC -->
<derived name="FULL" expr="#false" type="bool"/> <!-- We think? -->
</bitset>
</isa>

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<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright © 2020 Google, Inc.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
-->
<isa>
<!--
Cat4 Instructions: SFU (aka EFU) instructions
-->
<bitset name="#instruction-cat4" extends="#instruction">
<display>
{SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {DST_HALF}{DST}, {SRC}
</display>
<field name="SRC" low="0" high="15" type="#multisrc">
<param name="SRC_R"/>
<param name="FULL"/>
</field>
<pattern low="16" high="31">xxxxxxxxxxxxxxxx</pattern>
<field name="DST" low="32" high="39" type="#reg-gpr"/>
<field name="REPEAT" low="40" high="41" type="#rptN"/>
<field name="SAT" pos="42" type="bool" display="(sat)"/>
<field name="SRC_R" pos="43" type="bool" display="(r)"/>
<field name="SS" pos="44" type="bool" display="(ss)"/>
<field name="UL" pos="45" type="bool" display="(ul)"/>
<field name="DST_CONV" pos="46" type="bool">
<doc>
Destination register is opposite precision as source, ie.
if {FULL} is true then destination is half precision, and
visa versa.
</doc>
</field>
<derived name="DST_HALF" expr="#dest-half" type="bool" display="h"/>
<pattern low="47" high="51">xxxxx</pattern>
<field name="FULL" pos="52" type="bool">
<doc>Full precision source registers</doc>
</field>
<!-- 6b opc -->
<field name="JP" pos="59" type="bool" display="(jp)"/>
<field name="SY" pos="60" type="bool" display="(sy)"/>
<pattern low="61" high="63">100</pattern> <!-- cat4 -->
<encode>
<map name="SRC">src->regs[1]</map>
<map name="DST_CONV">
((src->regs[0]->num >> 2) == 62) ? 0 :
!!((src->regs[1]->flags ^ src->regs[0]->flags) &amp; IR3_REG_HALF)
</map>
<map name="FULL">!(src->regs[1]->flags &amp; IR3_REG_HALF)</map>
<map name="SRC_R">!!(src->regs[1]->flags &amp; IR3_REG_R)</map>
</encode>
</bitset>
<bitset name="rcp" extends="#instruction-cat4">
<pattern low="53" high="58">000000</pattern> <!-- OPC -->
</bitset>
<bitset name="rsq" extends="#instruction-cat4">
<pattern low="53" high="58">000001</pattern> <!-- OPC -->
</bitset>
<bitset name="log2" extends="#instruction-cat4">
<pattern low="53" high="58">000010</pattern> <!-- OPC -->
</bitset>
<bitset name="exp2" extends="#instruction-cat4">
<pattern low="53" high="58">000011</pattern> <!-- OPC -->
</bitset>
<bitset name="sin" extends="#instruction-cat4">
<pattern low="53" high="58">000100</pattern> <!-- OPC -->
</bitset>
<bitset name="cos" extends="#instruction-cat4">
<pattern low="53" high="58">000101</pattern> <!-- OPC -->
</bitset>
<bitset name="sqrt" extends="#instruction-cat4">
<pattern low="53" high="58">000110</pattern> <!-- OPC -->
</bitset>
<!--
NOTE that these are 8+opc from their highp equivs, so it's possible
that the high order bit in the opc field has been repurposed for
half-precision use? But note that other ops (rcp/lsin/cos/sqrt)
still use the same opc as highp
-->
<bitset name="hrsq" extends="#instruction-cat4">
<pattern low="53" high="58">001001</pattern> <!-- OPC -->
</bitset>
<bitset name="hlog2" extends="#instruction-cat4">
<pattern low="53" high="58">001010</pattern> <!-- OPC -->
</bitset>
<bitset name="hexp2" extends="#instruction-cat4">
<pattern low="53" high="58">001011</pattern> <!-- OPC -->
</bitset>
</isa>

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<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright © 2020 Google, Inc.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
-->
<isa>
<!--
Cat5 Instructions: texture instructions
-->
<bitset name="#cat5-s2en-bindless-base" size="1">
<doc>
The BASE field is actually split across BASE_LO and BASE_HI,
but '.baseN' should only appear in the bindless case.. the
easiest way to accomplish that is by splitting it out into a
bitset. We just arbitrarily map this to BASE_LO
</doc>
<override>
<expr>{BINDLESS}</expr>
<display>
.base{BASE}
</display>
</override>
<display/>
<field name="BASE_LO" pos="0" type="uint"/>
<derived name="BASE" type="uint">
<expr>({BASE_HI} * 2) | {BASE_LO}</expr>
</derived>
<encode type="struct ir3_instruction *">
<map name="BASE_LO">src->cat5.tex_base &amp; 0x1</map>
</encode>
</bitset>
<bitset name="#instruction-cat5" extends="#instruction">
<override>
<expr>{S2EN_BINDLESS}</expr>
<doc>
The s2en (indirect) or bindless case
</doc>
<display>
{SY}{JP}{NAME}{3D}{A}{O}{P}{S}{S2EN}{UNIFORM}{BASE} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1}{SRC2}{SRC3}{A1}
</display>
<field name="BASE_HI" low="19" high="20" type="uint"/>
<field name="SRC3" low="21" high="28" type="#cat5-src3">
<param name="BINDLESS"/>
<param name="DESC_MODE"/>
<param name="HAS_SAMP"/>
<param name="HAS_TEX"/>
</field>
<field name="DESC_MODE" low="29" high="31" type="#cat5-s2en-bindless-desc-mode"/>
<field name="BASE" pos="47" type="#cat5-s2en-bindless-base">
<param name="BINDLESS"/>
<param name="BASE_HI"/>
</field>
<derived name="BINDLESS" expr="#cat5-s2enb-is-bindless" type="bool"/>
<derived name="S2EN" expr="#cat5-s2enb-is-indirect" type="bool" display=".s2en"/>
<derived name="UNIFORM" expr="#cat5-s2enb-is-uniform" type="bool" display=".uniform"/>
<derived name="A1" expr="#cat5-s2enb-uses_a1" type="bool" display=", a1.x"/>
</override>
<doc>
The "normal" case, ie. not s2en (indirect) and/or bindless
</doc>
<display>
{SY}{JP}{NAME}{3D}{A}{O}{P}{S} {TYPE}({WRMASK}){DST_HALF}{DST}{SRC1}{SRC2}{SAMP}{TEX}
</display>
<derived name="DST_HALF" type="bool" display="h">
<expr>
({TYPE} == 0) /* f16 */ ||
({TYPE} == 2) /* u16 */ ||
({TYPE} == 4) /* s16 */ ||
({TYPE} == 6) /* u8 */ ||
({TYPE} == 7) /* s8 */
</expr>
</derived>
<field name="FULL" pos="0" type="bool"/>
<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
<field name="SRC1" low="1" high="8" type="#cat5-src1">
<param name="NUM_SRC"/>
<param name="HALF"/>
</field>
<field name="SRC2" low="9" high="16" type="#cat5-src2">
<param name="NUM_SRC"/>
<param name="HALF"/>
<param name="O"/>
</field>
<!--
TODO remainder of first 32b differ depending on s2en/bindless..
possibly use overrides? Need to sort-out how to display..
Note b17 seems to show up in some blob traces (samgpN), need
to figure out what this bit does
-->
<pattern low="17" high="18">0x</pattern>
<assert low="19" high="20">00</assert> <!-- BASE_HI -->
<field name="SAMP" low="21" high="24" type="#cat5-samp">
<param name="HAS_SAMP"/>
</field>
<field name="TEX" low="25" high="31" type="#cat5-tex">
<param name="HAS_TEX"/>
</field>
<field name="DST" low="32" high="39" type="#reg-gpr"/>
<field name="WRMASK" low="40" high="43" type="#wrmask"/>
<field name="TYPE" low="44" high="46" type="#cat5-type">
<param name="HAS_TYPE"/>
</field>
<assert pos="47">0</assert> <!-- BASE_LO -->
<field name="3D" pos="48" type="bool" display=".3d"/>
<field name="A" pos="49" type="bool" display=".a"/>
<field name="S" pos="50" type="bool" display=".s"/>
<field name="S2EN_BINDLESS" pos="51" type="bool"/>
<field name="O" pos="52" type="bool" display=".o"/>
<field name="P" pos="53" type="bool" display=".p"/>
<!-- OPC -->
<field name="JP" pos="59" type="bool" display="(jp)"/>
<field name="SY" pos="60" type="bool" display="(sy)"/>
<pattern low="61" high="63">101</pattern> <!-- cat5 -->
<encode>
<map name="FULL">extract_cat5_FULL(src)</map>
<map name="TEX">src</map>
<map name="SAMP">src</map>
<map name="WRMASK">src->regs[0]->wrmask</map>
<map name="BASE">src</map>
<map name="TYPE">src</map>
<map name="BASE_HI">src->cat5.tex_base >> 1</map>
<map name="3D">!!(src->flags &amp; IR3_INSTR_3D)</map>
<map name="A">!!(src->flags &amp; IR3_INSTR_A)</map>
<map name="S">!!(src->flags &amp; IR3_INSTR_S)</map>
<map name="S2EN_BINDLESS">!!(src->flags &amp; (IR3_INSTR_S2EN | IR3_INSTR_B))</map>
<map name="O">!!(src->flags &amp; IR3_INSTR_O)</map>
<map name="P">!!(src->flags &amp; IR3_INSTR_P)</map>
<map name="DESC_MODE">extract_cat5_DESC_MODE(src)</map>
<!--
TODO the src order is currently a bit messy due to ir3 using regs[1]
for s2en src in the s2en case
-->
<map name="SRC1">extract_cat5_SRC(src, 1)</map>
<map name="SRC2">extract_cat5_SRC(src, 2)</map>
<map name="SRC3">src->regs[1]</map>
</encode>
</bitset>
<bitset name="isam" extends="#instruction-cat5">
<pattern low="54" high="58">00000</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="isaml" extends="#instruction-cat5">
<pattern low="54" high="58">00001</pattern>
<derived name="NUM_SRC" expr="#two" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="isamm" extends="#instruction-cat5">
<pattern low="54" high="58">00010</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="sam" extends="#instruction-cat5">
<pattern low="54" high="58">00011</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="samb" extends="#instruction-cat5">
<pattern low="54" high="58">00100</pattern>
<derived name="NUM_SRC" expr="#two" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="saml" extends="#instruction-cat5">
<pattern low="54" high="58">00101</pattern>
<derived name="NUM_SRC" expr="#two" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="samgq" extends="#instruction-cat5">
<pattern low="54" high="58">00110</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="getlod" extends="#instruction-cat5">
<pattern low="54" high="58">00111</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="conv" extends="#instruction-cat5">
<pattern low="54" high="58">01000</pattern>
<derived name="NUM_SRC" expr="#two" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="convm" extends="#instruction-cat5">
<pattern low="54" high="58">01001</pattern>
<derived name="NUM_SRC" expr="#two" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="getsize" extends="#instruction-cat5">
<pattern low="54" high="58">01010</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#false" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="getbuf" extends="#instruction-cat5">
<pattern low="54" high="58">01011</pattern>
<derived name="NUM_SRC" expr="#zero" type="uint"/>
<derived name="HAS_SAMP" expr="#false" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="getpos" extends="#instruction-cat5">
<pattern low="54" high="58">01100</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#false" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="getinfo" extends="#instruction-cat5">
<pattern low="54" high="58">01101</pattern>
<derived name="NUM_SRC" expr="#zero" type="uint"/>
<derived name="HAS_SAMP" expr="#false" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="dsx" extends="#instruction-cat5">
<pattern low="54" high="58">01110</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#false" type="bool"/>
<derived name="HAS_TEX" expr="#false" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="dsy" extends="#instruction-cat5">
<pattern low="54" high="58">01111</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#false" type="bool"/>
<derived name="HAS_TEX" expr="#false" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="gather4r" extends="#instruction-cat5">
<pattern low="54" high="58">10000</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="gather4g" extends="#instruction-cat5">
<pattern low="54" high="58">10001</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="gather4b" extends="#instruction-cat5">
<pattern low="54" high="58">10010</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="gather4a" extends="#instruction-cat5">
<pattern low="54" high="58">10011</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="samgp0" extends="#instruction-cat5">
<pattern low="54" high="58">10100</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="samgp1" extends="#instruction-cat5">
<pattern low="54" high="58">10101</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="samgp2" extends="#instruction-cat5">
<pattern low="54" high="58">10110</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="samgp3" extends="#instruction-cat5">
<pattern low="54" high="58">10111</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#true" type="bool"/>
<derived name="HAS_TEX" expr="#true" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="dsxpp.1" extends="#instruction-cat5">
<pattern low="54" high="58">11000</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#false" type="bool"/>
<derived name="HAS_TEX" expr="#false" type="bool"/>
<derived name="HAS_TYPE" expr="#false" type="bool"/>
</bitset>
<bitset name="dsypp.1" extends="#instruction-cat5">
<pattern low="54" high="58">11001</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#false" type="bool"/>
<derived name="HAS_TEX" expr="#false" type="bool"/>
<derived name="HAS_TYPE" expr="#false" type="bool"/>
</bitset>
<bitset name="rgetpos" extends="#instruction-cat5">
<pattern low="54" high="58">11010</pattern>
<derived name="NUM_SRC" expr="#one" type="uint"/>
<derived name="HAS_SAMP" expr="#false" type="bool"/>
<derived name="HAS_TEX" expr="#false" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<bitset name="rgetinfo" extends="#instruction-cat5">
<pattern low="54" high="58">11011</pattern>
<derived name="NUM_SRC" expr="#zero" type="uint"/>
<derived name="HAS_SAMP" expr="#false" type="bool"/>
<derived name="HAS_TEX" expr="#false" type="bool"/>
<derived name="HAS_TYPE" expr="#true" type="bool"/>
</bitset>
<!--
All the magic for conditionally displaying various srcs, etc
for the non-bindless / non-indirect case, or things that are in
common with the bindless / indirect case
-->
<bitset name="#cat5-src1" size="8">
<override>
<expr>{NUM_SRC} > 0</expr>
<display>
, {HALF}{SRC}
</display>
<field name="SRC" low="0" high="7" type="#reg-gpr"/>
</override>
<display/>
<assert low="0" high="7">00000000</assert>
<encode type="struct ir3_register *">
<map name="SRC">src</map>
</encode>
</bitset>
<bitset name="#cat5-src2" size="8">
<override>
<expr>{O} || ({NUM_SRC} > 1)</expr>
<display>
, {HALF}{SRC}
</display>
<field name="SRC" low="0" high="7" type="#reg-gpr"/>
</override>
<display/>
<assert low="0" high="7">00000000</assert>
<encode type="struct ir3_register *">
<map name="SRC">src</map>
</encode>
</bitset>
<bitset name="#cat5-samp" size="4">
<override>
<expr>{HAS_SAMP}</expr>
<display>
, s#{SAMP}
</display>
<field name="SAMP" low="0" high="3" type="uint"/>
</override>
<display/>
<assert low="0" high="3">0000</assert>
<encode type="struct ir3_instruction *">
<map name="SAMP">src->cat5.samp</map>
</encode>
</bitset>
<bitset name="#cat5-samp-s2en-bindless-a1" size="8">
<doc>s2en (indirect) / bindless case with a1.x has 8b samp</doc>
<override>
<expr>{HAS_SAMP}</expr>
<display>
, s#{SAMP}
</display>
<field name="SAMP" low="0" high="8" type="uint"/>
</override>
<display/>
<assert low="0" high="7">00000000</assert>
<encode type="struct ir3_instruction *">
<map name="SAMP">src->cat5.samp</map>
</encode>
</bitset>
<bitset name="#cat5-tex" size="7">
<override>
<expr>{HAS_TEX}</expr>
<display>
, t#{TEX}
</display>
<field name="TEX" low="0" high="6" type="uint"/>
</override>
<display/>
<assert low="0" high="6">0000000</assert>
<encode type="struct ir3_instruction *">
<map name="TEX">src->cat5.tex</map>
</encode>
</bitset>
<bitset name="#cat5-tex-s2en-bindless" size="4">
<doc>s2en (indirect) / bindless case only has 4b tex</doc>
<override>
<expr>{HAS_TEX}</expr>
<display>
, t#{TEX}
</display>
<field name="TEX" low="0" high="3" type="uint"/>
</override>
<display/>
<assert low="0" high="3">0000</assert>
<encode type="struct ir3_instruction *">
<!--
TODO properly decouple the encoding from ir3 IR in this
case.. the IR has no business knowing how this gets
encoded into "SRC3"..
-->
<map name="TEX">src->cat5.samp >> 4</map>
</encode>
</bitset>
<bitset name="#cat5-type" size="3">
<display/>
<override>
<expr>{HAS_TYPE}</expr>
<display>
({TYPE})
</display>
</override>
<field name="TYPE" low="0" high="2" type="#type"/>
<encode type="struct ir3_instruction *">
<!--
Normally we only encode fields that have visible impact on
the decoded disasm, but the type field is one of those
special exceptions
-->
<map name="TYPE" force="true">src->cat5.type</map>
</encode>
</bitset>
<!--
Helpers/bitsets/etc for dealing with the bindless/indirect case:
-->
<enum name="#cat5-s2en-bindless-desc-mode">
<doc>
We don't actually display this enum, but it is useful to
document the various cases
TODO we should probably have an option for uniforms w/out
display strings, but which have 'C' names that can be used
to generate header that the compiler can use
</doc>
<value val="0" display="CAT5_NONUNIFORM">
<doc>
Use traditional GL binding model, get texture and sampler index
from src3 which is not presumed to be uniform. This is
backwards-compatible with earlier generations, where this field was
always 0 and nonuniform-indexed sampling always worked.
</doc>
</value>
<value val="1" display="CAT5_BINDLESS_A1_UNIFORM">
<doc>
The sampler base comes from the low 3 bits of a1.x, and the sampler
and texture index come from src3 which is presumed to be uniform.
</doc>
</value>
<value val="2" display="CAT5_BINDLESS_NONUNIFORM">
<doc>
The texture and sampler share the same base, and the sampler and
texture index come from src3 which is *not* presumed to be uniform.
</doc>
</value>
<value val="3" display="CAT5_BINDLESS_A1_NONUNIFORM">
<doc>
The sampler base comes from the low 3 bits of a1.x, and the sampler
and texture index come from src3 which is *not* presumed to be
uniform.
</doc>
</value>
<value val="4" display="CAT5_UNIFORM">
<doc>
Use traditional GL binding model, get texture and sampler index
from src3 which is presumed to be uniform.
</doc>
</value>
<value val="5" display="CAT5_BINDLESS_UNIFORM">
<doc>
The texture and sampler share the same base, and the sampler and
texture index come from src3 which is presumed to be uniform.
</doc>
</value>
<value val="6" display="CAT5_BINDLESS_IMM">
<doc>
The texture and sampler share the same base, get sampler index from low
4 bits of src3 and texture index from high 4 bits.
</doc>
</value>
<value val="7" display="CAT5_BINDLESS_A1_IMM">
<doc>
The sampler base comes from the low 3 bits of a1.x, and the texture
index comes from the next 8 bits of a1.x. The sampler index is an
immediate in src3.
</doc>
</value>
</enum>
<!-- Helper to map s2en/bindless DESC_MODE to whether it is an indirect mode -->
<expr name="#cat5-s2enb-is-indirect">
{DESC_MODE} &lt; 6 /* CAT5_BINDLESS_IMM */
</expr>
<!-- Helper to map s2en/bindless DESC_MODE to whether it is a bindless mode -->
<expr name="#cat5-s2enb-is-bindless">
({DESC_MODE} == 1) /* CAT5_BINDLESS_A1_UNIFORM */ ||
({DESC_MODE} == 2) /* CAT5_BINDLESS_NONUNIFORM */ ||
({DESC_MODE} == 3) /* CAT5_BINDLESS_A1_NONUNIFORM */ ||
({DESC_MODE} == 5) /* CAT5_BINDLESS_UNIFORM */ ||
({DESC_MODE} == 6) /* CAT5_BINDLESS_IMM */ ||
({DESC_MODE} == 7) /* CAT5_BINDLESS_A1_IMM */
</expr>
<!-- Helper to map s2en/bindless DESC_MODE to whether it uses a1.x -->
<expr name="#cat5-s2enb-uses_a1">
({DESC_MODE} == 1) /* CAT5_BINDLESS_A1_UNIFORM */ ||
({DESC_MODE} == 3) /* CAT5_BINDLESS_A1_NONUNIFORM */ ||
({DESC_MODE} == 7) /* CAT5_BINDLESS_A1_IMM */
</expr>
<!-- Helper to map s2en/bindless DESC_MODE to whether it is uniform (flow control) mode -->
<expr name="#cat5-s2enb-is-uniform">
({DESC_MODE} == 1) /* CAT5_BINDLESS_A1_UNIFORM */ ||
({DESC_MODE} == 4) /* CAT5_UNIFORM */ ||
({DESC_MODE} == 5) /* CAT5_BINDLESS_UNIFORM */
</expr>
<bitset name="#cat5-src3" size="8">
<doc>bindless/indirect src3, which can either be GPR or samp/tex</doc>
<override expr="#cat5-s2enb-is-indirect">
<display>
, {SRC_HALF}{SRC}
</display>
<field name="SRC" low="0" high="7" type="#reg-gpr"/>
<derived name="SRC_HALF" type="bool" display="h">
<expr>!{BINDLESS}</expr>
</derived>
</override>
<override expr="#cat5-s2enb-uses_a1">
<doc>
In the case that a1.x is used, all 8 bits encode sampler
</doc>
<display>
{SAMP}
</display>
<field name="SAMP" low="0" high="7" type="#cat5-samp-s2en-bindless-a1"/>
</override>
<display>
{SAMP}{TEX}
</display>
<field name="SAMP" low="0" high="3" type="#cat5-samp">
<param name="HAS_SAMP"/>
</field>
<field name="TEX" low="4" high="7" type="#cat5-tex-s2en-bindless">
<param name="HAS_TEX"/>
</field>
<encode type="struct ir3_register *">
<map name="SAMP">s->instr</map>
<map name="TEX">s->instr</map>
<map name="SRC">src</map>
</encode>
</bitset>
</isa>

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<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright © 2020 Google, Inc.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
-->
<isa>
<!--
Cat6 Instructions: load/store/atomic instructions
-->
<bitset name="#instruction-cat6" extends="#instruction">
<field pos="59" name="JP" type="bool" display="(jp)"/>
<field pos="60" name="SY" type="bool" display="(sy)"/>
<pattern low="61" high="63">110</pattern> <!-- cat6 -->
<encode>
<map name="TYPE">src->cat6.type</map>
</encode>
</bitset>
<bitset name="#instruction-cat6-a3xx" extends="#instruction-cat6">
<field name="TYPE" low="49" high="51" type="#type"/>
<!-- TODO pull more fields up to this level, when they are common across sub-encodings -->
</bitset>
<bitset name="ldg" extends="#instruction-cat6-a3xx">
<doc>
LoaD Global
</doc>
<display>
{SY}{JP}{NAME}.{TYPE} {DST}, g[{SRC1}+{SRC2}], {SIZE}
</display>
<override>
<display>
{SY}{JP}{NAME}.{TYPE} {DST}, g[{SRC1}{OFF}], {SIZE}
</display>
<expr>!{SRC2_REG}</expr>
<field low="1" high="13" name="OFF" type="offset"/>
</override>
<pattern pos="0" >1</pattern>
<field low="1" high="8" name="SRC2" type="#reg-gpr"/>
<assert low="9" high="13">00000</assert>
<field low="14" high="21" name="SRC1" type="#reg-gpr"/>
<field pos="22" name="SRC2_REG" type="bool"/>
<pattern pos="23" >1</pattern>
<field low="24" high="31" name="SIZE" type="uint"/>
<field low="32" high="39" name="DST" type="#reg-gpr"/>
<pattern low="40" high="48">xxxxxxxxx</pattern>
<pattern low="52" high="53">00</pattern>
<pattern low="54" high="58">00000</pattern> <!-- OPC -->
<encode>
<map name="SRC2_REG">!(src->regs[2]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC2">src->regs[2]</map>
<map name="OFF">src->regs[2]->iim_val</map>
<map name="SIZE">src->regs[3]->uim_val</map>
</encode>
</bitset>
<bitset name="stg" extends="#instruction-cat6-a3xx">
<doc>
STore Global
</doc>
<display>
{SY}{JP}{NAME}.{TYPE} g[{SRC1}+{SRC2}], {SRC3}, {SIZE}
</display>
<override>
<display>
{SY}{JP}{NAME}.{TYPE} g[{SRC1}{OFF}], {SRC3}, {SIZE}
</display>
<expr>!{G}</expr>
<derived name="OFF" width="13" type="offset">
<expr>({OFF_HI} &lt;&lt; 8) | {OFF_LO}</expr>
</derived>
<field low="9" high="13" name="OFF_HI" type="uint"/>
<field low="32" high="39" name="OFF_LO" type="uint"/>
</override>
<pattern pos="0" >x</pattern>
<field low="1" high="8" name="SRC3" type="#reg-gpr"/>
<assert low="9" high="13">00000</assert> <!-- OFF_HI -->
<pattern low="14" high="21">xxxxxxxx</pattern>
<pattern low="22" high="23">1x</pattern>
<field low="24" high="31" name="SIZE" type="uint"/>
<field low="32" high="39" name="SRC2" type="#reg-gpr"/>
<field pos="40" name="DST_OFF" type="bool"/>
<field low="41" high="48" name="SRC1" type="#reg-gpr"/>
<field pos="52" name="G" type="bool"/>
<pattern pos="53" >x</pattern>
<pattern low="54" high="58">00011</pattern> <!-- OPC -->
<encode>
<map name="SIZE">src->regs[3]->uim_val</map>
<map name="SRC2">src->regs[4]</map>
<map name="DST_OFF" force="true">1</map>
<map name="SRC3">src->regs[2]</map>
<map name="G">(src->flags &amp; IR3_INSTR_G) &amp;&amp; !(src->regs[4]->flags &amp; IR3_REG_IMMED)</map>
<map name="OFF_LO">src->cat6.dst_offset</map>
<map name="OFF_HI">src->cat6.dst_offset >> 8</map>
</encode>
</bitset>
<bitset name="#instruction-cat6-a3xx-ld" extends="#instruction-cat6-a3xx">
<pattern pos="0" >1</pattern>
<field low="1" high="13" name="OFF" type="offset"/>
<field low="14" high="21" name="SRC" type="#reg-gpr"/>
<pattern pos="22" >x</pattern>
<pattern pos="23" >1</pattern>
<field low="24" high="31" name="SIZE" type="uint"/>
<field low="32" high="39" name="DST" type="#reg-gpr"/>
<pattern low="40" high="48">xxxxxxxxx</pattern>
<pattern low="52" high="53">xx</pattern>
<encode>
<map name="OFF">src->regs[2]->uim_val</map>
<map name="SRC">src->regs[1]</map>
<map name="SIZE">src->regs[3]->uim_val</map>
</encode>
</bitset>
<bitset name="ldl" extends="#instruction-cat6-a3xx-ld">
<doc>
LoaD Local
</doc>
<display>
{SY}{JP}{NAME}.{TYPE} {DST}, l[{SRC}{OFF}], {SIZE}
</display>
<pattern low="54" high="58">00001</pattern> <!-- OPC -->
</bitset>
<bitset name="ldp" extends="#instruction-cat6-a3xx-ld">
<doc>
LoaD Private
</doc>
<display>
{SY}{JP}{NAME}.{TYPE} {DST}, p[{SRC}{OFF}], {SIZE}
</display>
<pattern low="54" high="58">00010</pattern> <!-- OPC -->
</bitset>
<bitset name="ldlw" extends="#instruction-cat6-a3xx-ld">
<doc>
LoaD Local (variant used for passing data between geom stages)
</doc>
<display>
{SY}{JP}{NAME}.{TYPE} {DST}, l[{SRC}{OFF}], {SIZE}
</display>
<pattern low="54" high="58">01010</pattern> <!-- OPC -->
</bitset>
<bitset name="ldlv" extends="#instruction-cat6-a3xx">
<doc>
LoaD Local Varying - read directly from varying storage
</doc>
<display>
{SY}{JP}{NAME}.{TYPE} {DST}, l[{OFF}], {SIZE}
</display>
<pattern pos="0" >0</pattern>
<field low="1" high="13" name="OFF" type="uint"/>
<pattern low="14" high="21">xxxxxxxx</pattern> <!-- SRC -->
<pattern low="22" high="23">11</pattern>
<field low="24" high="31" name="SIZE" type="uint"/>
<field low="32" high="39" name="DST" type="#reg-gpr"/>
<pattern low="40" high="48">xxxxxxxxx</pattern>
<pattern low="52" high="53">xx</pattern>
<pattern low="54" high="58">11111</pattern> <!-- OPC -->
<encode>
<map name="SIZE">src->regs[2]->uim_val</map>
<map name="OFF">src->regs[1]->uim_val</map>
</encode>
</bitset>
<bitset name="#instruction-cat6-a3xx-st" extends="#instruction-cat6-a3xx">
<derived name="OFF" width="13" type="offset">
<expr>({OFF_HI} &lt;&lt; 8) | {OFF_LO}</expr>
</derived>
<field low="1" high="8" name="SRC" type="#reg-gpr"/>
<field low="9" high="13" name="OFF_HI" type="uint"/>
<pattern low="14" high="22">xxxxxxxxx</pattern>
<pattern pos="23" >1</pattern>
<field low="24" high="31" name="SIZE" type="uint"/>
<field low="32" high="39" name="OFF_LO" type="uint"/>
<pattern pos="40" >1</pattern>
<field low="41" high="48" name="DST" type="#reg-gpr"/>
<pattern low="52" high="53">xx</pattern>
<encode>
<!--
TODO get rid of dst_offset and use a normal (potentially
immed) reg.. for now match the existing ir3 until we can
drop the old packed-struct encoding
-->
<map name="OFF_HI">src->cat6.dst_offset >> 8</map>
<map name="OFF_LO">src->cat6.dst_offset &amp; 0xff</map>
<map name="SRC">src->regs[2]</map>
<map name="DST">src->regs[1]</map>"
<map name="SIZE">src->regs[3]->uim_val</map>
</encode>
</bitset>
<bitset name="stl" extends="#instruction-cat6-a3xx-st">
<doc>
STore Local
</doc>
<display>
{SY}{JP}{NAME}.{TYPE} l[{DST}{OFF}], {SRC}, {SIZE}
</display>
<pattern pos="0" >x</pattern>
<pattern low="54" high="58">00100</pattern> <!-- OPC -->
</bitset>
<bitset name="stp" extends="#instruction-cat6-a3xx-st">
<doc>
STore Private
</doc>
<display>
{SY}{JP}{NAME}.{TYPE} p[{DST}{OFF}], {SRC}, {SIZE}
</display>
<pattern pos="0" >0</pattern> <!-- SRC_OFF -->
<pattern low="54" high="58">00101</pattern> <!-- OPC -->
</bitset>
<bitset name="stlw" extends="#instruction-cat6-a3xx-st">
<doc>
STore Local (variant used for passing data between geom stages)
</doc>
<display>
{SY}{JP}{NAME}.{TYPE} l[{DST}{OFF}], {SRC}, {SIZE}
</display>
<pattern pos="0" >x</pattern>
<pattern low="54" high="58">01011</pattern> <!-- OPC -->
</bitset>
<bitset name="stc" extends="#instruction-cat6-a3xx">
<doc>
STore Const - used for shader prolog (between shps and shpe)
to store "uniform folded" values into CONST file
NOTE: TYPE field actually seems to be set to different
values (ie f32 vs u32), but I *think* it does not matter.
(There is SP_MODE_CONTROL.CONSTANT_DEMOTION_ENABLE, but
I think float results are already converted to 32b)
NOTE: this could be the "old" encoding, although it
would conflict with stgb from earlier gens
</doc>
<display>
{SY}{JP}{NAME} c[{DST}], {SRC}, {SIZE}
</display>
<gen min="600"/>
<pattern pos="0" >x</pattern>
<field low="1" high="8" name="SRC" type="#reg-gpr"/>
<pattern low="9" high="22">xxxxxxxxxxxxxx</pattern>
<pattern pos="23" >1</pattern>
<field low="24" high="26" name="SIZE" type="uint"/>
<pattern low="27" high="31">xxxxx</pattern>
<field low="32" high="39" name="DST" type="uint"/>
<pattern low="40" high="48">xxxxxxxxx</pattern>
<pattern low="52" high="53">xx</pattern>
<pattern low="54" high="58">11100</pattern> <!-- OPC -->
<encode>
<map name="DST">src->regs[1]->uim_val</map>
<map name="SRC">src->regs[2]</map>
</encode>
</bitset>
<bitset name="resinfo" extends="#instruction-cat6-a3xx">
<display>
{SY}{JP}{NAME}.{TYPE}.{D}d {DST}, g[{SSBO}]
</display>
<derived name="D" expr="#cat6-d" type="uint"/>
<pattern pos="0" >x</pattern>
<pattern low="1" high="8" >xxxxxxxx</pattern> <!-- SRC3 -->
<field low="9" high="10" name="D_MINUS_ONE" type="uint"/>
<pattern pos="11" >x</pattern> <!-- TYPED -->
<pattern low="12" high="13">xx</pattern> <!-- TYPE_SIZE -->
<pattern low="14" high="21">xxxxxxxx</pattern> <!-- SRC1 -->
<pattern pos="22" >x</pattern> <!-- SRC1_IM -->
<pattern pos="23" >x</pattern> <!-- SRC2_IM -->
<pattern low="24" high="31">xxxxxxxx</pattern> <!-- SRC2 -->
<field low="32" high="39" name="DST" type="#reg-gpr"/>
<pattern pos="40" >0</pattern>
<field low="41" high="48" name="SSBO" type="#cat6-src"> <!-- SSBO/image binding point -->
<param name="SSBO_IM" as="SRC_IM"/>
</field>
<pattern pos="52" >x</pattern> <!-- G -->
<field pos="53" name="SSBO_IM" type="bool"/>
<pattern low="54" high="58">01111</pattern> <!-- OPC -->
<encode>
<map name="D_MINUS_ONE">src->cat6.d - 1</map>
<map name="SSBO">src->regs[1]</map>
<map name="SSBO_IM">!!(src->regs[1]->flags &amp; IR3_REG_IMMED)</map>
</encode>
</bitset>
<!-- ldgb.untyped.4d.f32.4 r0.x, g[0], r0.x, r1.z -->
<bitset name="ldgb" extends="#instruction-cat6-a3xx">
<display>
{SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE} {DST}, g[{SSBO}], {SRC1}, {SRC2}
</display>
<gen max="599"/>
<derived name="D" expr="#cat6-d" type="uint"/>
<derived name="TYPE_SIZE" expr="#cat6-type-size" type="uint"/>
<pattern pos="0" >x</pattern>
<pattern low="1" high="8" >xxxxxxxx</pattern> <!-- SRC3 -->
<field low="9" high="10" name="D_MINUS_ONE" type="uint"/>
<field pos="11" name="TYPED" type="#cat6-typed"/>
<field low="12" high="13" name="TYPE_SIZE_MINUS_ONE" type="uint"/>
<field low="14" high="21" name="SRC1" type="#cat6-src">
<param name="SRC1_IM" as="SRC_IM"/>
</field>
<field pos="22" name="SRC1_IM" type="bool"/>
<field pos="23" name="SRC2_IM" type="bool"/>
<field low="24" high="31" name="SRC2" type="#cat6-src">
<param name="SRC2_IM" as="SRC_IM"/>
</field>
<field low="32" high="39" name="DST" type="#reg-gpr"/>
<pattern pos="40" >0</pattern>
<field low="41" high="48" name="SSBO" type="#cat6-src"> <!-- SSBO/image binding point -->
<param name="SSBO_IM" as="SRC_IM"/>
</field>
<pattern pos="52" >x</pattern> <!-- G -->
<field pos="53" name="SSBO_IM" type="bool"/>
<pattern low="54" high="58">11011</pattern> <!-- OPC -->
<encode>
<map name="D_MINUS_ONE">src->cat6.d - 1</map>
<map name="TYPED">src</map>
<map name="TYPE_SIZE_MINUS_ONE">src->cat6.iim_val - 1</map>
<map name="SSBO">src->regs[1]</map>
<map name="SSBO_IM">!!(src->regs[1]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC1">src->regs[2]</map>
<map name="SRC1_IM">!!(src->regs[2]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC2">src->regs[3]</map>
<map name="SRC2_IM">!!(src->regs[3]->flags &amp; IR3_REG_IMMED)</map>
</encode>
</bitset>
<bitset name="#instruction-cat6-a3xx-ibo" extends="#instruction-cat6-a3xx">
<display>
{SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE} g[{SSBO}], {SRC1}, {SRC2}, {SRC3}
</display>
<gen max="599"/>
<derived name="D" expr="#cat6-d" type="uint"/>
<derived name="TYPE_SIZE" expr="#cat6-type-size" type="uint"/>
<pattern pos="0" >1</pattern>
<field low="1" high="8" name="SRC1" type="#reg-gpr"/>
<field low="9" high="10" name="D_MINUS_ONE" type="uint"/>
<field pos="11" name="TYPED" type="#cat6-typed"/>
<field low="12" high="13" name="TYPE_SIZE_MINUS_ONE" type="uint"/>
<pattern low="14" high="22">xxxxxxxxx</pattern>
<field pos="23" name="SRC2_IM" type="bool"/>
<field low="24" high="31" name="SRC2" type="#cat6-src">
<param name="SRC2_IM" as="SRC_IM"/>
</field>
<field low="32" high="39" name="SRC3" type="#cat6-src">
<param name="SRC3_IM" as="SRC_IM"/>
</field>
<field pos="40" name="SRC3_IM" type="bool"/>
<field low="41" high="48" name="SSBO" type="#cat6-src"> <!-- SSBO/image binding point -->
<param name="SSBO_IM" as="SRC_IM"/>
</field>
<pattern pos="52" >x</pattern> <!-- G -->
<field pos="53" name="SSBO_IM" type="bool"/>
<encode>
<map name="D_MINUS_ONE">src->cat6.d - 1</map>
<map name="TYPED">src</map>
<map name="TYPE_SIZE_MINUS_ONE">src->cat6.iim_val - 1</map>
<map name="SSBO">src->regs[1]</map>
<map name="SSBO_IM">!!(src->regs[1]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC1">src->regs[2]</map>
<map name="SRC1_IM">!!(src->regs[2]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC2">src->regs[3]</map>
<map name="SRC2_IM">!!(src->regs[3]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC3">src->regs[4]</map>
<map name="SRC3_IM">!!(src->regs[4]->flags &amp; IR3_REG_IMMED)</map>
</encode>
</bitset>
<bitset name="stgb" extends="#instruction-cat6-a3xx-ibo">
<pattern low="54" high="58">11100</pattern> <!-- OPC -->
</bitset>
<bitset name="stib" extends="#instruction-cat6-a3xx-ibo">
<pattern low="54" high="58">11101</pattern> <!-- OPC -->
</bitset>
<bitset name="#instruction-cat6-a3xx-atomic" extends="#instruction-cat6-a3xx">
<doc>
Base for atomic instructions (I think mostly a4xx+, as
a3xx didn't have real image/ssbo.. it was all just global).
Still used as of a6xx for local.
NOTE that existing disasm and asm parser expect atomic inc/dec
to still have an extra src. For now, match that.
</doc>
<override expr="#cat6-global">
<display>
{SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE}.g {DST}, g[{SSBO}], {SRC1}, {SRC2}, {SRC3}
</display>
<field low="1" high="8" name="SRC3" type="#reg-gpr"/>
<field low="41" high="48" name="SSBO" type="#cat6-src"> <!-- SSBO/image binding point -->
<param name="SSBO_IM" as="SRC_IM"/>
</field>
<field pos="53" name="SSBO_IM" type="bool"/>
</override>
<display>
{SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE}.l {DST}, l[{SRC1}], {SRC2}
</display>
<derived name="D" expr="#cat6-d" type="uint"/>
<derived name="TYPE_SIZE" expr="#cat6-type-size" type="uint"/>
<pattern pos="0" >1</pattern>
<pattern low="1" high="8" >xxxxxxxx</pattern> <!-- SRC3 -->
<field low="9" high="10" name="D_MINUS_ONE" type="uint"/>
<field pos="11" name="TYPED" type="#cat6-typed"/>
<field low="12" high="13" name="TYPE_SIZE_MINUS_ONE" type="uint"/>
<field low="14" high="21" name="SRC1" type="#cat6-src">
<param name="SRC1_IM" as="SRC_IM"/>
</field>
<field pos="22" name="SRC1_IM" type="bool"/>
<field pos="23" name="SRC2_IM" type="bool"/>
<field low="24" high="31" name="SRC2" type="#cat6-src">
<param name="SRC2_IM" as="SRC_IM"/>
</field>
<field low="32" high="39" name="DST" type="#reg-gpr"/>
<pattern pos="40" >x</pattern>
<assert low="41" high="48">00000000</assert> <!-- SSBO/image binding point -->
<field pos="52" name="G" type="bool"/>
<assert pos="53" >0</assert> <!-- SSBO_IM -->
<encode>
<map name="G">!!(src->flags &amp; IR3_INSTR_G)</map>
<map name="TYPED">src</map>
<map name="D_MINUS_ONE">src->cat6.d - 1</map>
<map name="TYPE_SIZE_MINUS_ONE">src->cat6.iim_val - 1</map>
<map name="SSBO">src->regs[1]</map>
<map name="SSBO_IM">!!(src->regs[1]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC1">extract_cat6_SRC(src, 1)</map>
<map name="SRC1_IM">!!(extract_cat6_SRC(src, 1)->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC2">extract_cat6_SRC(src, 2)</map>
<map name="SRC2_IM">!!(extract_cat6_SRC(src, 2)->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC3">extract_cat6_SRC(src, 3)</map>
<map name="SRC3_IM">!!(extract_cat6_SRC(src, 3)->flags &amp; IR3_REG_IMMED)</map>
</encode>
</bitset>
<bitset name="#instruction-cat6-a3xx-atomic-1src" extends="#instruction-cat6-a3xx-atomic">
<!-- TODO when asm parser is updated, shift display templates, etc, here -->
</bitset>
<bitset name="#instruction-cat6-a3xx-atomic-2src" extends="#instruction-cat6-a3xx-atomic">
<!-- TODO when asm parser is updated, shift display templates, etc, here -->
</bitset>
<bitset name="atomic.add" extends="#instruction-cat6-a3xx-atomic-2src">
<pattern low="54" high="58">10000</pattern> <!-- OPC -->
</bitset>
<bitset name="atomic.sub" extends="#instruction-cat6-a3xx-atomic-2src">
<pattern low="54" high="58">10001</pattern> <!-- OPC -->
</bitset>
<bitset name="atomic.xchg" extends="#instruction-cat6-a3xx-atomic-2src">
<pattern low="54" high="58">10010</pattern> <!-- OPC -->
</bitset>
<bitset name="atomic.inc" extends="#instruction-cat6-a3xx-atomic-1src">
<pattern low="54" high="58">10011</pattern> <!-- OPC -->
</bitset>
<bitset name="atomic.dec" extends="#instruction-cat6-a3xx-atomic-1src">
<pattern low="54" high="58">10100</pattern> <!-- OPC -->
</bitset>
<bitset name="atomic.cmpxchg" extends="#instruction-cat6-a3xx-atomic-2src">
<pattern low="54" high="58">10101</pattern> <!-- OPC -->
</bitset>
<bitset name="atomic.min" extends="#instruction-cat6-a3xx-atomic-2src">
<pattern low="54" high="58">10110</pattern> <!-- OPC -->
</bitset>
<bitset name="atomic.max" extends="#instruction-cat6-a3xx-atomic-2src">
<pattern low="54" high="58">10111</pattern> <!-- OPC -->
</bitset>
<bitset name="atomic.and" extends="#instruction-cat6-a3xx-atomic-2src">
<pattern low="54" high="58">11000</pattern> <!-- OPC -->
</bitset>
<bitset name="atomic.or" extends="#instruction-cat6-a3xx-atomic-2src">
<pattern low="54" high="58">11001</pattern> <!-- OPC -->
</bitset>
<bitset name="atomic.xor" extends="#instruction-cat6-a3xx-atomic-2src">
<pattern low="54" high="58">11010</pattern> <!-- OPC -->
</bitset>
<!--
New a6xx+ encodings for potentially bindless image/ssbo:
-->
<bitset name="#instruction-cat6-a6xx" extends="#instruction-cat6">
<doc>
Base for new instruction encoding that started being used
with a6xx for instructions supporting bindless mode.
</doc>
<gen min="600"/>
<derived name="TYPE_SIZE" expr="#cat6-type-size" type="uint"/>
<field low="1" high="3" name="BASE" type="#cat6-base">
<param name="BINDLESS"/>
</field>
<pattern low="4" high="5" >00</pattern>
<field low="6" high="7" name="MODE" type="#cat6-src-mode"/>
<field pos="8" name="BINDLESS" type="bool"/>
<field low="12" high="13" name="TYPE_SIZE_MINUS_ONE" type="uint"/>
<pattern pos="40" >0</pattern>
<pattern low="54" high="58">00000</pattern>
<encode>
<map name="MODE">extract_cat6_DESC_MODE(src)</map>
<map name="TYPE_SIZE_MINUS_ONE">src->cat6.iim_val - 1</map>
<map name="BINDLESS">!!(src->flags &amp; IR3_INSTR_B)</map>
<map name="BASE">src</map>
</encode>
</bitset>
<bitset name="ldc" extends="#instruction-cat6-a6xx">
<doc>
LoaD Constant - UBO load
</doc>
<override>
<!-- TODO.. wtf? -->
<expr>{K}</expr>
<display>
{SY}{JP}{NAME}.{TYPE_SIZE}.k.{MODE}{BASE} c[a1.x], {SRC1}, {SRC2}
</display>
<field low="32" high="39" name="TYPE_SIZE_MINUS_ONE" type="uint"/>
</override>
<!--
TODO are these *really* all bindless? Or does that bit have a different
meaning? Maybe I don't have enough ldc examples from deqp-glesN
-->
<display>
{SY}{JP}{NAME}.offset{OFFSET}.{TYPE_SIZE}.{MODE}{BASE} {DST}, {SRC1}, {SRC2}
</display>
<pattern pos="0" >x</pattern>
<field low="9" high="10" name="OFFSET" type="uint"/> <!-- D_MINUS_ONE -->
<pattern pos="11" >x</pattern> <!-- TYPED -->
<pattern low="14" high="19">011110</pattern> <!-- OPC -->
<pattern low="20" high="22">1xx</pattern>
<field pos="23" name="SRC1_IM" type="bool"/>
<derived name="SRC2_IM" expr="#cat6-direct" type="bool"/>
<field low="41" high="48" name="SRC2" type="#cat6-src">
<param name="SRC2_IM" as="SRC_IM"/>
</field>
<field low="24" high="31" name="SRC1" type="#cat6-src">
<param name="SRC1_IM" as="SRC_IM"/>
</field>
<field low="32" high="39" name="DST" type="#reg-gpr"/>
<pattern low="49" high="51">x11</pattern> <!-- TYPE -->
<field pos="52" name="K" type="bool"/>
<pattern pos="53" >1</pattern>
<encode>
<map name="K">0</map> <!-- TODO.. once we figure out what this is -->
<map name="SRC1_IM">!!(src->regs[2]->flags &amp; IR3_REG_IMMED)</map>
<map name="OFFSET">src->cat6.d</map>
<map name="SRC1">src->regs[2]</map>
<map name="SRC2">src->regs[1]</map>
</encode>
</bitset>
<bitset name="getspid" extends="#instruction-cat6-a6xx">
<doc>
GET Shader Processor ID?
</doc>
<display>
{SY}{JP}{NAME}.{TYPE} {DST}
</display>
<pattern pos="0" >0</pattern>
<pattern low="9" high="10">xx</pattern> <!-- D_MINUS_ONE -->
<pattern pos="11" >x</pattern> <!-- TYPED -->
<pattern low="14" high="19">100100</pattern> <!-- OPC -->
<pattern low="20" high="23">x1xx</pattern>
<pattern low="24" high="31">xxxxxxxx</pattern> <!-- SRC2 -->
<field low="32" high="39" name="DST" type="#reg-gpr"/>
<pattern low="41" high="48">xxxxxxxx</pattern> <!-- SSBO/image binding point -->
<field low="49" high="51" name="TYPE" type="#type"/>
<pattern low="52" high="53">1x</pattern>
</bitset>
<bitset name="getwid" extends="#instruction-cat6-a6xx">
<doc>
GET Wavefront ID
</doc>
<display>
{SY}{JP}{NAME}.{TYPE} {DST}
</display>
<pattern pos="0" >0</pattern>
<pattern low="9" high="10">xx</pattern> <!-- D_MINUS_ONE -->
<pattern pos="11" >x</pattern> <!-- TYPED -->
<pattern low="14" high="19">100101</pattern> <!-- OPC -->
<pattern low="20" high="23">x1xx</pattern>
<pattern low="24" high="31">xxxxxxxx</pattern> <!-- SRC2 -->
<field low="32" high="39" name="DST" type="#reg-gpr"/>
<pattern low="41" high="48">xxxxxxxx</pattern> <!-- SSBO/image binding point -->
<field low="49" high="51" name="TYPE" type="#type"/>
<pattern low="52" high="53">1x</pattern>
</bitset>
<bitset name="resinfo.b" extends="#instruction-cat6-a6xx">
<doc>
RESourceINFO - returns image/ssbo dimensions (3 components)
</doc>
<display>
{SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE}.{MODE}{BASE} {DST}, {SSBO}
</display>
<derived name="D" expr="#cat6-d" type="uint"/>
<derived name="TRUE" expr="#true" type="bool"/>
<pattern pos="0" >0</pattern>
<field low="9" high="10" name="D_MINUS_ONE" type="uint"/>
<field pos="11" name="TYPED" type="#cat6-typed"/>
<pattern low="14" high="19">001111</pattern> <!-- OPC -->
<pattern low="20" high="23">0110</pattern>
<pattern low="24" high="31">xxxxxxxx</pattern> <!-- SRC2 -->
<field low="32" high="39" name="DST" type="#reg-gpr"/>
<field low="41" high="48" name="SSBO" type="#cat6-src"> <!-- SSBO/image binding point -->
<param name="TRUE" as="SRC_IM"/>
</field>
<field low="49" high="51" name="TYPE" type="#type"/>
<pattern low="52" high="53">1x</pattern>
<encode>
<map name="D_MINUS_ONE">src->cat6.d - 1</map>
<map name="TYPED">src</map>
<map name="SSBO">src->regs[1]</map>
<map name="SRC1">src->regs[2]</map>
</encode>
</bitset>
<bitset name="#instruction-cat6-a6xx-ibo" extends="#instruction-cat6-a6xx">
<doc>
IBO (ie. Image/SSBO) instructions
</doc>
<display>
{SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE}.{MODE}{BASE} {SRC1}, {SRC2}, {SSBO}
</display>
<derived name="D" expr="#cat6-d" type="uint"/>
<derived name="TRUE" expr="#true" type="bool"/>
<field low="9" high="10" name="D_MINUS_ONE" type="uint"/>
<field pos="11" name="TYPED" type="#cat6-typed"/>
<pattern low="20" high="23">0110</pattern>
<field low="24" high="31" name="SRC2" type="#reg-gpr"/>
<field low="32" high="39" name="SRC1" type="#reg-gpr"/>
<field low="41" high="48" name="SSBO" type="#cat6-src"> <!-- SSBO/image binding point -->
<param name="SSBO_IM" as="SRC_IM"/>
</field>
<derived name="SSBO_IM" expr="#cat6-direct" type="bool"/>
<field low="49" high="51" name="TYPE" type="#type"/>
<encode>
<map name="TYPED">src</map>
<map name="D_MINUS_ONE">src->cat6.d - 1</map>
<map name="SSBO">src->regs[1]</map>
<map name="SRC1">src->regs[3]</map>
<map name="SRC2">src->regs[2]</map>
</encode>
</bitset>
<bitset name="stib.b" extends="#instruction-cat6-a6xx-ibo">
<doc>
STore IBo
</doc>
<pattern pos="0" >0</pattern>
<pattern low="14" high="19">011101</pattern> <!-- OPC -->
<pattern low="52" high="53">10</pattern>
</bitset>
<bitset name="ldib.b" extends="#instruction-cat6-a6xx-ibo">
<doc>
LoaD IBo
</doc>
<pattern pos="0" >x</pattern> <!-- blob seems to set randomly? -->
<pattern low="14" high="19">000110</pattern> <!-- OPC -->
<pattern low="52" high="53">10</pattern>
<encode>
<map name="SRC1">src->regs[0]</map>
</encode>
</bitset>
<bitset name="atomic.b.add" extends="#instruction-cat6-a6xx-ibo">
<pattern pos="0" >1</pattern>
<pattern low="14" high="19">010000</pattern> <!-- OPC -->
<pattern low="52" high="53">11</pattern>
</bitset>
<bitset name="atomic.b.sub" extends="#instruction-cat6-a6xx-ibo">
<pattern pos="0" >1</pattern>
<pattern low="14" high="19">010001</pattern> <!-- OPC -->
<pattern low="52" high="53">11</pattern>
</bitset>
<bitset name="atomic.b.xchg" extends="#instruction-cat6-a6xx-ibo">
<pattern pos="0" >1</pattern>
<pattern low="14" high="19">010010</pattern> <!-- OPC -->
<pattern low="52" high="53">11</pattern>
</bitset>
<!-- inc/dec? -->
<bitset name="atomic.b.cmpxchg" extends="#instruction-cat6-a6xx-ibo">
<pattern pos="0" >1</pattern>
<pattern low="14" high="19">010101</pattern> <!-- OPC -->
<pattern low="52" high="53">11</pattern>
</bitset>
<bitset name="atomic.b.min" extends="#instruction-cat6-a6xx-ibo">
<pattern pos="0" >1</pattern>
<pattern low="14" high="19">010110</pattern> <!-- OPC -->
<pattern low="52" high="53">11</pattern>
</bitset>
<bitset name="atomic.b.max" extends="#instruction-cat6-a6xx-ibo">
<pattern pos="0" >1</pattern>
<pattern low="14" high="19">010111</pattern> <!-- OPC -->
<pattern low="52" high="53">11</pattern>
</bitset>
<bitset name="atomic.b.and" extends="#instruction-cat6-a6xx-ibo">
<pattern pos="0" >1</pattern>
<pattern low="14" high="19">011000</pattern> <!-- OPC -->
<pattern low="52" high="53">11</pattern>
</bitset>
<bitset name="atomic.b.or" extends="#instruction-cat6-a6xx-ibo">
<pattern pos="0" >1</pattern>
<pattern low="14" high="19">011001</pattern> <!-- OPC -->
<pattern low="52" high="53">11</pattern>
</bitset>
<bitset name="atomic.b.xor" extends="#instruction-cat6-a6xx-ibo">
<pattern pos="0" >1</pattern>
<pattern low="14" high="19">011010</pattern> <!-- OPC -->
<pattern low="52" high="53">11</pattern>
</bitset>
<expr name="#cat6-d">
{D_MINUS_ONE} + 1
</expr>
<expr name="#cat6-type-size">
{TYPE_SIZE_MINUS_ONE} + 1
</expr>
<!-- Image/SSBO (ie. not local) -->
<expr name="#cat6-global">
{G}
</expr>
<bitset name="#cat6-typed" size="1">
<override>
<expr>{TYPED}</expr>
<display>
typed
</display>
</override>
<display>
untyped
</display>
<field name="TYPED" pos="0" type="bool"/>
<encode type="struct ir3_instruction *">
<map name="TYPED" force="true">src->cat6.typed</map>
</encode>
</bitset>
<bitset name="#cat6-base" size="3">
<override>
<expr>{BINDLESS}</expr>
<display>
.base{BASE}
</display>
</override>
<display/>
<field name="BASE" low="0" high="2" type="uint"/>
<encode type="struct ir3_instruction *">
<map name="BASE">src->cat6.base</map>
</encode>
</bitset>
<bitset name="#cat6-src" size="8">
<doc>
Source value that can be either immed or gpr
</doc>
<override>
<expr>{SRC_IM}</expr>
<display>
{IMMED}
</display>
<field name="IMMED" low="0" high="7" type="int"/>
</override>
<display>
r{GPR}.{SWIZ}
</display>
<field name="SWIZ" low="0" high="1" type="#swiz"/>
<field name="GPR" low="2" high="7" type="uint"/>
<encode type="struct ir3_register *">
<map name="GPR">src->num >> 2</map>
<map name="SWIZ">src->num &amp; 0x3</map>
<map name="IMMED">src->iim_val</map>
</encode>
</bitset>
<expr name="#cat6-direct">
{MODE} == 0
</expr>
<enum name="#cat6-src-mode">
<doc>
Source mode for "new" a6xx+ instruction encodings
</doc>
<value val="0" display="imm">
<doc>
Immediate index.
</doc>
</value>
<value val="1" display="uniform">
<doc>
Index from a uniform register (ie. does not depend on flow control)
</doc>
</value>
<value val="2" display="nonuniform">
<doc>
Index from a non-uniform register (ie. potentially depends on flow control)
</doc>
</value>
</enum>
</isa>

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src/freedreno/isa/ir3-cat7.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright © 2020 Google, Inc.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
-->
<isa>
<!--
Cat7 Instructions: barrier instructions
-->
<bitset name="#instruction-cat7" extends="#instruction">
<display>
{SY}{JP}{NAME}{G}{L}{R}{W}
</display>
<pattern low="0" high="31">xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx</pattern>
<pattern low="32" high="43">xxxxxxxxxxxx</pattern>
<pattern pos="44" >x</pattern> <!-- possilby (ss) ? -->
<pattern low="45" high="50">x1xxxx</pattern>
<field pos="51" name="W" type="bool" display=".w" /> <!-- write -->
<field pos="52" name="R" type="bool" display=".r" /> <!-- read -->
<field pos="53" name="L" type="bool" display=".l" /> <!-- local -->
<field pos="54" name="G" type="bool" display=".g" /> <!-- global -->
<!-- 4b OPC -->
<field pos="59" name="JP" type="bool" display="(jp)"/>
<field pos="60" name="SY" type="bool" display="(sy)"/>
<pattern low="61" high="63">111</pattern> <!-- cat7 -->
<encode>
<map name="W">src->cat7.w</map>
<map name="R">src->cat7.r</map>
<map name="L">src->cat7.l</map>
<map name="G">src->cat7.g</map>
</encode>
</bitset>
<bitset name="bar" extends="#instruction-cat7">
<pattern low="55" high="58">0000</pattern>
</bitset>
<bitset name="fence" extends="#instruction-cat7">
<pattern low="55" high="58">0001</pattern>
</bitset>
</isa>

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<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright © 2020 Google, Inc.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
-->
<isa>
<!--
Helpers for cat2/cat3 nop encoding, which re-uses the SRC1_R/SRC2_R
fields to encode a # of nop delay slots following the instruction.
-->
<expr name="#cat2-cat3-nop-encoding">
(({SRC1_R} != 0) || ({SRC2_R} != 0)) &amp;&amp; ({REPEAT} == 0)
</expr>
<expr name="#cat2-cat3-nop-value">
{SRC1_R} | ({SRC2_R} &lt;&lt; 1)
</expr>
<!--
Source/Dest gpr encoding. In the gpr case, this handles the special
cases (p0.x/a0.x)
-->
<expr name="#reg-gpr-a0">
{GPR} == 61 /* a0.* */
</expr>
<expr name="#reg-gpr-p0">
{GPR} == 62 /* p0.x */
</expr>
<bitset name="#reg-gpr" size="8">
<override expr="#reg-gpr-a0">
<display>
a0.{SWIZ}
</display>
<assert low="2" high="7">111101</assert>
</override>
<override expr="#reg-gpr-p0">
<display>
p0.{SWIZ}
</display>
<assert low="2" high="7">111110</assert>
</override>
<display>
r{GPR}.{SWIZ}
</display>
<field name="SWIZ" low="0" high="1" type="#swiz"/>
<field name="GPR" low="2" high="7" type="uint"/>
<encode type="struct ir3_register *">
<map name="GPR">src->num >> 2</map>
<map name="SWIZ">src->num &amp; 0x3</map>
</encode>
</bitset>
<bitset name="#reg-const" size="11">
<display>
c{CONST}.{SWIZ}
</display>
<field name="SWIZ" low="0" high="1" type="#swiz"/>
<field name="CONST" low="2" high="10" type="uint"/>
<encode type="struct ir3_register *">
<map name="CONST">src->num >> 2</map>
<map name="SWIZ">src->num &amp; 0x3</map>
</encode>
</bitset>
<expr name="#offset-zero">
{OFFSET} == 0
</expr>
<bitset name="#reg-relative-gpr" size="10">
<override expr="#offset-zero">
<display>
r&lt;a0.x&gt;
</display>
</override>
<display>
r&lt;a0.x + {OFFSET}&gt;
</display>
<field name="OFFSET" low="0" high="9" type="int"/>
<encode type="struct ir3_register *">
<map name="OFFSET">src->array.offset</map>
</encode>
</bitset>
<bitset name="#reg-relative-const" size="10">
<override expr="#offset-zero">
<display>
c&lt;a0.x&gt;
</display>
</override>
<display>
c&lt;a0.x + {OFFSET}&gt;
</display>
<field name="OFFSET" low="0" high="9" type="int"/>
<encode type="struct ir3_register *">
<map name="OFFSET">src->array.offset</map>
</encode>
</bitset>
<!--
Source Register encoding, used in cat2 and cat4 where a src can be
either gpr/const/relative
-->
<bitset name="#multisrc" size="16">
<doc>
Encoding for instruction source which can be GPR/CONST/IMMED
or relative GPR/CONST.
</doc>
<encode type="struct ir3_register *" case-prefix="REG_">
<map name="ABSNEG">extract_ABSNEG(src)</map>
<map name="SRC">src</map>
</encode>
</bitset>
<bitset name="#mulitsrc-immed" extends="#multisrc">
<override expr="#multisrc-half">
<display>
{ABSNEG}{SRC_R}h({IMMED})
</display>
</override>
<display>
{ABSNEG}{SRC_R}{IMMED}
</display>
<field name="IMMED" low="0" high="10" type="int"/>
<pattern low="11" high="13">100</pattern>
<field name="ABSNEG" low="14" high="15" type="#absneg"/>
<encode>
<map name="IMMED">src->uim_val</map>
</encode>
</bitset>
<bitset name="#mulitsrc-immed-flut" extends="#multisrc">
<doc>
Immediate with int->float lookup table:
0 -> 0.0
1 -> 0.5
2 -> 1.0
3 -> 2.0
4 -> e
5 -> pi
6 -> 1/pi
7 -> 1/log2(e)
8 -> log2(e)
9 -> 1/log2(10)
10 -> log2(10)
11 -> 4.0
</doc>
<field name="IMMED" low="0" high="9" type="#flut"/>
<pattern low="11" high="13">101</pattern>
<field name="ABSNEG" low="14" high="15" type="#absneg"/>
<encode>
<map name="IMMED">src->uim_val</map>
</encode>
</bitset>
<bitset name="#multisrc-immed-flut-full" extends="#mulitsrc-immed-flut">
<display>
{ABSNEG}{SRC_R}{IMMED}
</display>
<pattern pos="10">0</pattern>
</bitset>
<bitset name="#multisrc-immed-flut-half" extends="#mulitsrc-immed-flut">
<display>
{ABSNEG}{SRC_R}h{IMMED}
</display>
<pattern pos="10">1</pattern>
</bitset>
<expr name="#multisrc-half">
!{FULL}
</expr>
<bitset name="#multisrc-gpr" extends="#multisrc">
<display>
{ABSNEG}{SRC_R}{HALF}{SRC}
</display>
<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
<field name="SRC" low="0" high="7" type="#reg-gpr"/>
<pattern low="8" high="13">000000</pattern>
<field name="ABSNEG" low="14" high="15" type="#absneg"/>
</bitset>
<bitset name="#multisrc-const" extends="#multisrc">
<display>
{ABSNEG}{SRC_R}{HALF}{SRC}
</display>
<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
<field name="SRC" low="0" high="10" type="#reg-const"/>
<pattern low="11" high="13">x10</pattern>
<field name="ABSNEG" low="14" high="15" type="#absneg"/>
</bitset>
<bitset name="#multisrc-relative" extends="#multisrc">
<pattern low="11" high="13">001</pattern>
<field name="ABSNEG" low="14" high="15" type="#absneg"/>
</bitset>
<bitset name="#multisrc-relative-gpr" extends="#multisrc-relative">
<display>
{ABSNEG}{SRC_R}{HALF}{SRC}
</display>
<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
<field name="SRC" low="0" high="9" type="#reg-relative-gpr"/>
<pattern pos="10">0</pattern>
</bitset>
<bitset name="#multisrc-relative-const" extends="#multisrc-relative">
<display>
{ABSNEG}{SRC_R}{HALF}{SRC}
</display>
<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
<field name="SRC" low="0" high="9" type="#reg-relative-const"/>
<pattern pos="10">1</pattern>
</bitset>
<!--
For cat2/cat4, the dst reg is full precision if {FULL} == {DEST_CONV}
In addition, for cat2 instructions that can write p0.x (cmps.*, and.b,
xor.b, etc), p0.x is never half (DEST_CONV is ignored)
-->
<expr name="#dest-half">
({FULL} == {DST_CONV}) &amp;&amp; ({DST} &lt;= 0xf7 /* p0.x */)
</expr>
<expr name="#true">
1
</expr>
<expr name="#false">
0
</expr>
<!-- These make #true/#false a bit redundant, but I guess keep them for clarity -->
<expr name="#zero">
0
</expr>
<expr name="#one">
1
</expr>
<expr name="#two">
2
</expr>
<!--
Enums used in various places:
-->
<enum name="#rptN">
<value val="0" display=""/>
<value val="1" display="(rpt1)"/>
<value val="2" display="(rpt2)"/>
<value val="3" display="(rpt3)"/>
<value val="4" display="(rpt4)"/>
<value val="5" display="(rpt5)"/>
</enum>
<enum name="#cond">
<value val="0" display="lt"/>
<value val="1" display="le"/>
<value val="2" display="gt"/>
<value val="3" display="ge"/>
<value val="4" display="eq"/>
<value val="5" display="ne"/>
</enum>
<enum name="#swiz">
<value val="0" display="x"/>
<value val="1" display="y"/>
<value val="2" display="z"/>
<value val="3" display="w"/>
</enum>
<enum name="#type">
<value val="0" display="f16"/>
<value val="1" display="f32"/>
<value val="2" display="u16"/>
<value val="3" display="u32"/>
<value val="4" display="s16"/>
<value val="5" display="s32"/>
<value val="6" display="u8"/>
<value val="7" display="s8"/>
</enum>
<enum name="#absneg">
<value val="0" display=""/>
<value val="1" display="(neg)"/>
<value val="2" display="(abs)"/>
<value val="3" display="(absneg)"/>
</enum>
<enum name="#flut">
<doc>int to float lookup table</doc>
<value val="0" display="(0.0)"/>
<value val="1" display="(0.5)"/>
<value val="2" display="(1.0)"/>
<value val="3" display="(2.0)"/>
<value val="4" display="(e)"/>
<value val="5" display="(pi)"/>
<value val="6" display="(1/pi)"/>
<value val="7" display="(1/log2(e))"/>
<value val="8" display="(log2(e))"/>
<value val="9" display="(1/log2(10))"/>
<value val="10" display="(log2(10))"/>
<value val="11" display="(4.0)"/>
</enum>
<enum name="#wrmask">
<value val="0" display=""/>
<value val="1" display="x"/>
<value val="2" display="y"/>
<value val="3" display="xy"/>
<value val="4" display="z"/>
<value val="5" display="zx"/>
<value val="6" display="zy"/>
<value val="7" display="xyz"/>
<value val="8" display="w"/>
<value val="9" display="xw"/>
<value val="10" display="yw"/>
<value val="11" display="xyw"/>
<value val="12" display="zw"/>
<value val="13" display="xzw"/>
<value val="14" display="yzw"/>
<value val="15" display="xyzw"/>
</enum>
</isa>

90
src/freedreno/isa/ir3.xml Normal file
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@ -0,0 +1,90 @@
<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright © 2020 Google, Inc.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
-->
<!--
The basic idea is to define a hierarchy of encodings, where various
ranges of bits can be either:
* patterns to match to select a sub-encoding (0, 1, x (dontcare))
* instruction parameters (ie. dst register, type, etc)
* range of bits that delegates to another hierarchy (ie. src reg
encoding which has multiple sub-encodings depending on gpr/const/
relative)
The root of the encoding hierarchy defines the size. By the concrete
leaf nodes of an encoding hierarchy all bits should be accounted for
(ie. either defined fields or as 0/1/x).
TODO:
* add optional min/max gen fields for cases where same binary maps
to different instructions and/or encodings on later gens
* schema
-->
<isa>
<import file="ir3-common.xml"/>
<bitset name="#instruction" size="64">
<doc>
Encoding of an ir3 instruction. All instructions are 64b.
</doc>
<gen min="300"/>
<encode type="struct ir3_instruction *" case-prefix="OPC_">
<!--
Define mapping from encode src to individual fields,
which are common across all instruction categories
at the root instruction level
Not all of these apply to all instructions, but we
can define mappings here for anything that is used
in more than one instruction category. For things
that are specific to a single instruction category,
mappings should be defined at that level instead.
-->
<map name="DST">src->regs[0]</map>
<map name="SRC1">src->regs[1]</map>
<map name="SRC2">src->regs[2]</map>
<map name="SRC3">src->regs[3]</map>
<map name="REPEAT">src->repeat</map>
<map name="SS">!!(src->flags &amp; IR3_INSTR_SS)</map>
<map name="JP">!!(src->flags &amp; IR3_INSTR_JP)</map>
<map name="SY">!!(src->flags &amp; IR3_INSTR_SY)</map>
<map name="UL">!!(src->flags &amp; IR3_INSTR_UL)</map>
<map name="EQ">0</map> <!-- We don't use this (yet) -->
<map name="SAT">!!(src->flags &amp; IR3_INSTR_SAT)</map>
</encode>
</bitset>
<import file="ir3-cat0.xml"/>
<import file="ir3-cat1.xml"/>
<import file="ir3-cat2.xml"/>
<import file="ir3-cat3.xml"/>
<import file="ir3-cat4.xml"/>
<import file="ir3-cat5.xml"/>
<import file="ir3-cat6.xml"/>
<import file="ir3-cat7.xml"/>
</isa>

103
src/freedreno/isa/meson.build Normal file
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@ -0,0 +1,103 @@
# Copyright © 2020 Google, Inc
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
isa_depend_files = [
'ir3-common.xml',
'ir3-cat0.xml',
'ir3-cat1.xml',
'ir3-cat2.xml',
'ir3-cat3.xml',
'ir3-cat4.xml',
'ir3-cat5.xml',
'ir3-cat6.xml',
'ir3-cat7.xml',
'isa.py',
]
ir3_isa_c = custom_target(
'ir3-isa.c',
input: ['decode.py', 'ir3.xml'],
output: 'ir3-isa.c',
command: [
prog_python, '@INPUT0@', '@INPUT1@', '@OUTPUT@'
],
depend_files: isa_depend_files,
)
decode_files = [
ir3_isa_c,
'isa.h',
'decode.h',
'decode.c',
]
libir3decode = static_library(
'ir3decode',
decode_files,
dependencies: idep_mesautil,
include_directories: [
inc_include,
inc_src,
# Hack for src/util/half_float.h indirect dependency on
# gallium headers:
inc_gallium,
],
gnu_symbol_visibility: 'hidden',
)
ir3disasm = executable(
'ir3-disasm',
['ir3-disasm.c'],
link_with: libir3decode,
build_by_default: with_tools.contains('freedreno'),
include_directories: [
inc_src,
],
install: false,
)
encode_h = custom_target(
'encode.h',
input: ['encode.py', 'ir3.xml'],
output: 'encode.h',
command: [
prog_python, '@INPUT0@', '@INPUT1@', '@OUTPUT@'
],
depend_files: isa_depend_files,
)
encode_files = [
encode_h,
'encode.c',
'isa.h',
]
libir3encode = static_library(
'ir3encode',
encode_files,
dependencies: [idep_mesautil, idep_nir],
include_directories: [
inc_src,
inc_include,
inc_freedreno,
inc_gallium,
],
gnu_symbol_visibility: 'hidden',
)

1
src/freedreno/meson.build
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@ -42,6 +42,7 @@ install_fd_decode_tools = dep_libxml2.found() and prog_gzip.found() and \
subdir('common')
subdir('registers')
subdir('isa')
subdir('drm')
subdir('ir2')
subdir('ir3')