radeonsi/gfx9: workaround for INTERP with indirect indexing
and clean up the conditions. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
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@ -477,12 +477,19 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
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case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
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/* TODO: Indirect indexing of GS inputs is unimplemented. */
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return shader != PIPE_SHADER_GEOMETRY &&
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(sscreen->llvm_has_working_vgpr_indexing ||
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/* TCS and TES load inputs directly from LDS or
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* offchip memory, so indirect indexing is trivial. */
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shader == PIPE_SHADER_TESS_CTRL ||
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shader == PIPE_SHADER_TESS_EVAL);
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if (shader == PIPE_SHADER_GEOMETRY)
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return 0;
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if (shader == PIPE_SHADER_VERTEX &&
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!sscreen->llvm_has_working_vgpr_indexing)
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return 0;
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/* TCS and TES load inputs directly from LDS or offchip
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* memory, so indirect indexing is always supported.
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* PS has to support indirect indexing, because we can't
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* lower that to TEMPs for INTERP instructions.
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*/
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return 1;
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case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
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return sscreen->llvm_has_working_vgpr_indexing ||
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